274 		rtl_set_bbreg(hw, addr, MASKDWORD, data);  in _rtl8723be_config_bb_reg()
798 					      MASKDWORD);  in rtl8723be_phy_get_hw_reg_originalvalue()
1453 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1455 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1465 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_a_iqk()
1466 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_iqk()
1468 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_iqk()
1469 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1470 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1471 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_iqk()
1473 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);  in _rtl8723be_phy_path_a_iqk()
1474 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);  in _rtl8723be_phy_path_a_iqk()
1475 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_iqk()
1476 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_iqk()
1478 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl8723be_phy_path_a_iqk()
1480 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_iqk()
1483 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_iqk()
1484 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_iqk()
1489 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_iqk()
1492 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1493 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1494 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl8723be_phy_path_a_iqk()
1526 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1529 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1538 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1541 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_a_rx_iqk()
1542 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_rx_iqk()
1545 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1546 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1547 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1548 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1550 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);  in _rtl8723be_phy_path_a_rx_iqk()
1551 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1552 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1553 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1556 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl8723be_phy_path_a_rx_iqk()
1559 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1562 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_rx_iqk()
1563 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_rx_iqk()
1568 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1571 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1572 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1573 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1597 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);  in _rtl8723be_phy_path_a_rx_iqk()
1601 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1613 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_a_rx_iqk()
1616 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1617 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1618 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1619 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_a_rx_iqk()
1621 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1622 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);  in _rtl8723be_phy_path_a_rx_iqk()
1623 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_a_rx_iqk()
1624 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_a_rx_iqk()
1627 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);  in _rtl8723be_phy_path_a_rx_iqk()
1630 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_a_rx_iqk()
1633 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_a_rx_iqk()
1634 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_a_rx_iqk()
1639 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1642 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1643 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_a_rx_iqk()
1646 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_a_rx_iqk()
1673 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1675 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);  in _rtl8723be_phy_path_b_iqk()
1683 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_b_iqk()
1684 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_iqk()
1686 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_iqk()
1687 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1688 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1689 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_iqk()
1691 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x821403ea);  in _rtl8723be_phy_path_b_iqk()
1692 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_iqk()
1693 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_iqk()
1694 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_iqk()
1697 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl8723be_phy_path_b_iqk()
1700 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_iqk()
1703 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_iqk()
1704 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_iqk()
1709 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_iqk()
1712 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1713 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1714 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_iqk()
1746 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1748 	rtl_set_bbreg(hw, 0x948, MASKDWORD, 0x00000280);  in _rtl8723be_phy_path_b_rx_iqk()
1762 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl8723be_phy_path_b_rx_iqk()
1763 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_rx_iqk()
1766 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1767 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1768 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1769 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1771 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160ff0);  in _rtl8723be_phy_path_b_rx_iqk()
1772 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1773 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1774 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1777 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl8723be_phy_path_b_rx_iqk()
1779 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1782 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_rx_iqk()
1783 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_rx_iqk()
1788 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1790 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1791 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1792 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1816 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32tmp);  in _rtl8723be_phy_path_b_rx_iqk()
1821 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1833 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl8723be_phy_path_b_rx_iqk()
1836 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1837 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1838 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1839 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl8723be_phy_path_b_rx_iqk()
1841 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1842 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x2816001f);  in _rtl8723be_phy_path_b_rx_iqk()
1843 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000);  in _rtl8723be_phy_path_b_rx_iqk()
1844 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28110000);  in _rtl8723be_phy_path_b_rx_iqk()
1847 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a8d1);  in _rtl8723be_phy_path_b_rx_iqk()
1849 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl8723be_phy_path_b_rx_iqk()
1852 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl8723be_phy_path_b_rx_iqk()
1853 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl8723be_phy_path_b_rx_iqk()
1858 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl8723be_phy_path_b_rx_iqk()
1860 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1861 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl8723be_phy_path_b_rx_iqk()
1897 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl8723be_phy_path_b_fill_iqk_matrix()
2049 	path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);  in _rtl8723be_phy_iq_calibrate()
2055 	rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);  in _rtl8723be_phy_iq_calibrate()
2056 	rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);  in _rtl8723be_phy_iq_calibrate()
2057 	rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);  in _rtl8723be_phy_iq_calibrate()
2065 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2067 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2081 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2083 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2102 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2105 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2119 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2122 							      MASKDWORD) &  in _rtl8723be_phy_iq_calibrate()
2132 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl8723be_phy_iq_calibrate()
2143 		rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);  in _rtl8723be_phy_iq_calibrate()
2152 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);  in _rtl8723be_phy_iq_calibrate()
2153 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);  in _rtl8723be_phy_iq_calibrate()
2239 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x1);  in _rtl8723be_phy_set_rfpath_switch()
2241 		rtl_set_bbreg(hw, 0x92C, MASKDWORD, 0x2);  in _rtl8723be_phy_set_rfpath_switch()
2283 	path_sel_bb = rtl_get_bbreg(hw, 0x948, MASKDWORD);  in rtl8723be_phy_iq_calibrate()
2385 	rtl_set_bbreg(hw, 0x948, MASKDWORD, path_sel_bb);  in rtl8723be_phy_iq_calibrate()