69 	if (bitmask != MASKDWORD) {  in rtl92ee_phy_set_bb_reg()
154 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
158 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
161 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in _rtl92ee_phy_rf_serial_read()
164 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in _rtl92ee_phy_rf_serial_read()
201 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in _rtl92ee_phy_rf_serial_write()
302 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);  in _rtl92ee_config_rf_reg()
311 							 MASKDWORD);  in _rtl92ee_config_rf_reg()
321 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);  in _rtl92ee_config_rf_reg()
333 							 MASKDWORD);  in _rtl92ee_config_rf_reg()
377 		rtl_set_bbreg(hw, addr, MASKDWORD , data);  in _rtl92ee_config_bb_reg()
740 				rtl_set_bbreg(hw, array[i], MASKDWORD,  in phy_config_bb_with_hdr_file()
770 							      MASKDWORD,  in phy_config_bb_with_hdr_file()
1041 					      ROFDM0_RXDETECTOR2, MASKDWORD);  in rtl92ee_phy_get_hw_reg_originalvalue()
1949 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_iqk()
1951 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_iqk()
1953 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_iqk()
1954 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1955 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1956 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_iqk()
1958 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303);  in _rtl92ee_phy_path_a_iqk()
1959 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000);  in _rtl92ee_phy_path_a_iqk()
1962 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl92ee_phy_path_a_iqk()
1965 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);  in _rtl92ee_phy_path_a_iqk()
1966 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_iqk()
1970 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1971 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1972 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1990 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
1992 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
1994 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
1995 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
1997 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
1998 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
1999 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_iqk()
2000 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_iqk()
2002 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2);  in _rtl92ee_phy_path_b_iqk()
2003 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000);  in _rtl92ee_phy_path_b_iqk()
2006 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);  in _rtl92ee_phy_path_b_iqk()
2009 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_iqk()
2010 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_iqk()
2014 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2015 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2016 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2035 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2047 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2050 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_path_a_rx_iqk()
2051 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_a_rx_iqk()
2054 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2055 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2056 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2057 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2059 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2060 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2063 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl92ee_phy_path_a_rx_iqk()
2066 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_a_rx_iqk()
2067 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_rx_iqk()
2072 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2073 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2074 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2082 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2089 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);  in _rtl92ee_phy_path_a_rx_iqk()
2092 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2105 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2108 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_a_rx_iqk()
2111 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2112 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2113 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2114 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_a_rx_iqk()
2116 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2117 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f);  in _rtl92ee_phy_path_a_rx_iqk()
2120 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);  in _rtl92ee_phy_path_a_rx_iqk()
2122 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_a_rx_iqk()
2123 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_a_rx_iqk()
2127 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2128 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2132 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2151 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2162 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2165 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_path_b_rx_iqk()
2166 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_b_rx_iqk()
2169 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2170 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2171 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2172 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2174 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2175 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2178 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);  in _rtl92ee_phy_path_b_rx_iqk()
2181 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_rx_iqk()
2182 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_rx_iqk()
2187 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2188 	reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2189 	reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2197 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2204 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);  in _rtl92ee_phy_path_b_rx_iqk()
2207 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2219 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2222 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_path_b_rx_iqk()
2225 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2226 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2227 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2228 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c);  in _rtl92ee_phy_path_b_rx_iqk()
2230 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2231 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f);  in _rtl92ee_phy_path_b_rx_iqk()
2234 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);  in _rtl92ee_phy_path_b_rx_iqk()
2236 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);  in _rtl92ee_phy_path_b_rx_iqk()
2237 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);  in _rtl92ee_phy_path_b_rx_iqk()
2241 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2242 	reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2243 	reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2246 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2271 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl92ee_phy_path_a_fill_iqk_matrix()
2316 					  MASKDWORD) >> 22) & 0x3FF;  in _rtl92ee_phy_path_b_fill_iqk_matrix()
2356 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in _rtl92ee_phy_save_adda_registers()
2378 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);  in _rtl92ee_phy_reload_adda_registers()
2398 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616);  in _rtl92ee_phy_path_adda_on()
2409 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);  in _rtl92ee_phy_path_a_standby()
2411 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_standby()
2530 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);  in _rtl92ee_phy_iq_calibrate()
2531 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);  in _rtl92ee_phy_iq_calibrate()
2532 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);  in _rtl92ee_phy_iq_calibrate()
2543 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2544 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_iq_calibrate()
2545 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_iq_calibrate()
2555 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2558 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2575 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2579 						      MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2597 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2598 		rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);  in _rtl92ee_phy_iq_calibrate()
2599 		rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);  in _rtl92ee_phy_iq_calibrate()
2608 							MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2612 							MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2628 						       MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2632 						       MASKDWORD) & 0x3FF0000)  in _rtl92ee_phy_iq_calibrate()
2648 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl92ee_phy_iq_calibrate()
2673 		rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);  in _rtl92ee_phy_iq_calibrate()
2674 		rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);  in _rtl92ee_phy_iq_calibrate()