Lines Matching refs:MASKDWORD
221 if (bitmask != MASKDWORD) { in rtl92d_phy_set_bb_reg()
254 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); in _rtl92d_phy_rf_serial_read()
258 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); in _rtl92d_phy_rf_serial_read()
261 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
264 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92d_phy_rf_serial_read()
267 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
300 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92d_phy_rf_serial_write()
547 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
559 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
575 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
591 MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
842 MASKDWORD); in rtl92d_phy_get_hw_reg_originalvalue()
1400 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1401 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1403 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1404 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1406 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1407 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1410 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1411 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1412 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1413 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1417 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1420 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1421 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1428 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
1430 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
1432 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
1434 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
1470 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1471 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1472 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1473 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1476 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1477 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1478 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1479 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1483 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1485 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1486 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1491 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1492 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1499 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1501 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1503 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1505 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1527 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1529 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1544 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1545 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1551 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1553 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1555 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1557 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1559 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1587 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1588 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1589 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1590 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1593 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1594 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1595 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1596 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1600 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1603 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1604 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1610 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1611 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1619 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1621 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1623 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1625 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1627 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1645 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1647 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1661 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); in _rtl92d_phy_save_adda_registers()
1686 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92d_phy_reload_adda_registers()
1714 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); in _rtl92d_phy_path_adda_on()
1737 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1738 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1739 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1750 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1751 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1782 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); in _rtl92d_phy_iq_calibrate()
1805 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1806 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1807 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1810 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1812 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1819 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1821 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1824 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1825 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1826 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1832 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1834 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1836 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1838 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1846 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1848 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1864 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1866 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1868 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1870 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1877 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1879 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1891 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1911 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1912 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1949 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); in _rtl92d_phy_iq_calibrate_5g_normal()
1979 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1980 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1981 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1985 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1987 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1990 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1991 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1992 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1996 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1998 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2000 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2002 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2008 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2010 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2023 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2025 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2027 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2029 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2034 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2036 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2047 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2147 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
2178 MASKDWORD)); in _rtl92d_phy_patha_fill_iqk_matrix()
2206 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2860 MASKDWORD); in rtl92d_phy_sw_chnl()
3368 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3370 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3424 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3427 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3430 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3433 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3460 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3461 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()