Lines Matching refs:rtl8xxxu_write32
371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
382 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8723b_set_tx_power()
383 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8723b_set_tx_power()
392 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8723b_set_tx_power()
393 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8723b_set_tx_power()
491 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_init_phy_bb()
527 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
531 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
535 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
539 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
543 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
547 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723bu_phy_init_antenna_selection()
552 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); in rtl8723bu_phy_init_antenna_selection()
556 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
571 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
586 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_iqk_path_a()
587 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_iqk_path_a()
590 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_iqk_path_a()
591 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_iqk_path_a()
592 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
593 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
595 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); in rtl8723bu_iqk_path_a()
596 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_iqk_path_a()
597 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_iqk_path_a()
598 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_iqk_path_a()
601 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8723bu_iqk_path_a()
609 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
616 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_iqk_path_a()
618 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_iqk_path_a()
624 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_iqk_path_a()
627 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_iqk_path_a()
628 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_iqk_path_a()
633 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_iqk_path_a()
636 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_iqk_path_a()
644 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
681 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
696 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_rx_iqk_path_a()
697 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
700 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
701 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
702 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
703 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
705 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); in rtl8723bu_rx_iqk_path_a()
706 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_rx_iqk_path_a()
707 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
708 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
711 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8723bu_rx_iqk_path_a()
719 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
726 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
728 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
734 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
737 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
738 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
743 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
746 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
754 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
777 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
784 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
801 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
804 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
805 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
806 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
807 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); in rtl8723bu_rx_iqk_path_a()
810 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); in rtl8723bu_rx_iqk_path_a()
811 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
812 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
815 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); in rtl8723bu_rx_iqk_path_a()
823 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
826 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
828 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
833 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
836 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
837 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
842 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
853 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
929 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8723bu_phy_iqcalibrate()
931 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8723bu_phy_iqcalibrate()
932 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8723bu_phy_iqcalibrate()
933 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8723bu_phy_iqcalibrate()
941 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
962 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1005 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1011 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1051 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1068 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1069 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
1074 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1076 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1081 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1082 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1191 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); in rtl8723bu_phy_iq_calibrate()
1228 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723bu_active_to_emu()
1294 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1315 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1320 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1325 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1330 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1426 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_power_on()
1436 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
1495 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8723b_enable_rf()
1539 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723b_enable_rf()
1548 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723b_enable_rf()
1555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723b_enable_rf()
1578 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); in rtl8723b_enable_rf()
1587 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); in rtl8723b_enable_rf()
1588 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); in rtl8723b_enable_rf()
1589 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); in rtl8723b_enable_rf()
1619 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8723bu_init_aggregation()
1629 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); in rtl8723bu_init_statistics()
1630 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); in rtl8723bu_init_statistics()
1634 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_init_statistics()
1638 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8723bu_init_statistics()
1642 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8723bu_init_statistics()