Lines Matching refs:rt2x00_set_field32
94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write()
95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write()
96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write()
97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write()
98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write()
123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_read()
124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_read()
125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); in rt2800_bbp_read()
126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_read()
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); in rt2800_rfcsr_write()
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, in rt2800_rfcsr_write()
158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); in rt2800_rfcsr_write()
159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); in rt2800_rfcsr_write()
168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); in rt2800_rfcsr_write()
169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_write()
170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); in rt2800_rfcsr_write()
171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_write()
221 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, in rt2800_rfcsr_read()
223 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); in rt2800_rfcsr_read()
224 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); in rt2800_rfcsr_read()
237 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_read()
238 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); in rt2800_rfcsr_read()
239 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_read()
274 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); in rt2800_rf_write()
275 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); in rt2800_rf_write()
276 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); in rt2800_rf_write()
277 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); in rt2800_rf_write()
441 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); in rt2800_enable_wlan_rt3290()
442 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); in rt2800_enable_wlan_rt3290()
443 rt2x00_set_field32(®, WLAN_CLK_EN, 0); in rt2800_enable_wlan_rt3290()
444 rt2x00_set_field32(®, WLAN_EN, 1); in rt2800_enable_wlan_rt3290()
479 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); in rt2800_enable_wlan_rt3290()
480 rt2x00_set_field32(®, WLAN_CLK_EN, 1); in rt2800_enable_wlan_rt3290()
481 rt2x00_set_field32(®, WLAN_RESET, 1); in rt2800_enable_wlan_rt3290()
484 rt2x00_set_field32(®, WLAN_RESET, 0); in rt2800_enable_wlan_rt3290()
512 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt2800_mcu_request()
513 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt2800_mcu_request()
514 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt2800_mcu_request()
515 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt2800_mcu_request()
519 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt2800_mcu_request()
572 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_disable_wpdma()
573 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_disable_wpdma()
574 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_disable_wpdma()
575 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_disable_wpdma()
576 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_disable_wpdma()
723 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800_load_firmware()
724 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800_load_firmware()
784 rt2x00_set_field32(&word, TXWI_W0_FRAG, in rt2800_write_tx_data()
786 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, in rt2800_write_tx_data()
788 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); in rt2800_write_tx_data()
789 rt2x00_set_field32(&word, TXWI_W0_TS, in rt2800_write_tx_data()
791 rt2x00_set_field32(&word, TXWI_W0_AMPDU, in rt2800_write_tx_data()
793 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, in rt2800_write_tx_data()
795 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); in rt2800_write_tx_data()
796 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); in rt2800_write_tx_data()
797 rt2x00_set_field32(&word, TXWI_W0_BW, in rt2800_write_tx_data()
799 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, in rt2800_write_tx_data()
801 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); in rt2800_write_tx_data()
802 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); in rt2800_write_tx_data()
806 rt2x00_set_field32(&word, TXWI_W1_ACK, in rt2800_write_tx_data()
808 rt2x00_set_field32(&word, TXWI_W1_NSEQ, in rt2800_write_tx_data()
810 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); in rt2800_write_tx_data()
811 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, in rt2800_write_tx_data()
814 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, in rt2800_write_tx_data()
816 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); in rt2800_write_tx_data()
817 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); in rt2800_write_tx_data()
1315 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, in rt2800_update_beacons_setup()
1335 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_write_beacon()
1425 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_clear_beacon()
1527 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); in rt2800_brightness_set()
1531 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, in rt2800_brightness_set()
1534 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, in rt2800_brightness_set()
1537 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, in rt2800_brightness_set()
1614 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); in rt2800_config_wcid_attr_bssidx()
1615 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, in rt2800_config_wcid_attr_bssidx()
1632 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, in rt2800_config_wcid_attr_cipher()
1639 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, in rt2800_config_wcid_attr_cipher()
1641 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, in rt2800_config_wcid_attr_cipher()
1643 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); in rt2800_config_wcid_attr_cipher()
1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); in rt2800_config_wcid_attr_cipher()
1649 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); in rt2800_config_wcid_attr_cipher()
1650 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); in rt2800_config_wcid_attr_cipher()
1651 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); in rt2800_config_wcid_attr_cipher()
1710 rt2x00_set_field32(®, field, in rt2800_config_shared_key()
1776 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); in rt2800_set_max_psdu_len()
1890 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, in rt2800_config_filter()
1892 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, in rt2800_config_filter()
1894 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, in rt2800_config_filter()
1896 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); in rt2800_config_filter()
1897 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); in rt2800_config_filter()
1898 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, in rt2800_config_filter()
1900 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); in rt2800_config_filter()
1901 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); in rt2800_config_filter()
1902 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, in rt2800_config_filter()
1904 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, in rt2800_config_filter()
1906 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, in rt2800_config_filter()
1908 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, in rt2800_config_filter()
1910 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, in rt2800_config_filter()
1912 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, in rt2800_config_filter()
1914 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); in rt2800_config_filter()
1915 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, in rt2800_config_filter()
1917 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, in rt2800_config_filter()
1934 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); in rt2800_config_intf()
1942 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); in rt2800_config_intf()
1943 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); in rt2800_config_intf()
1944 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1945 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); in rt2800_config_intf()
1949 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); in rt2800_config_intf()
1950 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); in rt2800_config_intf()
1951 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1952 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); in rt2800_config_intf()
1970 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); in rt2800_config_intf()
1981 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); in rt2800_config_intf()
1982 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); in rt2800_config_intf()
2068 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); in rt2800_config_ht_opmode()
2069 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); in rt2800_config_ht_opmode()
2073 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); in rt2800_config_ht_opmode()
2074 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); in rt2800_config_ht_opmode()
2078 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); in rt2800_config_ht_opmode()
2079 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); in rt2800_config_ht_opmode()
2083 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); in rt2800_config_ht_opmode()
2084 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); in rt2800_config_ht_opmode()
2095 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, in rt2800_config_erp()
2102 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, in rt2800_config_erp()
2115 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, in rt2800_config_erp()
2120 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); in rt2800_config_erp()
2126 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800_config_erp()
2144 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); in rt2800_config_3572bt_ant()
2145 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); in rt2800_config_3572bt_ant()
2147 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); in rt2800_config_3572bt_ant()
2148 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); in rt2800_config_3572bt_ant()
2160 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); in rt2800_config_3572bt_ant()
2161 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); in rt2800_config_3572bt_ant()
2179 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); in rt2800_set_ant_diversity()
2186 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_set_ant_diversity()
2187 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); in rt2800_set_ant_diversity()
2356 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt2800_config_channel_rf2xxx()
2359 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); in rt2800_config_channel_rf2xxx()
2362 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); in rt2800_config_channel_rf2xxx()
2363 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
2365 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
2374 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2380 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); in rt2800_config_channel_rf2xxx()
2382 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2388 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); in rt2800_config_channel_rf2xxx()
2390 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); in rt2800_config_channel_rf2xxx()
2391 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); in rt2800_config_channel_rf2xxx()
2394 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); in rt2800_config_channel_rf2xxx()
2654 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel_rf3052()
2656 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel_rf3052()
2658 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); in rt2800_config_channel_rf3052()
3368 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, in rt2800_config_channel_rf55xx()
3807 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); in rt2800_config_alc()
3808 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); in rt2800_config_alc()
3809 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); in rt2800_config_alc()
3810 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, max_power); in rt2800_config_alc()
3817 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); in rt2800_config_alc()
3818 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); in rt2800_config_alc()
3823 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); in rt2800_config_alc()
4200 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); in rt2800_config_channel()
4201 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); in rt2800_config_channel()
4202 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); in rt2800_config_channel()
4210 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); in rt2800_config_channel()
4218 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, in rt2800_config_channel()
4220 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, in rt2800_config_channel()
4225 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, in rt2800_config_channel()
4227 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, in rt2800_config_channel()
4232 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, in rt2800_config_channel()
4235 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_config_channel()
4237 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, in rt2800_config_channel()
4245 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); in rt2800_config_channel()
4246 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); in rt2800_config_channel()
4250 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); in rt2800_config_channel()
4251 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); in rt2800_config_channel()
4255 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); in rt2800_config_channel()
4256 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); in rt2800_config_channel()
4260 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); in rt2800_config_channel()
4261 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); in rt2800_config_channel()
4284 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); in rt2800_config_channel()
4286 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); in rt2800_config_channel()
4288 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); in rt2800_config_channel()
4296 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
4297 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel()
4299 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
4300 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel()
4303 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
4304 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
4689 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4691 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4693 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4700 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4702 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4704 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4711 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4713 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4715 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4722 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4724 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4726 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4737 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4739 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4741 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4748 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4750 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4752 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4759 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4761 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4763 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4774 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4776 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4778 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4785 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4787 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4789 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4796 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4798 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4800 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4807 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4809 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4811 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4822 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4824 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4826 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4833 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4835 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4837 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4844 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4846 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4848 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4855 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4857 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4859 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4870 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4872 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4874 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4881 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4883 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4885 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4892 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
4894 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
4896 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
4903 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
4905 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
4907 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
4918 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
4920 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
4922 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
4929 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
4931 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
4933 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
4940 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4942 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4944 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
4955 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4957 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4959 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4966 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4968 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4970 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
4977 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt3593()
4978 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt3593()
4979 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, in rt2800_config_txpower_rt3593()
4986 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt3593()
4987 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt3593()
4988 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, in rt2800_config_txpower_rt3593()
4999 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5001 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5003 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5137 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); in rt2800_config_txpower_rt6352()
5142 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); in rt2800_config_txpower_rt6352()
5149 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); in rt2800_config_txpower_rt6352()
5156 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); in rt2800_config_txpower_rt6352()
5264 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt28xx()
5275 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt28xx()
5286 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt28xx()
5297 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt28xx()
5314 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); in rt2800_config_txpower_rt28xx()
5325 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); in rt2800_config_txpower_rt28xx()
5336 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); in rt2800_config_txpower_rt28xx()
5347 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); in rt2800_config_txpower_rt28xx()
5443 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); in rt2800_vco_calibration()
5446 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); in rt2800_vco_calibration()
5450 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_vco_calibration()
5456 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); in rt2800_vco_calibration()
5459 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); in rt2800_vco_calibration()
5463 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); in rt2800_vco_calibration()
5514 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, in rt2800_config_retry_limit()
5516 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, in rt2800_config_retry_limit()
5533 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); in rt2800_config_ps()
5534 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, in rt2800_config_ps()
5536 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); in rt2800_config_ps()
5542 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); in rt2800_config_ps()
5543 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); in rt2800_config_ps()
5544 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); in rt2800_config_ps()
5721 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); in rt2800_init_registers()
5722 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800_init_registers()
5723 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); in rt2800_init_registers()
5724 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800_init_registers()
5725 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_init_registers()
5726 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); in rt2800_init_registers()
5732 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); in rt2800_init_registers()
5733 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); in rt2800_init_registers()
5739 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); in rt2800_init_registers()
5745 rt2x00_set_field32(®, LDO0_EN, 1); in rt2800_init_registers()
5746 rt2x00_set_field32(®, LDO_BGSEL, 3); in rt2800_init_registers()
5751 rt2x00_set_field32(®, OSC_ROSC_EN, 1); in rt2800_init_registers()
5752 rt2x00_set_field32(®, OSC_CAL_REQ, 1); in rt2800_init_registers()
5753 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); in rt2800_init_registers()
5757 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); in rt2800_init_registers()
5761 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); in rt2800_init_registers()
5762 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); in rt2800_init_registers()
5763 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); in rt2800_init_registers()
5764 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); in rt2800_init_registers()
5768 rt2x00_set_field32(®, PLL_CONTROL, 1); in rt2800_init_registers()
5869 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); in rt2800_init_registers()
5877 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); in rt2800_init_registers()
5878 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); in rt2800_init_registers()
5879 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); in rt2800_init_registers()
5880 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); in rt2800_init_registers()
5881 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); in rt2800_init_registers()
5882 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); in rt2800_init_registers()
5883 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); in rt2800_init_registers()
5884 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); in rt2800_init_registers()
5888 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); in rt2800_init_registers()
5889 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); in rt2800_init_registers()
5890 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); in rt2800_init_registers()
5894 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); in rt2800_init_registers()
5904 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); in rt2800_init_registers()
5905 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); in rt2800_init_registers()
5906 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); in rt2800_init_registers()
5910 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); in rt2800_init_registers()
5911 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); in rt2800_init_registers()
5912 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); in rt2800_init_registers()
5913 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); in rt2800_init_registers()
5914 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); in rt2800_init_registers()
5915 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); in rt2800_init_registers()
5916 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); in rt2800_init_registers()
5922 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); in rt2800_init_registers()
5923 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); in rt2800_init_registers()
5924 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); in rt2800_init_registers()
5925 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); in rt2800_init_registers()
5926 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); in rt2800_init_registers()
5927 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); in rt2800_init_registers()
5931 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); in rt2800_init_registers()
5932 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); in rt2800_init_registers()
5933 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); in rt2800_init_registers()
5934 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); in rt2800_init_registers()
5935 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); in rt2800_init_registers()
5936 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); in rt2800_init_registers()
5937 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); in rt2800_init_registers()
5941 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
5942 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
5943 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
5944 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
5945 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
5946 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
5947 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
5948 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
5949 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
5950 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
5954 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
5955 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
5956 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
5957 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
5958 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
5959 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
5960 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
5961 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
5962 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
5963 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
5967 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
5968 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
5969 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
5970 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
5971 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
5972 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
5973 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
5974 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
5975 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
5976 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
5980 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
5981 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
5982 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
5983 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
5984 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
5985 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
5986 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
5987 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
5988 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
5989 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
5993 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
5994 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
5995 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
5996 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
5997 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
5998 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
5999 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6000 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6001 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6002 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6006 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
6007 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6008 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6009 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6010 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6011 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6012 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
6013 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6014 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
6015 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6022 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_init_registers()
6023 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_init_registers()
6024 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_init_registers()
6025 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_init_registers()
6026 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); in rt2800_init_registers()
6027 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); in rt2800_init_registers()
6028 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); in rt2800_init_registers()
6029 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); in rt2800_init_registers()
6030 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); in rt2800_init_registers()
6039 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); in rt2800_init_registers()
6040 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); in rt2800_init_registers()
6041 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); in rt2800_init_registers()
6042 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); in rt2800_init_registers()
6043 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); in rt2800_init_registers()
6044 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); in rt2800_init_registers()
6045 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); in rt2800_init_registers()
6046 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); in rt2800_init_registers()
6047 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); in rt2800_init_registers()
6048 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); in rt2800_init_registers()
6060 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); in rt2800_init_registers()
6061 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, in rt2800_init_registers()
6063 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); in rt2800_init_registers()
6076 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); in rt2800_init_registers()
6077 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); in rt2800_init_registers()
6078 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); in rt2800_init_registers()
6079 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); in rt2800_init_registers()
6080 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); in rt2800_init_registers()
6113 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); in rt2800_init_registers()
6117 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); in rt2800_init_registers()
6122 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); in rt2800_init_registers()
6123 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); in rt2800_init_registers()
6124 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); in rt2800_init_registers()
6125 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); in rt2800_init_registers()
6126 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); in rt2800_init_registers()
6127 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); in rt2800_init_registers()
6128 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); in rt2800_init_registers()
6129 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); in rt2800_init_registers()
6133 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); in rt2800_init_registers()
6134 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); in rt2800_init_registers()
6135 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); in rt2800_init_registers()
6136 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); in rt2800_init_registers()
6137 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); in rt2800_init_registers()
6138 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); in rt2800_init_registers()
6139 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); in rt2800_init_registers()
6140 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); in rt2800_init_registers()
6144 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); in rt2800_init_registers()
6145 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); in rt2800_init_registers()
6146 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); in rt2800_init_registers()
6147 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); in rt2800_init_registers()
6148 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); in rt2800_init_registers()
6149 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); in rt2800_init_registers()
6150 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); in rt2800_init_registers()
6151 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); in rt2800_init_registers()
6155 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); in rt2800_init_registers()
6156 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); in rt2800_init_registers()
6157 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); in rt2800_init_registers()
6158 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); in rt2800_init_registers()
6165 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); in rt2800_init_registers()
6166 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); in rt2800_init_registers()
6185 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); in rt2800_init_registers()
6192 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); in rt2800_init_registers()
6193 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); in rt2800_init_registers()
6194 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); in rt2800_init_registers()
6195 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); in rt2800_init_registers()
6196 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); in rt2800_init_registers()
6803 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_init_bbp_53xx()
6804 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); in rt2800_init_bbp_53xx()
6805 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); in rt2800_init_bbp_53xx()
6806 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); in rt2800_init_bbp_53xx()
6808 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); in rt2800_init_bbp_53xx()
6810 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); in rt2800_init_bbp_53xx()
7199 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); in rt2800_led_open_drain_enable()
7532 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
7533 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
7544 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
7549 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
7551 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_30xx()
7556 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_30xx()
7771 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_3390()
7827 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3572()
7828 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
7832 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3572()
7833 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
7896 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); in rt2800_init_rfcsr_3593()
7897 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); in rt2800_init_rfcsr_3593()
7947 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3593()
7948 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3593()
7952 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3593()
9101 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
9102 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_enable_radio()
9108 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); in rt2800_enable_radio()
9109 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); in rt2800_enable_radio()
9110 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_enable_radio()
9114 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
9115 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800_enable_radio()
9147 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); in rt2800_disable_radio()
9148 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_disable_radio()
9193 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); in rt2800_efuse_read()
9194 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); in rt2800_efuse_read()
9195 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); in rt2800_efuse_read()
10265 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); in rt2800_probe_hw()
10347 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); in rt2800_set_rts_threshold()
10351 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
10355 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
10359 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
10363 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
10367 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
10371 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
10414 rt2x00_set_field32(®, field, queue->txop); in rt2800_conf_tx()
10422 rt2x00_set_field32(®, field, queue->aifs); in rt2800_conf_tx()
10426 rt2x00_set_field32(®, field, queue->cw_min); in rt2800_conf_tx()
10430 rt2x00_set_field32(®, field, queue->cw_max); in rt2800_conf_tx()
10437 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); in rt2800_conf_tx()
10438 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); in rt2800_conf_tx()
10439 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); in rt2800_conf_tx()
10440 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); in rt2800_conf_tx()