Lines Matching full:31
11 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
32 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
48 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
68 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
79 #define MT_RXV1_ACID_DET_H BIT(31)
95 #define MT_RXV2_SEL_ANT BIT(31)
101 #define MT_RXV4_RCPI3 GENMASK(31, 24)
159 #define MT_TXD0_P_IDX BIT(31)
166 #define MT_TXD1_OWN_MAC GENMASK(31, 26)
178 #define MT_TXD2_FIX_RATE BIT(31)
195 #define MT_TXD3_SN_VALID BIT(31)
203 #define MT_TXD4_PN_LOW GENMASK(31, 0)
205 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
213 #define MT_TXD6_FIXED_RATE BIT(31)
254 #define MT_TXS0_PID GENMASK(31, 24)
271 #define MT_TXS1_ANT_ID GENMASK(31, 20)
281 #define MT_TXS2_WCID GENMASK(31, 24)
285 #define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)
291 #define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)
300 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)