25 	mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));  in mt76_stop_tx_ac()
31 	mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));  in mt76_start_tx_ac()
51 	mt76_set(dev, MT_ARB_SCR,  in mt7603_mac_set_timing()
135 	mt76_set(dev, addr + 0 * 4, w0);  in mt7603_wtbl_init()
136 	mt76_set(dev, addr + 1 * 4, w1);  in mt7603_wtbl_init()
137 	mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);  in mt7603_wtbl_init()
236 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);  in mt7603_wtbl_set_ps()
274 	mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);  in mt7603_wtbl_clear()
705 	mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */  in mt7603_wtbl_set_rates()
1184 	mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);  in mt7603_pse_reset()
1207 	mt76_set(dev, MT_WPDMA_GLO_CFG,  in mt7603_mac_dma_start()
1221 	mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);  in mt7603_mac_start()
1226 	mt76_set(dev, MT_ARB_SCR,  in mt7603_mac_stop()
1247 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1);  in mt7603_pse_client_reset()
1251 	mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2);  in mt7603_pse_client_reset()
1252 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);  in mt7603_pse_client_reset()
1269 	mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);  in mt7603_dma_sched_reset()
1313 	mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);  in mt7603_mac_watchdog_reset()
1569 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);  in mt7603_cca_stats_reset()
1571 	mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN);  in mt7603_cca_stats_reset()