112 	wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n",  in wil6210_mask_irq_misc()
121 	wil_dbg_irq(wil, "mask_halp\n");  in wil6210_mask_halp()
129 	wil_dbg_irq(wil, "mask_irq_pseudo\n");  in wil6210_mask_irq_pseudo()
164 	wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n",  in wil6210_unmask_irq_misc()
173 	wil_dbg_irq(wil, "unmask_halp\n");  in wil6210_unmask_halp()
181 	wil_dbg_irq(wil, "unmask_irq_pseudo\n");  in wil6210_unmask_irq_pseudo()
190 	wil_dbg_irq(wil, "mask_irq\n");  in wil_mask_irq()
202 	wil_dbg_irq(wil, "unmask_irq\n");  in wil_unmask_irq()
251 	wil_dbg_irq(wil, "configure_interrupt_moderation\n");  in wil_configure_interrupt_moderation()
309 	wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);  in wil6210_irq_rx()
325 		wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n",  in wil6210_irq_rx()
371 	wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);  in wil6210_irq_rx_edma()
380 		wil_dbg_irq(wil, "RX status ring\n");  in wil6210_irq_rx_edma()
422 	wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);  in wil6210_irq_tx_edma()
431 		wil_dbg_irq(wil, "TX status ring\n");  in wil6210_irq_tx_edma()
468 	wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);  in wil6210_irq_tx()
477 		wil_dbg_irq(wil, "TX done\n");  in wil6210_irq_tx()
556 	wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);  in wil6210_irq_misc()
581 		wil_dbg_irq(wil, "IRQ: FW ready\n");  in wil6210_irq_misc()
597 			wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n");  in wil6210_irq_misc()
619 	wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);  in wil6210_irq_misc_thread()
635 		wil_dbg_irq(wil, "MBOX event\n");  in wil6210_irq_misc_thread()
641 		wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr);  in wil6210_irq_misc_thread()
651 		wil_dbg_irq(wil, "set suspend_resp_comp to true\n");  in wil6210_irq_misc_thread()
666 	wil_dbg_irq(wil, "Thread IRQ\n");  in wil6210_thread_irq()
674 		wil_dbg_irq(wil, "set suspend_resp_comp to true\n");  in wil6210_thread_irq()
777 	wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);  in wil6210_hardirq()
872 	wil_dbg_irq(wil, "set_halp\n");  in wil6210_set_halp()
880 	wil_dbg_irq(wil, "clear_halp\n");  in wil6210_clear_halp()