Lines Matching refs:REG_WRITE
69 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
214 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
217 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar5008_hw_set_channel()
246 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
290 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar5008_hw_cmn_spur_mitigate()
291 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar5008_hw_cmn_spur_mitigate()
323 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
324 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
334 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
335 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
345 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
346 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
356 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
357 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
367 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
368 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
378 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
379 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
390 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
401 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar5008_hw_cmn_spur_mitigate()
448 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
455 REG_WRITE(ah, AR_PHY_SPUR_REG, new); in ar5008_hw_spur_mitigate()
466 REG_WRITE(ah, AR_PHY_TIMING11, new); in ar5008_hw_spur_mitigate()
565 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5008_hw_init_bb()
585 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
586 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5008_hw_init_chain_masks()
594 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
595 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_hw_init_chain_masks()
602 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); in ar5008_hw_init_chain_masks()
611 REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
646 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5008_hw_override_ini()
655 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5008_hw_override_ini()
664 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); in ar5008_hw_override_ini()
689 REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5008_hw_set_channel_regs()
695 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
696 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5008_hw_set_channel_regs()
721 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5008_hw_process_ini()
724 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); in ar5008_hw_process_ini()
729 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); in ar5008_hw_process_ini()
740 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
772 REG_WRITE(ah, reg, val); in ar5008_hw_process_ini()
825 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5008_hw_set_rfmode()
830 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5008_hw_mark_phy_inactive()
869 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar5008_hw_rfbus_req()
880 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar5008_hw_rfbus_done()
888 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
889 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5008_restore_chainmask()
1236 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar5008_hw_set_radar_params()
1237 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar5008_hw_set_radar_params()