Lines Matching refs:lmc_t1_write
899 lmc_t1_write (lmc_softc_t * const sc, int a, int d) in lmc_t1_write() function
934 lmc_t1_write (sc, 0x01, 0x1B); /* CR0 - primary control */ in lmc_t1_init()
935 lmc_t1_write (sc, 0x02, 0x42); /* JAT_CR - jitter atten config */ in lmc_t1_init()
936 lmc_t1_write (sc, 0x14, 0x00); /* LOOP - loopback config */ in lmc_t1_init()
937 lmc_t1_write (sc, 0x15, 0x00); /* DL3_TS - external data link timeslot */ in lmc_t1_init()
938 lmc_t1_write (sc, 0x18, 0xFF); /* PIO - programmable I/O */ in lmc_t1_init()
939 lmc_t1_write (sc, 0x19, 0x30); /* POE - programmable OE */ in lmc_t1_init()
940 lmc_t1_write (sc, 0x1A, 0x0F); /* CMUX - clock input mux */ in lmc_t1_init()
941 lmc_t1_write (sc, 0x20, 0x41); /* LIU_CR - RX LIU config */ in lmc_t1_init()
942 lmc_t1_write (sc, 0x22, 0x76); /* RLIU_CR - RX LIU config */ in lmc_t1_init()
943 lmc_t1_write (sc, 0x40, 0x03); /* RCR0 - RX config */ in lmc_t1_init()
944 lmc_t1_write (sc, 0x45, 0x00); /* RALM - RX alarm config */ in lmc_t1_init()
945 lmc_t1_write (sc, 0x46, 0x05); /* LATCH - RX alarm/err/cntr latch */ in lmc_t1_init()
946 lmc_t1_write (sc, 0x68, 0x40); /* TLIU_CR - TX LIU config */ in lmc_t1_init()
947 lmc_t1_write (sc, 0x70, 0x0D); /* TCR0 - TX framer config */ in lmc_t1_init()
948 lmc_t1_write (sc, 0x71, 0x05); /* TCR1 - TX config */ in lmc_t1_init()
949 lmc_t1_write (sc, 0x72, 0x0B); /* TFRM - TX frame format */ in lmc_t1_init()
950 lmc_t1_write (sc, 0x73, 0x00); /* TERROR - TX error insert */ in lmc_t1_init()
951 lmc_t1_write (sc, 0x74, 0x00); /* TMAN - TX manual Sa/FEBE config */ in lmc_t1_init()
952 lmc_t1_write (sc, 0x75, 0x00); /* TALM - TX alarm signal config */ in lmc_t1_init()
953 lmc_t1_write (sc, 0x76, 0x00); /* TPATT - TX test pattern config */ in lmc_t1_init()
954 lmc_t1_write (sc, 0x77, 0x00); /* TLB - TX inband loopback config */ in lmc_t1_init()
955 lmc_t1_write (sc, 0x90, 0x05); /* CLAD_CR - clock rate adapter config */ in lmc_t1_init()
956 lmc_t1_write (sc, 0x91, 0x05); /* CSEL - clad freq sel */ in lmc_t1_init()
957 lmc_t1_write (sc, 0xA6, 0x00); /* DL1_CTL - DL1 control */ in lmc_t1_init()
958 lmc_t1_write (sc, 0xB1, 0x00); /* DL2_CTL - DL2 control */ in lmc_t1_init()
959 lmc_t1_write (sc, 0xD0, 0x47); /* SBI_CR - sys bus iface config */ in lmc_t1_init()
960 lmc_t1_write (sc, 0xD1, 0x70); /* RSB_CR - RX sys bus config */ in lmc_t1_init()
961 lmc_t1_write (sc, 0xD4, 0x30); /* TSB_CR - TX sys bus config */ in lmc_t1_init()
964 lmc_t1_write (sc, 0x0E0 + i, 0x00); /* SBCn - sys bus per-channel ctl */ in lmc_t1_init()
965 lmc_t1_write (sc, 0x100 + i, 0x00); /* TPCn - TX per-channel ctl */ in lmc_t1_init()
966 lmc_t1_write (sc, 0x180 + i, 0x00); /* RPCn - RX per-channel ctl */ in lmc_t1_init()
970 lmc_t1_write (sc, 0x0E0 + i, 0x0D); /* SBCn - sys bus per-channel ctl */ in lmc_t1_init()