Lines Matching refs:phydev
15 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
20 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
23 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
27 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
38 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
70 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
74 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
78 return genphy_c45_an_disable_aneg(phydev); in genphy_c45_pma_setup_forced()
91 int genphy_c45_an_config_aneg(struct phy_device *phydev) in genphy_c45_an_config_aneg() argument
96 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
97 phydev->supported); in genphy_c45_an_config_aneg()
99 changed = genphy_config_eee_advert(phydev); in genphy_c45_an_config_aneg()
101 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
103 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
112 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
114 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
136 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
139 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in genphy_c45_an_disable_aneg()
152 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
154 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, in genphy_c45_restart_aneg()
168 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) in genphy_c45_check_and_restart_aneg() argument
174 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_check_and_restart_aneg()
183 ret = genphy_c45_restart_aneg(phydev); in genphy_c45_check_and_restart_aneg()
200 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
202 int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_aneg_done()
216 int genphy_c45_read_link(struct phy_device *phydev) in genphy_c45_read_link() argument
222 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { in genphy_c45_read_link()
223 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
231 phydev->link = 0; in genphy_c45_read_link()
244 if (!phy_polling_mode(phydev)) { in genphy_c45_read_link()
245 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
252 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
260 phydev->link = link; in genphy_c45_read_link()
276 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
280 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
286 phydev->lp_advertising); in genphy_c45_read_lpa()
287 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
288 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
289 phydev->pause = 0; in genphy_c45_read_lpa()
290 phydev->asym_pause = 0; in genphy_c45_read_lpa()
295 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
299 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
303 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
304 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
305 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
308 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
312 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
322 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
326 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
328 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
334 phydev->speed = SPEED_10; in genphy_c45_read_pma()
337 phydev->speed = SPEED_100; in genphy_c45_read_pma()
340 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
343 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
346 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
349 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
352 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
356 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
366 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
370 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
371 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
378 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
382 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
386 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
406 int genphy_c45_pma_read_abilities(struct phy_device *phydev) in genphy_c45_pma_read_abilities() argument
410 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
411 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
412 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_pma_read_abilities()
418 phydev->supported); in genphy_c45_pma_read_abilities()
421 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in genphy_c45_pma_read_abilities()
426 phydev->supported, in genphy_c45_pma_read_abilities()
430 phydev->supported, in genphy_c45_pma_read_abilities()
434 phydev->supported, in genphy_c45_pma_read_abilities()
438 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_pma_read_abilities()
443 phydev->supported, in genphy_c45_pma_read_abilities()
446 phydev->supported, in genphy_c45_pma_read_abilities()
449 phydev->supported, in genphy_c45_pma_read_abilities()
452 phydev->supported, in genphy_c45_pma_read_abilities()
455 phydev->supported, in genphy_c45_pma_read_abilities()
458 phydev->supported, in genphy_c45_pma_read_abilities()
462 phydev->supported, in genphy_c45_pma_read_abilities()
465 phydev->supported, in genphy_c45_pma_read_abilities()
469 phydev->supported, in genphy_c45_pma_read_abilities()
472 phydev->supported, in genphy_c45_pma_read_abilities()
476 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_pma_read_abilities()
482 phydev->supported, in genphy_c45_pma_read_abilities()
486 phydev->supported, in genphy_c45_pma_read_abilities()
501 int genphy_c45_read_status(struct phy_device *phydev) in genphy_c45_read_status() argument
505 ret = genphy_c45_read_link(phydev); in genphy_c45_read_status()
509 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
510 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
511 phydev->pause = 0; in genphy_c45_read_status()
512 phydev->asym_pause = 0; in genphy_c45_read_status()
514 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
515 ret = genphy_c45_read_lpa(phydev); in genphy_c45_read_status()
519 phy_resolve_aneg_linkmode(phydev); in genphy_c45_read_status()
521 ret = genphy_c45_read_pma(phydev); in genphy_c45_read_status()
536 int genphy_c45_config_aneg(struct phy_device *phydev) in genphy_c45_config_aneg() argument
541 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
542 return genphy_c45_pma_setup_forced(phydev); in genphy_c45_config_aneg()
544 ret = genphy_c45_an_config_aneg(phydev); in genphy_c45_config_aneg()
550 return genphy_c45_check_and_restart_aneg(phydev, changed); in genphy_c45_config_aneg()
556 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument