Lines Matching refs:phydev
435 static int vsc85xx_phy_read_page(struct phy_device *phydev) in vsc85xx_phy_read_page() argument
437 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); in vsc85xx_phy_read_page()
440 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) in vsc85xx_phy_write_page() argument
442 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); in vsc85xx_phy_write_page()
445 static int vsc85xx_get_sset_count(struct phy_device *phydev) in vsc85xx_get_sset_count() argument
447 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_sset_count()
455 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) in vsc85xx_get_strings() argument
457 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_strings()
468 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) in vsc85xx_get_stat() argument
470 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stat()
473 val = phy_read_paged(phydev, priv->hw_stats[i].page, in vsc85xx_get_stat()
484 static void vsc85xx_get_stats(struct phy_device *phydev, in vsc85xx_get_stats() argument
487 struct vsc8531_private *priv = phydev->priv; in vsc85xx_get_stats()
494 data[i] = vsc85xx_get_stat(phydev, i); in vsc85xx_get_stats()
497 static int vsc85xx_led_cntl_set(struct phy_device *phydev, in vsc85xx_led_cntl_set() argument
504 mutex_lock(&phydev->lock); in vsc85xx_led_cntl_set()
505 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); in vsc85xx_led_cntl_set()
508 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); in vsc85xx_led_cntl_set()
509 mutex_unlock(&phydev->lock); in vsc85xx_led_cntl_set()
514 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) in vsc85xx_mdix_get() argument
518 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); in vsc85xx_mdix_get()
527 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) in vsc85xx_mdix_set() argument
532 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc85xx_mdix_set()
542 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); in vsc85xx_mdix_set()
553 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_mdix_set()
559 return genphy_restart_aneg(phydev); in vsc85xx_mdix_set()
562 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) in vsc85xx_downshift_get() argument
566 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_get()
580 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) in vsc85xx_downshift_set() argument
586 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
593 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, in vsc85xx_downshift_set()
598 static int vsc85xx_wol_set(struct phy_device *phydev, in vsc85xx_wol_set() argument
606 u8 *mac_addr = phydev->attached_dev->dev_addr; in vsc85xx_wol_set()
608 mutex_lock(&phydev->lock); in vsc85xx_wol_set()
609 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_set()
611 rc = phy_restore_page(phydev, rc, rc); in vsc85xx_wol_set()
620 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
621 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); in vsc85xx_wol_set()
622 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); in vsc85xx_wol_set()
624 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
625 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
626 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
633 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
634 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); in vsc85xx_wol_set()
635 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); in vsc85xx_wol_set()
637 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
638 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
639 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
642 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_set()
647 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); in vsc85xx_wol_set()
649 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
655 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
657 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
662 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); in vsc85xx_wol_set()
664 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); in vsc85xx_wol_set()
669 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_wol_set()
672 mutex_unlock(&phydev->lock); in vsc85xx_wol_set()
677 static void vsc85xx_wol_get(struct phy_device *phydev, in vsc85xx_wol_get() argument
686 mutex_lock(&phydev->lock); in vsc85xx_wol_get()
687 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); in vsc85xx_wol_get()
691 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); in vsc85xx_wol_get()
695 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
696 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); in vsc85xx_wol_get()
697 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); in vsc85xx_wol_get()
706 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
707 mutex_unlock(&phydev->lock); in vsc85xx_wol_get()
711 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
715 struct device *dev = &phydev->mdio.dev; in vsc85xx_edge_rate_magic_get()
737 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
741 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_mode_get()
742 struct device *dev = &phydev->mdio.dev; in vsc85xx_dt_led_mode_get()
753 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()
761 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) in vsc85xx_edge_rate_magic_get() argument
766 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, in vsc85xx_dt_led_mode_get() argument
774 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, in vsc85xx_dt_led_modes_get() argument
777 struct vsc8531_private *priv = phydev->priv; in vsc85xx_dt_led_modes_get()
786 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, in vsc85xx_dt_led_modes_get()
796 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) in vsc85xx_edge_rate_cntl_set() argument
800 mutex_lock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
801 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_edge_rate_cntl_set()
804 mutex_unlock(&phydev->lock); in vsc85xx_edge_rate_cntl_set()
809 static int vsc85xx_mac_if_set(struct phy_device *phydev, in vsc85xx_mac_if_set() argument
815 mutex_lock(&phydev->lock); in vsc85xx_mac_if_set()
816 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc85xx_mac_if_set()
833 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); in vsc85xx_mac_if_set()
837 rc = genphy_soft_reset(phydev); in vsc85xx_mac_if_set()
840 mutex_unlock(&phydev->lock); in vsc85xx_mac_if_set()
845 static int vsc85xx_default_config(struct phy_device *phydev) in vsc85xx_default_config() argument
850 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc85xx_default_config()
851 mutex_lock(&phydev->lock); in vsc85xx_default_config()
855 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, in vsc85xx_default_config()
859 mutex_unlock(&phydev->lock); in vsc85xx_default_config()
864 static int vsc85xx_get_tunable(struct phy_device *phydev, in vsc85xx_get_tunable() argument
869 return vsc85xx_downshift_get(phydev, (u8 *)data); in vsc85xx_get_tunable()
875 static int vsc85xx_set_tunable(struct phy_device *phydev, in vsc85xx_set_tunable() argument
881 return vsc85xx_downshift_set(phydev, *(u8 *)data); in vsc85xx_set_tunable()
888 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc85xx_tr_write() argument
890 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc85xx_tr_write()
891 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
892 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc85xx_tr_write()
895 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) in vsc8531_pre_init_seq_set() argument
907 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, in vsc8531_pre_init_seq_set()
912 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
916 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
920 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, in vsc8531_pre_init_seq_set()
925 mutex_lock(&phydev->lock); in vsc8531_pre_init_seq_set()
926 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc8531_pre_init_seq_set()
931 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); in vsc8531_pre_init_seq_set()
934 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc8531_pre_init_seq_set()
935 mutex_unlock(&phydev->lock); in vsc8531_pre_init_seq_set()
940 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) in vsc85xx_eee_init_seq_set() argument
965 mutex_lock(&phydev->lock); in vsc85xx_eee_init_seq_set()
966 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); in vsc85xx_eee_init_seq_set()
971 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); in vsc85xx_eee_init_seq_set()
974 oldpage = phy_restore_page(phydev, oldpage, oldpage); in vsc85xx_eee_init_seq_set()
975 mutex_unlock(&phydev->lock); in vsc85xx_eee_init_seq_set()
981 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_base_write() argument
983 struct vsc8531_private *priv = phydev->priv; in phy_base_write()
985 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_write()
986 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_write()
990 return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val); in phy_base_write()
994 static int phy_base_read(struct phy_device *phydev, u32 regnum) in phy_base_read() argument
996 struct vsc8531_private *priv = phydev->priv; in phy_base_read()
998 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { in phy_base_read()
999 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); in phy_base_read()
1003 return __mdiobus_read(phydev->mdio.bus, priv->base_addr, regnum); in phy_base_read()
1007 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) in vsc8584_csr_write() argument
1009 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); in vsc8584_csr_write()
1010 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
1011 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); in vsc8584_csr_write()
1015 static int vsc8584_cmd(struct phy_device *phydev, u16 val) in vsc8584_cmd() argument
1020 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
1023 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); in vsc8584_cmd()
1027 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); in vsc8584_cmd()
1032 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_cmd()
1044 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, in vsc8584_micro_deassert_reset() argument
1049 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
1061 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_micro_deassert_reset()
1067 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
1069 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
1071 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_deassert_reset()
1077 static int vsc8584_micro_assert_reset(struct phy_device *phydev) in vsc8584_micro_assert_reset() argument
1082 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
1086 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
1089 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
1091 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
1093 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
1094 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
1096 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
1098 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
1100 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
1102 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
1104 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
1106 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | in vsc8584_micro_assert_reset()
1110 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
1112 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
1114 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_micro_assert_reset()
1120 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, in vsc8584_get_fw_crc() argument
1125 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
1127 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
1128 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); in vsc8584_get_fw_crc()
1131 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
1135 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8584_get_fw_crc()
1137 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
1140 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_get_fw_crc()
1146 static int vsc8584_patch_fw(struct phy_device *phydev, in vsc8584_patch_fw() argument
1151 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_patch_fw()
1153 dev_err(&phydev->mdio.dev, in vsc8584_patch_fw()
1158 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
1164 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | in vsc8584_patch_fw()
1167 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | in vsc8584_patch_fw()
1169 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
1172 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
1176 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
1178 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_patch_fw()
1184 static bool vsc8574_is_serdes_init(struct phy_device *phydev) in vsc8574_is_serdes_init() argument
1189 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
1192 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
1198 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
1204 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
1210 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
1219 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_is_serdes_init()
1225 static int vsc8574_config_pre_init(struct phy_device *phydev) in vsc8574_config_pre_init() argument
1291 struct device *dev = &phydev->mdio.dev; in vsc8574_config_pre_init()
1298 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1301 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1303 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1305 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1312 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1314 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1316 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1317 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1318 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1319 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1321 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1323 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1325 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1328 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8574_config_pre_init()
1330 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8574_config_pre_init()
1332 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1334 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8574_config_pre_init()
1337 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8574_config_pre_init()
1339 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8574_config_pre_init()
1341 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
1343 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
1345 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1348 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
1350 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
1360 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1367 serdes_init = vsc8574_is_serdes_init(phydev); in vsc8574_config_pre_init()
1370 ret = vsc8584_micro_assert_reset(phydev); in vsc8574_config_pre_init()
1383 if (vsc8584_patch_fw(phydev, fw)) in vsc8574_config_pre_init()
1389 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1392 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1393 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1394 phy_base_write(phydev, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
1397 vsc8584_micro_deassert_reset(phydev, false); in vsc8574_config_pre_init()
1402 ret = vsc8584_get_fw_crc(phydev, in vsc8574_config_pre_init()
1413 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
1416 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
1420 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8574_config_pre_init()
1428 static int vsc8584_config_pre_init(struct phy_device *phydev) in vsc8584_config_pre_init() argument
1460 struct device *dev = &phydev->mdio.dev; in vsc8584_config_pre_init()
1465 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1468 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1470 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1472 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1474 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
1476 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
1483 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); in vsc8584_config_pre_init()
1485 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1487 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1489 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1491 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1493 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1495 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1497 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1499 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); in vsc8584_config_pre_init()
1502 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); in vsc8584_config_pre_init()
1504 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1507 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8584_config_pre_init()
1509 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); in vsc8584_config_pre_init()
1511 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1513 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8584_config_pre_init()
1516 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); in vsc8584_config_pre_init()
1518 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8584_config_pre_init()
1520 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
1522 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
1524 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1527 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
1529 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
1539 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1547 if (vsc8584_patch_fw(phydev, fw)) in vsc8584_config_pre_init()
1552 vsc8584_micro_deassert_reset(phydev, false); in vsc8584_config_pre_init()
1555 ret = vsc8584_get_fw_crc(phydev, in vsc8584_config_pre_init()
1565 ret = vsc8584_micro_assert_reset(phydev); in vsc8584_config_pre_init()
1569 vsc8584_micro_deassert_reset(phydev, true); in vsc8584_config_pre_init()
1572 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_pre_init()
1582 static bool vsc8584_is_pkg_init(struct phy_device *phydev, bool reversed) in vsc8584_is_pkg_init() argument
1584 struct mdio_device **map = phydev->mdio.bus->mdio_map; in vsc8584_is_pkg_init()
1591 vsc8531 = phydev->priv; in vsc8584_is_pkg_init()
1600 if ((phy->phy_id & phydev->drv->phy_id_mask) != in vsc8584_is_pkg_init()
1601 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) in vsc8584_is_pkg_init()
1613 static int vsc8584_config_init(struct phy_device *phydev) in vsc8584_config_init() argument
1615 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8584_config_init()
1619 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8584_config_init()
1621 mutex_lock(&phydev->mdio.bus->mdio_lock); in vsc8584_config_init()
1623 __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, in vsc8584_config_init()
1625 addr = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, in vsc8584_config_init()
1629 val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, in vsc8584_config_init()
1632 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8584_config_init()
1634 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8584_config_init()
1649 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) { in vsc8584_config_init()
1650 if ((phydev->phy_id & phydev->drv->phy_id_mask) == in vsc8584_config_init()
1651 (PHY_ID_VSC8574 & phydev->drv->phy_id_mask)) in vsc8584_config_init()
1652 ret = vsc8574_config_pre_init(phydev); in vsc8584_config_init()
1653 else if ((phydev->phy_id & phydev->drv->phy_id_mask) == in vsc8584_config_init()
1654 (PHY_ID_VSC8584 & phydev->drv->phy_id_mask)) in vsc8584_config_init()
1655 ret = vsc8584_config_pre_init(phydev); in vsc8584_config_init()
1665 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_init()
1668 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8584_config_init()
1670 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_init()
1675 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8584_config_init()
1681 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) in vsc8584_config_init()
1686 ret = vsc8584_cmd(phydev, val); in vsc8584_config_init()
1693 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1701 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1708 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8584_config_init()
1710 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8584_config_init()
1712 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); in vsc8584_config_init()
1716 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); in vsc8584_config_init()
1718 ret = genphy_soft_reset(phydev); in vsc8584_config_init()
1723 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8584_config_init()
1731 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8584_config_init()
1735 static int vsc85xx_config_init(struct phy_device *phydev) in vsc85xx_config_init() argument
1738 struct vsc8531_private *vsc8531 = phydev->priv; in vsc85xx_config_init()
1740 rc = vsc85xx_default_config(phydev); in vsc85xx_config_init()
1744 rc = vsc85xx_mac_if_set(phydev, phydev->interface); in vsc85xx_config_init()
1748 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); in vsc85xx_config_init()
1752 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; in vsc85xx_config_init()
1755 rc = vsc8531_pre_init_seq_set(phydev); in vsc85xx_config_init()
1760 rc = vsc85xx_eee_init_seq_set(phydev); in vsc85xx_config_init()
1765 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc85xx_config_init()
1773 static int vsc8584_did_interrupt(struct phy_device *phydev) in vsc8584_did_interrupt() argument
1777 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc8584_did_interrupt()
1778 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc8584_did_interrupt()
1783 static int vsc8514_config_pre_init(struct phy_device *phydev) in vsc8514_config_pre_init() argument
1814 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1817 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1819 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1821 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1823 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1825 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1827 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); in vsc8514_config_pre_init()
1830 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); in vsc8514_config_pre_init()
1832 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); in vsc8514_config_pre_init()
1834 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); in vsc8514_config_pre_init()
1836 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); in vsc8514_config_pre_init()
1838 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_pre_init()
1840 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); in vsc8514_config_pre_init()
1842 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8514_config_pre_init()
1847 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, in vsc85xx_csr_ctrl_phy_read() argument
1853 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_ctrl_phy_read()
1863 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_ctrl_phy_read()
1867 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_ctrl_phy_read()
1876 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_ctrl_phy_read()
1884 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); in vsc85xx_csr_ctrl_phy_read()
1887 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); in vsc85xx_csr_ctrl_phy_read()
1889 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_ctrl_phy_read()
1895 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev, in vsc85xx_csr_ctrl_phy_write() argument
1900 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); in vsc85xx_csr_ctrl_phy_write()
1910 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, in vsc85xx_csr_ctrl_phy_write()
1914 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); in vsc85xx_csr_ctrl_phy_write()
1917 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); in vsc85xx_csr_ctrl_phy_write()
1920 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, in vsc85xx_csr_ctrl_phy_write()
1929 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); in vsc85xx_csr_ctrl_phy_write()
1936 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc85xx_csr_ctrl_phy_write()
1942 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, in __phy_write_mcb_s6g() argument
1949 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg, in __phy_write_mcb_s6g()
1957 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); in __phy_write_mcb_s6g()
1971 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_update_mcb_s6g() argument
1973 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); in phy_update_mcb_s6g()
1977 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) in phy_commit_mcb_s6g() argument
1979 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); in phy_commit_mcb_s6g()
1982 static int vsc8514_config_init(struct phy_device *phydev) in vsc8514_config_init() argument
1984 struct vsc8531_private *vsc8531 = phydev->priv; in vsc8514_config_init()
1990 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in vsc8514_config_init()
1992 mutex_lock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
1994 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); in vsc8514_config_init()
1996 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); in vsc8514_config_init()
1999 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); in vsc8514_config_init()
2002 vsc8531->base_addr = phydev->mdio.addr + addr; in vsc8514_config_init()
2004 vsc8531->base_addr = phydev->mdio.addr - addr; in vsc8514_config_init()
2017 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) in vsc8514_config_init()
2018 vsc8514_config_pre_init(phydev); in vsc8514_config_init()
2022 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, in vsc8514_config_init()
2025 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); in vsc8514_config_init()
2029 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); in vsc8514_config_init()
2034 ret = vsc8584_cmd(phydev, in vsc8514_config_init()
2042 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
2044 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
2046 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2051 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
2053 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2062 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2073 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2079 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2084 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); in vsc8514_config_init()
2089 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
2091 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2094 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
2101 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
2106 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2111 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
2116 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, in vsc8514_config_init()
2118 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, in vsc8514_config_init()
2121 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
2128 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
2132 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
2134 ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); in vsc8514_config_init()
2139 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, in vsc8514_config_init()
2145 ret = genphy_soft_reset(phydev); in vsc8514_config_init()
2151 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); in vsc8514_config_init()
2159 mutex_unlock(&phydev->mdio.bus->mdio_lock); in vsc8514_config_init()
2163 static int vsc85xx_ack_interrupt(struct phy_device *phydev) in vsc85xx_ack_interrupt() argument
2167 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in vsc85xx_ack_interrupt()
2168 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_ack_interrupt()
2173 static int vsc85xx_config_intr(struct phy_device *phydev) in vsc85xx_config_intr() argument
2177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in vsc85xx_config_intr()
2178 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, in vsc85xx_config_intr()
2181 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2184 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); in vsc85xx_config_intr()
2190 static int vsc85xx_config_aneg(struct phy_device *phydev) in vsc85xx_config_aneg() argument
2194 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); in vsc85xx_config_aneg()
2198 return genphy_config_aneg(phydev); in vsc85xx_config_aneg()
2201 static int vsc85xx_read_status(struct phy_device *phydev) in vsc85xx_read_status() argument
2205 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); in vsc85xx_read_status()
2209 return genphy_read_status(phydev); in vsc85xx_read_status()
2212 static int vsc8514_probe(struct phy_device *phydev) in vsc8514_probe() argument
2219 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8514_probe()
2223 phydev->priv = vsc8531; in vsc8514_probe()
2229 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8514_probe()
2234 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8514_probe()
2237 static int vsc8574_probe(struct phy_device *phydev) in vsc8574_probe() argument
2244 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8574_probe()
2248 phydev->priv = vsc8531; in vsc8574_probe()
2254 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8574_probe()
2259 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8574_probe()
2262 static int vsc8584_probe(struct phy_device *phydev) in vsc8584_probe() argument
2269 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { in vsc8584_probe()
2270 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); in vsc8584_probe()
2274 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc8584_probe()
2278 phydev->priv = vsc8531; in vsc8584_probe()
2284 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc8584_probe()
2289 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc8584_probe()
2292 static int vsc85xx_probe(struct phy_device *phydev) in vsc85xx_probe() argument
2299 rate_magic = vsc85xx_edge_rate_magic_get(phydev); in vsc85xx_probe()
2303 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); in vsc85xx_probe()
2307 phydev->priv = vsc8531; in vsc85xx_probe()
2314 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, in vsc85xx_probe()
2319 return vsc85xx_dt_led_modes_get(phydev, default_mode); in vsc85xx_probe()