981 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)  in phy_base_write()  function
1009 	phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);  in vsc8584_csr_write()
1010 	phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));  in vsc8584_csr_write()
1011 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));  in vsc8584_csr_write()
1020 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_cmd()
1023 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);  in vsc8584_cmd()
1032 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_cmd()
1049 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_deassert_reset()
1061 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_micro_deassert_reset()
1067 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);  in vsc8584_micro_deassert_reset()
1069 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);  in vsc8584_micro_deassert_reset()
1071 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_deassert_reset()
1086 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_micro_assert_reset()
1091 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
1093 	phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
1094 	phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);  in vsc8584_micro_assert_reset()
1098 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
1100 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);  in vsc8584_micro_assert_reset()
1104 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);  in vsc8584_micro_assert_reset()
1106 	phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |  in vsc8584_micro_assert_reset()
1112 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);  in vsc8584_micro_assert_reset()
1114 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_micro_assert_reset()
1125 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
1127 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);  in vsc8584_get_fw_crc()
1128 	phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);  in vsc8584_get_fw_crc()
1135 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);  in vsc8584_get_fw_crc()
1140 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_get_fw_crc()
1158 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_patch_fw()
1164 	phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |  in vsc8584_patch_fw()
1167 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |  in vsc8584_patch_fw()
1169 	phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);  in vsc8584_patch_fw()
1172 		phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |  in vsc8584_patch_fw()
1176 	phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);  in vsc8584_patch_fw()
1178 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_patch_fw()
1189 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_is_serdes_init()
1219 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_is_serdes_init()
1298 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1303 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1305 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8574_config_pre_init()
1312 	phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);  in vsc8574_config_pre_init()
1314 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1316 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);  in vsc8574_config_pre_init()
1317 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);  in vsc8574_config_pre_init()
1318 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);  in vsc8574_config_pre_init()
1319 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);  in vsc8574_config_pre_init()
1323 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1325 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1330 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8574_config_pre_init()
1332 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8574_config_pre_init()
1334 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8574_config_pre_init()
1339 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8574_config_pre_init()
1343 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8574_config_pre_init()
1345 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1350 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8574_config_pre_init()
1389 		phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1392 		phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);  in vsc8574_config_pre_init()
1393 		phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);  in vsc8574_config_pre_init()
1394 		phy_base_write(phydev, MSCC_INT_MEM_CNTL,  in vsc8574_config_pre_init()
1413 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8574_config_pre_init()
1420 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8574_config_pre_init()
1465 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1470 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1472 	phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);  in vsc8584_config_pre_init()
1476 	phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);  in vsc8584_config_pre_init()
1483 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);  in vsc8584_config_pre_init()
1485 	phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);  in vsc8584_config_pre_init()
1487 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1489 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);  in vsc8584_config_pre_init()
1493 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1495 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1497 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));  in vsc8584_config_pre_init()
1502 	phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);  in vsc8584_config_pre_init()
1504 	phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));  in vsc8584_config_pre_init()
1509 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);  in vsc8584_config_pre_init()
1511 	phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);  in vsc8584_config_pre_init()
1513 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8584_config_pre_init()
1518 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8584_config_pre_init()
1522 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8584_config_pre_init()
1524 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1529 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8584_config_pre_init()
1572 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8584_config_pre_init()
1665 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8584_config_init()
1675 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8584_config_init()
1814 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
1819 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
1821 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
1825 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
1827 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);  in vsc8514_config_pre_init()
1832 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);  in vsc8514_config_pre_init()
1836 	phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);  in vsc8514_config_pre_init()
1838 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);  in vsc8514_config_pre_init()
1842 	phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);  in vsc8514_config_pre_init()
1853 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_ctrl_phy_read()
1863 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_ctrl_phy_read()
1867 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_ctrl_phy_read()
1889 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_ctrl_phy_read()
1900 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);  in vsc85xx_csr_ctrl_phy_write()
1910 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,  in vsc85xx_csr_ctrl_phy_write()
1914 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);  in vsc85xx_csr_ctrl_phy_write()
1917 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));  in vsc85xx_csr_ctrl_phy_write()
1920 	phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,  in vsc85xx_csr_ctrl_phy_write()
1936 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc85xx_csr_ctrl_phy_write()
2022 	phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,  in vsc8514_config_init()
2029 	ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);  in vsc8514_config_init()