84 	struct phy_device *phydev = dev_get_drvdata(dev);  in mv3310_hwmon_read()  local
93 		temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);  in mv3310_hwmon_read()
141 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)  in mv3310_hwmon_config()  argument
146 	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,  in mv3310_hwmon_config()
153 	return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,  in mv3310_hwmon_config()
159 	struct phy_device *phydev = data;  in mv3310_hwmon_disable()  local
161 	mv3310_hwmon_config(phydev, false);  in mv3310_hwmon_disable()
164 static int mv3310_hwmon_probe(struct phy_device *phydev)  in mv3310_hwmon_probe()  argument
166 	struct device *dev = &phydev->mdio.dev;  in mv3310_hwmon_probe()
167 	struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);  in mv3310_hwmon_probe()
183 	ret = mv3310_hwmon_config(phydev, true);  in mv3310_hwmon_probe()
187 	ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);  in mv3310_hwmon_probe()
192 				priv->hwmon_name, phydev,  in mv3310_hwmon_probe()
198 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)  in mv3310_hwmon_config()  argument
203 static int mv3310_hwmon_probe(struct phy_device *phydev)  in mv3310_hwmon_probe()  argument
209 static int mv3310_probe(struct phy_device *phydev)  in mv3310_probe()  argument
215 	if (!phydev->is_c45 ||  in mv3310_probe()
216 	    (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)  in mv3310_probe()
219 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);  in mv3310_probe()
224 		dev_warn(&phydev->mdio.dev,  in mv3310_probe()
229 	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);  in mv3310_probe()
233 	dev_set_drvdata(&phydev->mdio.dev, priv);  in mv3310_probe()
235 	ret = mv3310_hwmon_probe(phydev);  in mv3310_probe()
242 static int mv3310_suspend(struct phy_device *phydev)  in mv3310_suspend()  argument
244 	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,  in mv3310_suspend()
248 static int mv3310_resume(struct phy_device *phydev)  in mv3310_resume()  argument
252 	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,  in mv3310_resume()
257 	return mv3310_hwmon_config(phydev, true);  in mv3310_resume()
267 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)  in mv3310_has_pma_ngbaset_quirk()  argument
269 	if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))  in mv3310_has_pma_ngbaset_quirk()
273 	return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &  in mv3310_has_pma_ngbaset_quirk()
277 static int mv3310_config_init(struct phy_device *phydev)  in mv3310_config_init()  argument
280 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&  in mv3310_config_init()
281 	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&  in mv3310_config_init()
282 	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&  in mv3310_config_init()
283 	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&  in mv3310_config_init()
284 	    phydev->interface != PHY_INTERFACE_MODE_10GKR)  in mv3310_config_init()
290 static int mv3310_get_features(struct phy_device *phydev)  in mv3310_get_features()  argument
294 	ret = genphy_c45_pma_read_abilities(phydev);  in mv3310_get_features()
298 	if (mv3310_has_pma_ngbaset_quirk(phydev)) {  in mv3310_get_features()
299 		val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,  in mv3310_get_features()
305 				 phydev->supported,  in mv3310_get_features()
309 				 phydev->supported,  in mv3310_get_features()
316 static int mv3310_config_aneg(struct phy_device *phydev)  in mv3310_config_aneg()  argument
323 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;  in mv3310_config_aneg()
325 	if (phydev->autoneg == AUTONEG_DISABLE)  in mv3310_config_aneg()
326 		return genphy_c45_pma_setup_forced(phydev);  in mv3310_config_aneg()
328 	ret = genphy_c45_an_config_aneg(phydev);  in mv3310_config_aneg()
337 	reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);  in mv3310_config_aneg()
338 	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,  in mv3310_config_aneg()
345 	return genphy_c45_check_and_restart_aneg(phydev, changed);  in mv3310_config_aneg()
348 static int mv3310_aneg_done(struct phy_device *phydev)  in mv3310_aneg_done()  argument
352 	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);  in mv3310_aneg_done()
359 	return genphy_c45_aneg_done(phydev);  in mv3310_aneg_done()
362 static void mv3310_update_interface(struct phy_device *phydev)  in mv3310_update_interface()  argument
364 	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||  in mv3310_update_interface()
365 	     phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||  in mv3310_update_interface()
366 	     phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {  in mv3310_update_interface()
373 		switch (phydev->speed) {  in mv3310_update_interface()
375 			phydev->interface = PHY_INTERFACE_MODE_10GKR;  in mv3310_update_interface()
378 			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;  in mv3310_update_interface()
383 			phydev->interface = PHY_INTERFACE_MODE_SGMII;  in mv3310_update_interface()
392 static int mv3310_read_10gbr_status(struct phy_device *phydev)  in mv3310_read_10gbr_status()  argument
394 	phydev->link = 1;  in mv3310_read_10gbr_status()
395 	phydev->speed = SPEED_10000;  in mv3310_read_10gbr_status()
396 	phydev->duplex = DUPLEX_FULL;  in mv3310_read_10gbr_status()
398 	mv3310_update_interface(phydev);  in mv3310_read_10gbr_status()
403 static int mv3310_read_status(struct phy_device *phydev)  in mv3310_read_status()  argument
407 	phydev->speed = SPEED_UNKNOWN;  in mv3310_read_status()
408 	phydev->duplex = DUPLEX_UNKNOWN;  in mv3310_read_status()
409 	linkmode_zero(phydev->lp_advertising);  in mv3310_read_status()
410 	phydev->link = 0;  in mv3310_read_status()
411 	phydev->pause = 0;  in mv3310_read_status()
412 	phydev->asym_pause = 0;  in mv3310_read_status()
413 	phydev->mdix = 0;  in mv3310_read_status()
415 	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);  in mv3310_read_status()
420 		return mv3310_read_10gbr_status(phydev);  in mv3310_read_status()
422 	val = genphy_c45_read_link(phydev);  in mv3310_read_status()
426 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);  in mv3310_read_status()
431 		val = genphy_c45_read_lpa(phydev);  in mv3310_read_status()
436 		val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);  in mv3310_read_status()
440 		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);  in mv3310_read_status()
442 		if (phydev->autoneg == AUTONEG_ENABLE)  in mv3310_read_status()
443 			phy_resolve_aneg_linkmode(phydev);  in mv3310_read_status()
446 	if (phydev->autoneg != AUTONEG_ENABLE) {  in mv3310_read_status()
447 		val = genphy_c45_read_pma(phydev);  in mv3310_read_status()
452 	if (phydev->speed == SPEED_10000) {  in mv3310_read_status()
453 		val = genphy_c45_read_mdix(phydev);  in mv3310_read_status()
457 		val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);  in mv3310_read_status()
463 			phydev->mdix = ETH_TP_MDI_X;  in mv3310_read_status()
466 			phydev->mdix = ETH_TP_MDI;  in mv3310_read_status()
469 			phydev->mdix = ETH_TP_MDI_INVALID;  in mv3310_read_status()
474 	mv3310_update_interface(phydev);  in mv3310_read_status()