119 static int dp83867_ack_interrupt(struct phy_device *phydev)  in dp83867_ack_interrupt()  argument
121 	int err = phy_read(phydev, MII_DP83867_ISR);  in dp83867_ack_interrupt()
129 static int dp83867_config_intr(struct phy_device *phydev)  in dp83867_config_intr()  argument
133 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {  in dp83867_config_intr()
134 		micr_status = phy_read(phydev, MII_DP83867_MICR);  in dp83867_config_intr()
146 		return phy_write(phydev, MII_DP83867_MICR, micr_status);  in dp83867_config_intr()
150 	return phy_write(phydev, MII_DP83867_MICR, micr_status);  in dp83867_config_intr()
153 static int dp83867_config_port_mirroring(struct phy_device *phydev)  in dp83867_config_port_mirroring()  argument
156 		(struct dp83867_private *)phydev->priv;  in dp83867_config_port_mirroring()
159 		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
162 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_port_mirroring()
168 static int dp83867_of_init(struct phy_device *phydev)  in dp83867_of_init()  argument
170 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
171 	struct device *dev = &phydev->mdio.dev;  in dp83867_of_init()
189 			phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",  in dp83867_of_init()
211 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {  in dp83867_of_init()
212 		const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);  in dp83867_of_init()
220 			phydev_warn(phydev,  in dp83867_of_init()
226 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in dp83867_of_init()
227 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {  in dp83867_of_init()
231 			phydev_err(phydev, "ti,rx-internal-delay must be specified\n");  in dp83867_of_init()
235 			phydev_err(phydev,  in dp83867_of_init()
243 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in dp83867_of_init()
244 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {  in dp83867_of_init()
248 			phydev_err(phydev, "ti,tx-internal-delay must be specified\n");  in dp83867_of_init()
252 			phydev_err(phydev,  in dp83867_of_init()
268 		phydev_err(phydev,  in dp83867_of_init()
273 		phydev_err(phydev,  in dp83867_of_init()
281 static int dp83867_of_init(struct phy_device *phydev)  in dp83867_of_init()  argument
287 static int dp83867_probe(struct phy_device *phydev)  in dp83867_probe()  argument
291 	dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),  in dp83867_probe()
296 	phydev->priv = dp83867;  in dp83867_probe()
301 static int dp83867_config_init(struct phy_device *phydev)  in dp83867_config_init()  argument
303 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_config_init()
307 	ret = dp83867_of_init(phydev);  in dp83867_config_init()
313 		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,  in dp83867_config_init()
316 	if (phy_interface_is_rgmii(phydev)) {  in dp83867_config_init()
317 		val = phy_read(phydev, MII_DP83867_PHYCTRL);  in dp83867_config_init()
333 		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);  in dp83867_config_init()
337 		ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);  in dp83867_config_init()
348 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);  in dp83867_config_init()
351 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)  in dp83867_config_init()
354 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)  in dp83867_config_init()
357 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)  in dp83867_config_init()
360 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);  in dp83867_config_init()
365 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,  in dp83867_config_init()
371 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
375 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {  in dp83867_config_init()
382 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
393 		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,  in dp83867_config_init()
401 		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);  in dp83867_config_init()
410 		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);  in dp83867_config_init()
414 	if (phy_interrupt_is_valid(phydev)) {  in dp83867_config_init()
415 		val = phy_read(phydev, DP83867_CFG3);  in dp83867_config_init()
417 		phy_write(phydev, DP83867_CFG3, val);  in dp83867_config_init()
421 		dp83867_config_port_mirroring(phydev);  in dp83867_config_init()
435 		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,  in dp83867_config_init()
442 static int dp83867_phy_reset(struct phy_device *phydev)  in dp83867_phy_reset()  argument
446 	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);  in dp83867_phy_reset()