Lines Matching refs:DP83867_DEVADDR
19 #define DP83867_DEVADDR 0x1f macro
159 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
162 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring()
212 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2); in dp83867_of_init()
313 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
333 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1); in dp83867_config_init()
348 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL); in dp83867_config_init()
360 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val); in dp83867_config_init()
365 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL, in dp83867_config_init()
371 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, in dp83867_config_init()
382 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, in dp83867_config_init()
393 ret = phy_modify_mmd(phydev, DP83867_DEVADDR, in dp83867_config_init()
401 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); in dp83867_config_init()
410 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val); in dp83867_config_init()
435 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, in dp83867_config_init()