1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/net/ti-dp83867.h>
133 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {  in dp83867_config_intr()
156 		(struct dp83867_private *)phydev->priv;  in dp83867_config_port_mirroring()
158 	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)  in dp83867_config_port_mirroring()
170 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_of_init()
171 	struct device *dev = &phydev->mdio.dev;  in dp83867_of_init()
172 	struct device_node *of_node = dev->of_node;  in dp83867_of_init()
176 		return -ENODEV;  in dp83867_of_init()
179 	ret = of_property_read_u32(of_node, "ti,clk-output-sel",  in dp83867_of_init()
180 				   &dp83867->clk_output_sel);  in dp83867_of_init()
183 		dp83867->set_clk_output = true;  in dp83867_of_init()
187 		if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&  in dp83867_of_init()
188 		    dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {  in dp83867_of_init()
189 			phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",  in dp83867_of_init()
190 				   dp83867->clk_output_sel);  in dp83867_of_init()
191 			return -EINVAL;  in dp83867_of_init()
195 	if (of_property_read_bool(of_node, "ti,max-output-impedance"))  in dp83867_of_init()
196 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;  in dp83867_of_init()
197 	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))  in dp83867_of_init()
198 		dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;  in dp83867_of_init()
200 		dp83867->io_impedance = -1; /* leave at default */  in dp83867_of_init()
202 	dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,  in dp83867_of_init()
203 					"ti,dp83867-rxctrl-strap-quirk");  in dp83867_of_init()
205 	dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,  in dp83867_of_init()
206 					"ti,sgmii-ref-clock-output-enable");  in dp83867_of_init()
211 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {  in dp83867_of_init()
221 				    "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"  in dp83867_of_init()
222 				    "Should be 'rgmii-id' to use internal delays\n");  in dp83867_of_init()
225 	/* RX delay *must* be specified if internal delay of RX is used. */  in dp83867_of_init()
226 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in dp83867_of_init()
227 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {  in dp83867_of_init()
228 		ret = of_property_read_u32(of_node, "ti,rx-internal-delay",  in dp83867_of_init()
229 					   &dp83867->rx_id_delay);  in dp83867_of_init()
231 			phydev_err(phydev, "ti,rx-internal-delay must be specified\n");  in dp83867_of_init()
234 		if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {  in dp83867_of_init()
236 				   "ti,rx-internal-delay value of %u out of range\n",  in dp83867_of_init()
237 				   dp83867->rx_id_delay);  in dp83867_of_init()
238 			return -EINVAL;  in dp83867_of_init()
242 	/* TX delay *must* be specified if internal delay of RX is used. */  in dp83867_of_init()
243 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in dp83867_of_init()
244 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {  in dp83867_of_init()
245 		ret = of_property_read_u32(of_node, "ti,tx-internal-delay",  in dp83867_of_init()
246 					   &dp83867->tx_id_delay);  in dp83867_of_init()
248 			phydev_err(phydev, "ti,tx-internal-delay must be specified\n");  in dp83867_of_init()
251 		if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {  in dp83867_of_init()
253 				   "ti,tx-internal-delay value of %u out of range\n",  in dp83867_of_init()
254 				   dp83867->tx_id_delay);  in dp83867_of_init()
255 			return -EINVAL;  in dp83867_of_init()
259 	if (of_property_read_bool(of_node, "enet-phy-lane-swap"))  in dp83867_of_init()
260 		dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;  in dp83867_of_init()
262 	if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))  in dp83867_of_init()
263 		dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;  in dp83867_of_init()
265 	ret = of_property_read_u32(of_node, "ti,fifo-depth",  in dp83867_of_init()
266 				   &dp83867->fifo_depth);  in dp83867_of_init()
269 			   "ti,fifo-depth property is required\n");  in dp83867_of_init()
272 	if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {  in dp83867_of_init()
274 			   "ti,fifo-depth value %u out of range\n",  in dp83867_of_init()
275 			   dp83867->fifo_depth);  in dp83867_of_init()
276 		return -EINVAL;  in dp83867_of_init()
291 	dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),  in dp83867_probe()
294 		return -ENOMEM;  in dp83867_probe()
296 	phydev->priv = dp83867;  in dp83867_probe()
303 	struct dp83867_private *dp83867 = phydev->priv;  in dp83867_config_init()
312 	if (dp83867->rxctrl_strap_quirk)  in dp83867_config_init()
321 		val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);  in dp83867_config_init()
351 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)  in dp83867_config_init()
354 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)  in dp83867_config_init()
357 		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)  in dp83867_config_init()
362 		delay = (dp83867->rx_id_delay |  in dp83867_config_init()
363 			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));  in dp83867_config_init()
370 	if (dp83867->io_impedance >= 0)  in dp83867_config_init()
373 			       dp83867->io_impedance);  in dp83867_config_init()
375 	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {  in dp83867_config_init()
402 		/* SGMII type is set to 4-wire mode by default.  in dp83867_config_init()
404 		 * switch on 6-wire mode.  in dp83867_config_init()
406 		if (dp83867->sgmii_ref_clk_en)  in dp83867_config_init()
420 	if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)  in dp83867_config_init()
424 	if (dp83867->set_clk_output) {  in dp83867_config_init()
427 		if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {  in dp83867_config_init()
431 			val = dp83867->clk_output_sel <<  in dp83867_config_init()