Lines Matching refs:phydev
17 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) in bcm_phy_write_exp() argument
21 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_write_exp()
25 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in bcm_phy_write_exp()
29 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg) in bcm_phy_read_exp() argument
33 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_read_exp()
37 val = phy_read(phydev, MII_BCM54XX_EXP_DATA); in bcm_phy_read_exp()
40 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0); in bcm_phy_read_exp()
46 int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum) in bcm54xx_auxctl_read() argument
51 phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MASK | in bcm54xx_auxctl_read()
53 return phy_read(phydev, MII_BCM54XX_AUX_CTL); in bcm54xx_auxctl_read()
57 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) in bcm54xx_auxctl_write() argument
59 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
63 int bcm_phy_write_misc(struct phy_device *phydev, in bcm_phy_write_misc() argument
69 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
74 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL); in bcm_phy_write_misc()
76 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
81 rc = bcm_phy_write_exp(phydev, tmp, val); in bcm_phy_write_misc()
87 int bcm_phy_read_misc(struct phy_device *phydev, in bcm_phy_read_misc() argument
93 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
98 tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL); in bcm_phy_read_misc()
100 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
105 rc = bcm_phy_read_exp(phydev, tmp); in bcm_phy_read_misc()
111 int bcm_phy_ack_intr(struct phy_device *phydev) in bcm_phy_ack_intr() argument
116 reg = phy_read(phydev, MII_BCM54XX_ISR); in bcm_phy_ack_intr()
124 int bcm_phy_config_intr(struct phy_device *phydev) in bcm_phy_config_intr() argument
128 reg = phy_read(phydev, MII_BCM54XX_ECR); in bcm_phy_config_intr()
132 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in bcm_phy_config_intr()
137 return phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
141 int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow) in bcm_phy_read_shadow() argument
143 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); in bcm_phy_read_shadow()
144 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD)); in bcm_phy_read_shadow()
148 int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow, in bcm_phy_write_shadow() argument
151 return phy_write(phydev, MII_BCM54XX_SHD, in bcm_phy_write_shadow()
158 int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down) in bcm_phy_enable_apd() argument
163 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3); in bcm_phy_enable_apd()
168 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val); in bcm_phy_enable_apd()
171 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD); in bcm_phy_enable_apd()
178 if (phydev->autoneg == AUTONEG_ENABLE) in bcm_phy_enable_apd()
187 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); in bcm_phy_enable_apd()
191 int bcm_phy_set_eee(struct phy_device *phydev, bool enable) in bcm_phy_set_eee() argument
196 val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL); in bcm_phy_set_eee()
205 phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val); in bcm_phy_set_eee()
208 val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV); in bcm_phy_set_eee()
217 phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val); in bcm_phy_set_eee()
223 int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count) in bcm_phy_downshift_get() argument
227 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); in bcm_phy_downshift_get()
237 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2); in bcm_phy_downshift_get()
255 int bcm_phy_downshift_set(struct phy_device *phydev, u8 count) in bcm_phy_downshift_set() argument
266 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC); in bcm_phy_downshift_set()
275 return bcm54xx_auxctl_write(phydev, in bcm_phy_downshift_set()
280 ret = bcm54xx_auxctl_write(phydev, in bcm_phy_downshift_set()
287 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2); in bcm_phy_downshift_set()
305 return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val); in bcm_phy_downshift_set()
325 int bcm_phy_get_sset_count(struct phy_device *phydev) in bcm_phy_get_sset_count() argument
331 void bcm_phy_get_strings(struct phy_device *phydev, u8 *data) in bcm_phy_get_strings() argument
344 static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow, in bcm_phy_get_stat() argument
351 val = phy_read(phydev, stat.reg); in bcm_phy_get_stat()
364 void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow, in bcm_phy_get_stats() argument
370 data[i] = bcm_phy_get_stat(phydev, shadow, i); in bcm_phy_get_stats()
374 void bcm_phy_r_rc_cal_reset(struct phy_device *phydev) in bcm_phy_r_rc_cal_reset() argument
377 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010); in bcm_phy_r_rc_cal_reset()
380 bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000); in bcm_phy_r_rc_cal_reset()
384 int bcm_phy_28nm_a0b0_afe_config_init(struct phy_device *phydev) in bcm_phy_28nm_a0b0_afe_config_init() argument
389 bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048); in bcm_phy_28nm_a0b0_afe_config_init()
392 bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b); in bcm_phy_28nm_a0b0_afe_config_init()
397 bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20); in bcm_phy_28nm_a0b0_afe_config_init()
400 bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b); in bcm_phy_28nm_a0b0_afe_config_init()
403 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); in bcm_phy_28nm_a0b0_afe_config_init()
405 bcm_phy_r_rc_cal_reset(phydev); in bcm_phy_28nm_a0b0_afe_config_init()
408 bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19); in bcm_phy_28nm_a0b0_afe_config_init()
411 bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f); in bcm_phy_28nm_a0b0_afe_config_init()
414 bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0); in bcm_phy_28nm_a0b0_afe_config_init()
417 bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b); in bcm_phy_28nm_a0b0_afe_config_init()
420 bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800); in bcm_phy_28nm_a0b0_afe_config_init()