195 static u32 adin_get_reg_value(struct phy_device *phydev,  in adin_get_reg_value()  argument
200 	struct device *dev = &phydev->mdio.dev;  in adin_get_reg_value()
209 		phydev_warn(phydev,  in adin_get_reg_value()
218 static int adin_config_rgmii_mode(struct phy_device *phydev)  in adin_config_rgmii_mode()  argument
223 	if (!phy_interface_is_rgmii(phydev))  in adin_config_rgmii_mode()
224 		return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,  in adin_config_rgmii_mode()
228 	reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);  in adin_config_rgmii_mode()
234 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in adin_config_rgmii_mode()
235 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {  in adin_config_rgmii_mode()
238 		val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",  in adin_config_rgmii_mode()
247 	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||  in adin_config_rgmii_mode()
248 	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {  in adin_config_rgmii_mode()
251 		val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",  in adin_config_rgmii_mode()
260 	return phy_write_mmd(phydev, MDIO_MMD_VEND1,  in adin_config_rgmii_mode()
264 static int adin_config_rmii_mode(struct phy_device *phydev)  in adin_config_rmii_mode()  argument
269 	if (phydev->interface != PHY_INTERFACE_MODE_RMII)  in adin_config_rmii_mode()
270 		return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,  in adin_config_rmii_mode()
274 	reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);  in adin_config_rmii_mode()
280 	val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",  in adin_config_rmii_mode()
287 	return phy_write_mmd(phydev, MDIO_MMD_VEND1,  in adin_config_rmii_mode()
291 static int adin_get_downshift(struct phy_device *phydev, u8 *data)  in adin_get_downshift()  argument
295 	val = phy_read(phydev, ADIN1300_PHY_CTRL2);  in adin_get_downshift()
299 	cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);  in adin_get_downshift()
311 static int adin_set_downshift(struct phy_device *phydev, u8 cnt)  in adin_set_downshift()  argument
317 		return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,  in adin_set_downshift()
326 	rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,  in adin_set_downshift()
332 	return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,  in adin_set_downshift()
336 static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)  in adin_get_edpd()  argument
340 	val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);  in adin_get_edpd()
357 static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)  in adin_set_edpd()  argument
362 		return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,  in adin_set_edpd()
379 	return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,  in adin_set_edpd()
384 static int adin_get_tunable(struct phy_device *phydev,  in adin_get_tunable()  argument
389 		return adin_get_downshift(phydev, data);  in adin_get_tunable()
391 		return adin_get_edpd(phydev, data);  in adin_get_tunable()
397 static int adin_set_tunable(struct phy_device *phydev,  in adin_set_tunable()  argument
402 		return adin_set_downshift(phydev, *(const u8 *)data);  in adin_set_tunable()
404 		return adin_set_edpd(phydev, *(const u16 *)data);  in adin_set_tunable()
410 static int adin_config_init(struct phy_device *phydev)  in adin_config_init()  argument
414 	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;  in adin_config_init()
416 	rc = adin_config_rgmii_mode(phydev);  in adin_config_init()
420 	rc = adin_config_rmii_mode(phydev);  in adin_config_init()
424 	rc = adin_set_downshift(phydev, 4);  in adin_config_init()
428 	rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);  in adin_config_init()
432 	phydev_dbg(phydev, "PHY is using mode '%s'\n",  in adin_config_init()
433 		   phy_modes(phydev->interface));  in adin_config_init()
438 static int adin_phy_ack_intr(struct phy_device *phydev)  in adin_phy_ack_intr()  argument
441 	int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);  in adin_phy_ack_intr()
446 static int adin_phy_config_intr(struct phy_device *phydev)  in adin_phy_config_intr()  argument
448 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED)  in adin_phy_config_intr()
449 		return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,  in adin_phy_config_intr()
452 	return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,  in adin_phy_config_intr()
456 static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,  in adin_cl45_to_adin_reg()  argument
471 	phydev_err(phydev,  in adin_cl45_to_adin_reg()
478 static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)  in adin_read_mmd()  argument
480 	struct mii_bus *bus = phydev->mdio.bus;  in adin_read_mmd()
481 	int phy_addr = phydev->mdio.addr;  in adin_read_mmd()
485 	adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);  in adin_read_mmd()
497 static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,  in adin_write_mmd()  argument
500 	struct mii_bus *bus = phydev->mdio.bus;  in adin_write_mmd()
501 	int phy_addr = phydev->mdio.addr;  in adin_write_mmd()
505 	adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);  in adin_write_mmd()
517 static int adin_config_mdix(struct phy_device *phydev)  in adin_config_mdix()  argument
524 	switch (phydev->mdix_ctrl) {  in adin_config_mdix()
537 	reg = phy_read(phydev, ADIN1300_PHY_CTRL1);  in adin_config_mdix()
551 	return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);  in adin_config_mdix()
554 static int adin_config_aneg(struct phy_device *phydev)  in adin_config_aneg()  argument
558 	ret = adin_config_mdix(phydev);  in adin_config_aneg()
562 	return genphy_config_aneg(phydev);  in adin_config_aneg()
565 static int adin_mdix_update(struct phy_device *phydev)  in adin_mdix_update()  argument
571 	reg = phy_read(phydev, ADIN1300_PHY_CTRL1);  in adin_mdix_update()
581 			phydev->mdix = ETH_TP_MDI_X;  in adin_mdix_update()
583 			phydev->mdix = ETH_TP_MDI;  in adin_mdix_update()
592 	reg = phy_read(phydev, ADIN1300_PHY_STATUS1);  in adin_mdix_update()
599 		phydev->mdix = ETH_TP_MDI_X;  in adin_mdix_update()
601 		phydev->mdix = ETH_TP_MDI;  in adin_mdix_update()
606 static int adin_read_status(struct phy_device *phydev)  in adin_read_status()  argument
610 	ret = adin_mdix_update(phydev);  in adin_read_status()
614 	return genphy_read_status(phydev);  in adin_read_status()
617 static int adin_soft_reset(struct phy_device *phydev)  in adin_soft_reset()  argument
622 	rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,  in adin_soft_reset()
631 	rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,  in adin_soft_reset()
637 static int adin_get_sset_count(struct phy_device *phydev)  in adin_get_sset_count()  argument
642 static void adin_get_strings(struct phy_device *phydev, u8 *data)  in adin_get_strings()  argument
652 static int adin_read_mmd_stat_regs(struct phy_device *phydev,  in adin_read_mmd_stat_regs()  argument
658 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);  in adin_read_mmd_stat_regs()
667 	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);  in adin_read_mmd_stat_regs()
677 static u64 adin_get_stat(struct phy_device *phydev, int i)  in adin_get_stat()  argument
680 	struct adin_priv *priv = phydev->priv;  in adin_get_stat()
685 		ret = adin_read_mmd_stat_regs(phydev, stat, &val);  in adin_get_stat()
689 		ret = phy_read(phydev, stat->reg1);  in adin_get_stat()
700 static void adin_get_stats(struct phy_device *phydev,  in adin_get_stats()  argument
706 	rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);  in adin_get_stats()
711 		data[i] = adin_get_stat(phydev, i);  in adin_get_stats()
714 static int adin_probe(struct phy_device *phydev)  in adin_probe()  argument
716 	struct device *dev = &phydev->mdio.dev;  in adin_probe()
723 	phydev->priv = priv;  in adin_probe()