Lines Matching +full:fixed +full:- +full:links

1 # SPDX-License-Identifier: GPL-2.0-only
20 	  loadable module or built-in.
31 	  third revision of the ASPEED MDIO register interface - the first two
105 	tristate "MMIO device-controlled MDIO bus multiplexers"
110 	  are controlled via a simple memory-mapped device, like an FPGA.
133 	tristate "GPIO lib-based bitbanged MDIO buses"
136 	---help---
137 	  Supports GPIO lib-based MDIO busses.
140 	  will be called mdio-gpio.
202 	tristate "APM X-Gene SoC MDIO bus controller"
206 	  APM X-Gene SoC's.
217 	  PHYlink models the link between the PHY and MAC, allowing fixed
218 	  configuration links, PHYs, and Serdes links with MAC level
238 	---help---
239 	  Adds support for a set of LED trigger events per-PHY.  Link
243 	  logical-or of all the link speed ones.
265 	  - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
266 	  - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
271 	---help---
276 	---help---
282 	  Currently supports the Asix Electronics PHY found in the X-Surf 100
287 	---help---
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364 	---help---
368 	tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
371 	---help---
372 	  Adds the platform "fixed" MDIO Bus to cover the boards that use
375 	  Currently tested with mpc866ads and mpc8349e-mitx.
379 	---help---
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489 	---help---
497 	tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch"