13 	u32 value = readl(ioaddr + XGMAC_DMA_MODE);  in dwxgmac2_dma_reset()
25 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);  in dwxgmac2_dma_init()
36 	u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));  in dwxgmac2_dma_init_chan()
52 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_init_rx_chan()
68 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_init_tx_chan()
80 	u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE);  in dwxgmac2_dma_axi()
136 		reg_space[i] = readl(ioaddr + i * 4);  in dwxgmac2_dma_dump_regs()
142 	u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));  in dwxgmac2_dma_rx_mode()
163 		u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel));  in dwxgmac2_dma_rx_mode()
211 	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));  in dwxgmac2_dma_rx_mode()
218 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));  in dwxgmac2_dma_tx_mode()
272 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_start_tx()
276 	value = readl(ioaddr + XGMAC_TX_CONFIG);  in dwxgmac2_dma_start_tx()
285 	value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_dma_stop_tx()
289 	value = readl(ioaddr + XGMAC_TX_CONFIG);  in dwxgmac2_dma_stop_tx()
298 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_start_rx()
302 	value = readl(ioaddr + XGMAC_RX_CONFIG);  in dwxgmac2_dma_start_rx()
311 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_dma_stop_rx()
319 	u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));  in dwxgmac2_dma_interrupt()
320 	u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));  in dwxgmac2_dma_interrupt()
365 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0);  in dwxgmac2_get_hw_feature()
381 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1);  in dwxgmac2_get_hw_feature()
410 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2);  in dwxgmac2_get_hw_feature()
422 	hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3);  in dwxgmac2_get_hw_feature()
460 	u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan));  in dwxgmac2_enable_tso()
472 	u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel));  in dwxgmac2_qmode()
473 	u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL);  in dwxgmac2_qmode()
491 	value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan));  in dwxgmac2_set_bfsize()
498 	u32 value = readl(ioaddr + XGMAC_RX_CONFIG);  in dwxgmac2_enable_sph()
504 	value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan));  in dwxgmac2_enable_sph()