19 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_axi()
78 	value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));  in dwmac4_dma_init_rx_chan()
92 	value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_dma_init_tx_chan()
109 	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));  in dwmac4_dma_init_channel()
122 	u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);  in dwmac4_dma_init()
142 		readl(ioaddr + DMA_CHAN_CONTROL(channel));  in _dwmac4_dump_dma_regs()
144 		readl(ioaddr + DMA_CHAN_TX_CONTROL(channel));  in _dwmac4_dump_dma_regs()
146 		readl(ioaddr + DMA_CHAN_RX_CONTROL(channel));  in _dwmac4_dump_dma_regs()
148 		readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(channel));  in _dwmac4_dump_dma_regs()
150 		readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));  in _dwmac4_dump_dma_regs()
152 		readl(ioaddr + DMA_CHAN_TX_END_ADDR(channel));  in _dwmac4_dump_dma_regs()
154 		readl(ioaddr + DMA_CHAN_RX_END_ADDR(channel));  in _dwmac4_dump_dma_regs()
156 		readl(ioaddr + DMA_CHAN_TX_RING_LEN(channel));  in _dwmac4_dump_dma_regs()
158 		readl(ioaddr + DMA_CHAN_RX_RING_LEN(channel));  in _dwmac4_dump_dma_regs()
160 		readl(ioaddr + DMA_CHAN_INTR_ENA(channel));  in _dwmac4_dump_dma_regs()
162 		readl(ioaddr + DMA_CHAN_RX_WATCHDOG(channel));  in _dwmac4_dump_dma_regs()
164 		readl(ioaddr + DMA_CHAN_SLOT_CTRL_STATUS(channel));  in _dwmac4_dump_dma_regs()
166 		readl(ioaddr + DMA_CHAN_CUR_TX_DESC(channel));  in _dwmac4_dump_dma_regs()
168 		readl(ioaddr + DMA_CHAN_CUR_RX_DESC(channel));  in _dwmac4_dump_dma_regs()
170 		readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(channel));  in _dwmac4_dump_dma_regs()
172 		readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(channel));  in _dwmac4_dump_dma_regs()
174 		readl(ioaddr + DMA_CHAN_STATUS(channel));  in _dwmac4_dump_dma_regs()
199 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));  in dwmac4_dma_rx_chan_op_mode()
270 	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));  in dwmac4_dma_rx_chan_op_mode()
278 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_dma_tx_chan_op_mode()
330 	u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0);  in dwmac4_get_hw_feature()
355 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE1);  in dwmac4_get_hw_feature()
365 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE2);  in dwmac4_get_hw_feature()
383 	hw_cap = readl(ioaddr + GMAC_HW_FEATURE3);  in dwmac4_get_hw_feature()
400 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
405 		value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan));  in dwmac4_enable_tso()
413 	u32 mtl_tx_op = readl(ioaddr + MTL_CHAN_TX_OP_MODE(channel));  in dwmac4_qmode()
426 	u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan));  in dwmac4_set_bfsize()