Lines Matching refs:GRF_CLR_BIT
72 #define GRF_CLR_BIT(nr) (BIT(nr+16)) macro
81 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
83 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
141 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
143 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
149 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
151 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
153 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
154 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
157 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
158 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
160 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
162 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
258 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
260 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
262 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
263 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
266 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
267 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
269 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
271 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
273 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
275 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
378 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
379 GRF_CLR_BIT(8))
380 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
383 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
384 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
387 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
388 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
390 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
392 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
396 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
398 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
496 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
498 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
500 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
501 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
504 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
505 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
507 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
509 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
511 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
513 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
622 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
623 GRF_CLR_BIT(11))
624 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
627 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
628 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
631 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
632 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
634 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
636 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
640 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
642 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
733 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
734 GRF_CLR_BIT(11))
735 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
738 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
739 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
742 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
743 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
745 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
747 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
751 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
753 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
844 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
845 GRF_CLR_BIT(11))
846 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
849 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
850 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
853 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
854 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
856 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
858 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
862 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
864 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
954 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
957 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
958 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
961 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
1009 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
1011 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))