136 	u32 delay_val = 0, fine_val = 0;  in mt2712_set_delay()  local
142 		delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay);  in mt2712_set_delay()
143 		delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay);  in mt2712_set_delay()
144 		delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv);  in mt2712_set_delay()
146 		delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
147 		delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
148 		delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
162 			delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
163 			delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
164 			delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
170 			delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
171 			delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
172 			delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
187 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);  in mt2712_set_delay()
188 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay);  in mt2712_set_delay()
189 		delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv);  in mt2712_set_delay()
191 		delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay);  in mt2712_set_delay()
192 		delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay);  in mt2712_set_delay()
193 		delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv);  in mt2712_set_delay()
199 	regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);  in mt2712_set_delay()