mcdi_pcol.h - OpenGrok cross reference for /Linux-v5.4/drivers/net/ethernet/sfc/mcdi

Lines Matching full:enum
376 /* enum: Info. */
378 /* enum: Warning. */
380 /* enum: Error. */
382 /* enum: Fatal. */
396 /* enum: Link is down or link speed could not be determined */
398 /* enum: 100Mbs */
400 /* enum: 1Gbs */
402 /* enum: 10Gbs */
404 /* enum: 40Gbs */
406 /* enum: 25Gbs */
408 /* enum: 50Gbs */
410 /* enum: 100Gbs */
426 /* enum: SRAM Access. */
434 /* enum: Descriptor loader reported failure */
436 /* enum: Descriptor ring empty and no EOP seen for packet */
438 /* enum: Overlength packet */
440 /* enum: Malformed option descriptor */
442 /* enum: Option descriptor part way through a packet */
444 /* enum: DMA or PIO data access error */
454 /* enum: PLL lost lock */
456 /* enum: Filter overflow (PDMA) */
458 /* enum: FIFO overflow (FPGA) */
460 /* enum: Merge queue overflow */
464 /* enum: AOE failed to load - no valid image? */
466 /* enum: AOE FC reported an exception */
468 /* enum: AOE FC watchdogged */
470 /* enum: AOE FC failed to start */
472 /* enum: Generic AOE fault - likely to have been reported via other means too
476 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
478 /* enum: AOE loaded successfully */
480 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
482 /* enum: AOE byteblaster connected/disconnected (Connection status in
486 /* enum: DDR ECC status update */
488 /* enum: PTP status update */
490 /* enum: FPGA header incorrect */
492 /* enum: FPGA Powered Off due to error in powering up FPGA */
494 /* enum: AOE FPGA load failed due to MC to MUM communication failure */
496 /* enum: Notify that invalid flash type detected */
498 /* enum: Notify that the attempt to run FPGA Controller firmware timedout */
500 /* enum: Failure to probe one or more FPGA boot flash chips */
502 /* enum: FPGA boot-flash contains an invalid image header */
504 /* enum: Failed to program clocks required by the FPGA */
506 /* enum: Notify that FPGA Controller is alive to serve MCDI requests */
512 /* enum: FC Assert happened, but the register information is not available */
514 /* enum: The register information for FC Assert is ready for readinng by driver
519 /* enum: Reading from NV failed */
521 /* enum: Invalid Magic Number if FPGA header */
523 /* enum: Invalid Silicon type detected in header */
525 /* enum: Unsupported VRatio */
527 /* enum: Unsupported DDR Type */
529 /* enum: DDR Voltage out of supported range */
531 /* enum: Unsupported DDR speed */
533 /* enum: Unsupported DDR size */
535 /* enum: Unsupported DDR rank */
539 /* enum: Primary boot flash */
541 /* enum: Secondary boot flash */
561 /* enum: MUM failed to load - no valid image? */
563 /* enum: MUM f/w reported an exception */
565 /* enum: MUM not kicking watchdog */
573 /* enum: Corrupted or bad SUC application. */
575 /* enum: SUC application reported an assert. */
577 /* enum: SUC application reported an exception. */
579 /* enum: SUC watchdog timer expired. */
593 /* enum: Event generated by host software */
595 /* enum: Bad assert. */
597 /* enum: PM Notice. */
599 /* enum: Command done. */
601 /* enum: Link change. */
603 /* enum: Sensor Event. */
605 /* enum: Schedule error. */
607 /* enum: Reboot. */
609 /* enum: Mac stats DMA. */
611 /* enum: Firmware alert. */
613 /* enum: Function level reset. */
615 /* enum: Transmit error */
617 /* enum: Tx flush has completed */
619 /* enum: PTP packet received timestamp */
621 /* enum: PTP NIC failure */
623 /* enum: PTP PPS event */
625 /* enum: Rx flush has completed */
627 /* enum: Receive error */
629 /* enum: AOE fault */
631 /* enum: Network port calibration failed (VCAL). */
633 /* enum: HW PPS event */
635 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
639 /* enum: the MC has detected a parity error */
641 /* enum: the MC has detected a correctable error */
643 /* enum: the MC has detected an uncorrectable error */
645 /* enum: The MC has entered offline BIST mode */
647 /* enum: PTP tick event providing current NIC time */
649 /* enum: MUM fault */
651 /* enum: notify the designated PF of a new authorization request */
653 /* enum: notify a function that awaits an authorization that its request has
657 /* enum: MCDI command accepted. New commands can be issued but this command is
661 /* enum: The MC has detected a fault on the SUC */
663 /* enum: Artificial event generated by host and posted via MC for test
795 /* enum: Info. */
797 /* enum: Warning. */
799 /* enum: Error. */
801 /* enum: Fatal. */
807 #define          FCDI_EVENT_LINK_DOWN 0x0 /* enum */
808 #define          FCDI_EVENT_LINK_UP 0x1 /* enum */
817 /* enum: The FC was rebooted. */
819 /* enum: Bad assert. */
821 /* enum: DDR3 test result. */
823 /* enum: Link status. */
825 /* enum: A timed read is ready to be serviced. */
827 /* enum: One or more PPS IN events */
829 /* enum: Tick event from PTP clock */
831 /* enum: ECC error counters */
833 /* enum: Current status of PTP */
835 /* enum: Port id config to map MC-FC port idx */
837 /* enum: Boot result or error code */
841 #define          FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
842 #define          FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
861 #define          FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
862 #define          FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
863 #define          FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
882 /*            Enum values, see field(s): */
927 /* enum: Info. */
929 /* enum: Warning. */
931 /* enum: Error. */
933 /* enum: Fatal. */
939 /*             Enum values, see field(s): */
965 /* enum: The MUM was rebooted. */
967 /* enum: Bad assert. */
969 /* enum: Sensor failure. */
971 /* enum: Link fault has been asserted, or has cleared. */
991 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
992 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
993 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
994 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
995 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
996 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
997 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
998 #define          MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1003 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1004 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1005 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1006 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1007 #define          MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1082 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT (see below) */
1084 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT and
1088 /* enum: Deprecated; equivalent to setting BOOT_MAGIC_PRESENT,
1113 /* enum: Control should return to the caller rather than jumping */
1154 /* enum: indicates that the MC wasn't flash booted */
1187 /* enum: No assertions have failed. */
1189 /* enum: A system-level assertion has failed. */
1191 /* enum: A thread-level assertion has failed. */
1193 /* enum: The system was reset by the watchdog. */
1195 /* enum: An illegal address trap stopped the system (huntington and later) */
1204 /* enum: A magic value hinting that the value in this register at the time of
1229 /* enum: UART. */
1231 /* enum: Event queue. */
1262 /* enum: Reserved version number to indicate "any" version. */
1264 /* enum: Bootrom version value for Siena. */
1266 /* enum: Bootrom version value for Huntington. */
1268 /* enum: Bootrom version value for Medford2. */
1275 /*            Enum values, see field(s): */
1291 /*            Enum values, see field(s): */
1320 /* enum: Enable PTP packet timestamping operation. */
1322 /* enum: Disable PTP packet timestamping operation. */
1324 /* enum: Send a PTP packet. This operation is used on Siena and Huntington.
1329 /* enum: Read the current NIC time. */
1331 /* enum: Get the current PTP status. Note that the clock frequency returned (in
1335 /* enum: Adjust the PTP NIC's time. */
1337 /* enum: Synchronize host and NIC time. */
1339 /* enum: Basic manufacturing tests. Siena PTP adapters only. */
1341 /* enum: Packet based manufacturing tests. Siena PTP adapters only. */
1343 /* enum: Reset some of the PTP related statistics */
1345 /* enum: Debug operations to MC. */
1347 /* enum: Read an FPGA register. Siena PTP adapters only. */
1349 /* enum: Write an FPGA register. Siena PTP adapters only. */
1351 /* enum: Apply an offset to the NIC clock */
1353 /* enum: Change the frequency correction applied to the NIC clock */
1355 /* enum: Set the MC packet filter VLAN tags for received PTP packets.
1359 /* enum: Set the MC packet filter UUID for received PTP packets. Deprecated for
1363 /* enum: Set the MC packet filter Domain for received PTP packets. Deprecated
1367 /* enum: Set the clock source. Required for snapper tests on Huntington and
1371 /* enum: Reset value of Timer Reg. Not implemented. */
1373 /* enum: Enable the forwarding of PPS events to the host */
1375 /* enum: Get the time format used by this NIC for PTP operations */
1377 /* enum: Get the clock attributes. NOTE- extended version of
1381 /* enum: Get corrections that should be applied to the various different
1385 /* enum: Subscribe to receive periodic time events indicating the current NIC
1389 /* enum: Unsubscribe to stop receiving time events */
1391 /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS
1395 /* enum: Set the PTP sync status. Status is used by firmware to report to event
1399 /* enum: Above this for future use. */
1414 /* enum: PTP, version 1 */
1416 /* enum: PTP, version 1, with VLAN headers - deprecated */
1418 /* enum: PTP, version 2 */
1420 /* enum: PTP, version 2, with VLAN headers - deprecated */
1422 /* enum: PTP, version 2, with improved UUID filtering */
1424 /* enum: FCoE (seconds and microseconds) */
1483 /* enum: Number of fractional bits in frequency adjustment */
1485 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1514 /* enum: Number of fractional bits in frequency adjustment */
1516 /* enum: Number of fractional bits in frequency adjustment when FP44_FREQ_ADJ
1666 /*            Enum values, see field(s): */
1720 /* enum: Internal. */
1722 /* enum: External. */
1739 /* enum: Enable */
1741 /* enum: Disable */
1791 /* enum: Unsubscribe a single queue */
1793 /* enum: Unsubscribe all queues */
1818 /* enum: Host System clock and NIC clock are not in sync */
1820 /* enum: Host System clock and NIC clock are synchronized */
1976 /* enum: Successful test */
1978 /* enum: FPGA load failed */
1980 /* enum: FPGA version invalid */
1982 /* enum: FPGA registers incorrect */
1984 /* enum: Oscillator possibly not working? */
1986 /* enum: Timestamps not increasing */
1988 /* enum: Mismatched packet count */
1990 /* enum: Mismatched packet count (Siena filter and FPGA) */
1992 /* enum: Not enough packets to perform timestamp check */
1994 /* enum: Timestamp trigger GPIO not working */
1996 /* enum: Insufficient PPS events to perform checks */
1998 /* enum: PPS time event period not sufficiently close to 1s. */
2000 /* enum: PPS time event nS reading not sufficiently close to zero. */
2002 /* enum: PTP peripheral registers incorrect */
2004 /* enum: Failed to read time from PTP peripheral */
2036  * be assumed. Note this enum is deprecated. Do not add to it- use the
2041 /* enum: Times are in seconds and nanoseconds */
2043 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2045 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2057 /* enum: Times are in seconds and nanoseconds */
2059 /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */
2061 /* enum: Major register has units of seconds, minor 2^-27s per tick */
2063 /* enum: Major register units are seconds, minor units are quarter nanoseconds
2134 /*            Enum values, see field(s): */
2217 /* enum: OCSD (Option Card Sensor Data) sub-command. */
2219 /* enum: Last known valid HP sub-command. */
2237 /* enum: OCSD stopped for this card. */
2239 /* enum: OCSD was successfully started with the address provided. */
2241 /* enum: OCSD was already started for this card. */
2282 /* enum: Internal. */
2284 /* enum: External. */
2292 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2310 /* enum: Good. */
2329 /* enum: Internal. */
2331 /* enum: External. */
2339 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
2357 /* enum: Good. */
2717 /* enum: Prefer to use full featured firmware */
2719 /* enum: Prefer to use firmware with fewer features but lower latency */
2721 /* enum: Prefer to use firmware for SolarCapture packed stream mode */
2723 /* enum: Prefer to use firmware with fewer features and simpler TX event
2727 /* enum: Reserved value */
2729 /* enum: Prefer to use firmware with additional "rules engine" filtering
2733 /* enum: Prefer to use firmware with additional DPDK support */
2735 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
2739 /* enum: Only this option is allowed for non-admin functions */
2756 /* enum: Labels the lowest-numbered function visible to the OS */
2758 /* enum: The function can control the link state of the physical port it is
2762 /* enum: The function can perform privileged operations */
2764 /* enum: The function does not have an active port associated with it. The port
2768 /* enum: If set, indicates that VI spreading is currently enabled. Will always
3048 /* enum: Xaui. */
3050 /* enum: CX4. */
3052 /* enum: KX4. */
3054 /* enum: XFP Far. */
3056 /* enum: SFP+. */
3058 /* enum: 10GBaseT. */
3060 /* enum: QSFP+. */
3064 /* enum: Native clause 22 */
3066 #define          MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
3067 #define          MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
3068 #define          MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
3069 #define          MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
3070 #define          MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
3071 #define          MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
3072 #define          MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
3073 /* enum: Clause22 proxied over clause45 by PHY. */
3075 #define          MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
3076 #define          MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
3095 /* enum: Run the PHY's short cable BIST. */
3097 /* enum: Run the PHY's long cable BIST. */
3099 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
3101 /* enum: Run the MC loopback tests. */
3103 /* enum: Run the PHY's standard BIST. */
3105 /* enum: Run MC RAM test. */
3107 /* enum: Run Port RAM test. */
3109 /* enum: Run register test. */
3137 /* enum: Running. */
3139 /* enum: Passed. */
3141 /* enum: Failed. */
3143 /* enum: Timed-out. */
3153 /*            Enum values, see field(s): */
3166 /* enum: Ok. */
3168 /* enum: Open. */
3170 /* enum: Intra-pair short. */
3172 /* enum: Inter-pair short. */
3174 /* enum: Busy. */
3179 /*            Enum values, see field(s): */
3184 /*            Enum values, see field(s): */
3189 /*            Enum values, see field(s): */
3197 /*            Enum values, see field(s): */
3201 /* enum: Complete. */
3203 /* enum: Bus switch off I2C write. */
3205 /* enum: Bus switch off I2C no access IO exp. */
3207 /* enum: Bus switch off I2C no access module. */
3209 /* enum: IO exp I2C configure. */
3211 /* enum: Bus switch I2C no cross talk. */
3213 /* enum: Module presence. */
3215 /* enum: Module ID I2C access. */
3217 /* enum: Module ID sane value. */
3225 /*            Enum values, see field(s): */
3229 /* enum: Test has completed. */
3231 /* enum: RAM test - walk ones. */
3233 /* enum: RAM test - walk zeros. */
3235 /* enum: RAM test - walking inversions zeros/ones. */
3237 /* enum: RAM test - walking inversions checkerboard. */
3239 /* enum: Register test - set / clear individual bits. */
3241 /* enum: ECC error detected. */
3249 /* enum: MC MIPS bus. */
3251 /* enum: CSR IREG bus. */
3253 /* enum: RX0 DPCPU bus. */
3255 /* enum: TX0 DPCPU bus. */
3257 /* enum: TX1 DPCPU bus. */
3259 /* enum: RX0 DICPU bus. */
3261 /* enum: TX DICPU bus. */
3263 /* enum: RX1 DPCPU bus. */
3265 /* enum: RX1 DICPU bus. */
3326 /* enum: None. */
3328 /* enum: Data. */
3330 /* enum: GMAC. */
3332 /* enum: XGMII. */
3334 /* enum: XGXS. */
3336 /* enum: XAUI. */
3338 /* enum: GMII. */
3340 /* enum: SGMII. */
3342 /* enum: XGBR. */
3344 /* enum: XFI. */
3346 /* enum: XAUI Far. */
3348 /* enum: GMII Far. */
3350 /* enum: SGMII Far. */
3352 /* enum: XFI Far. */
3354 /* enum: GPhy. */
3356 /* enum: PhyXS. */
3358 /* enum: PCS. */
3360 /* enum: PMA-PMD. */
3362 /* enum: Cross-Port. */
3364 /* enum: XGMII-Wireside. */
3366 /* enum: XAUI Wireside. */
3368 /* enum: XAUI Wireside Far. */
3370 /* enum: XAUI Wireside near. */
3372 /* enum: GMII Wireside. */
3374 /* enum: XFI Wireside. */
3376 /* enum: XFI Wireside Far. */
3378 /* enum: PhyXS Wireside. */
3380 /* enum: PMA lanes MAC-Serdes. */
3382 /* enum: KR Serdes Parallel (Encoder). */
3384 /* enum: KR Serdes Serial. */
3386 /* enum: PMA lanes MAC-Serdes Wireside. */
3388 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3390 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3392 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3394 /* enum: KR Serdes Serial Wireside. */
3396 /* enum: Near side of AOE Siena side port */
3398 /* enum: Medford Wireside datapath loopback */
3400 /* enum: Force link up without setting up any physical loopback (snapper use
3409 /*            Enum values, see field(s): */
3416 /*            Enum values, see field(s): */
3423 /*            Enum values, see field(s): */
3430 /*            Enum values, see field(s): */
3442 /* enum: None. */
3444 /* enum: Data. */
3446 /* enum: GMAC. */
3448 /* enum: XGMII. */
3450 /* enum: XGXS. */
3452 /* enum: XAUI. */
3454 /* enum: GMII. */
3456 /* enum: SGMII. */
3458 /* enum: XGBR. */
3460 /* enum: XFI. */
3462 /* enum: XAUI Far. */
3464 /* enum: GMII Far. */
3466 /* enum: SGMII Far. */
3468 /* enum: XFI Far. */
3470 /* enum: GPhy. */
3472 /* enum: PhyXS. */
3474 /* enum: PCS. */
3476 /* enum: PMA-PMD. */
3478 /* enum: Cross-Port. */
3480 /* enum: XGMII-Wireside. */
3482 /* enum: XAUI Wireside. */
3484 /* enum: XAUI Wireside Far. */
3486 /* enum: XAUI Wireside near. */
3488 /* enum: GMII Wireside. */
3490 /* enum: XFI Wireside. */
3492 /* enum: XFI Wireside Far. */
3494 /* enum: PhyXS Wireside. */
3496 /* enum: PMA lanes MAC-Serdes. */
3498 /* enum: KR Serdes Parallel (Encoder). */
3500 /* enum: KR Serdes Serial. */
3502 /* enum: PMA lanes MAC-Serdes Wireside. */
3504 /* enum: KR Serdes Parallel Wireside (Full PCS). */
3506 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
3508 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
3510 /* enum: KR Serdes Serial Wireside. */
3512 /* enum: Near side of AOE Siena side port */
3514 /* enum: Medford Wireside datapath loopback */
3516 /* enum: Force link up without setting up any physical loopback (snapper use
3525 /*            Enum values, see field(s): */
3532 /*            Enum values, see field(s): */
3539 /*            Enum values, see field(s): */
3546 /*            Enum values, see field(s): */
3553 /*            Enum values, see field(s): */
3560 /*            Enum values, see field(s): */
3567 /*            Enum values, see field(s): */
3574 /* enum: None, AN disabled or not supported */
3576 /* enum: Clause 28 - BASE-T */
3578 /* enum: Clause 37 - BASE-X */
3580 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
3592 /* enum: No FEC */
3594 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
3596 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
3634 /*            Enum values, see field(s): */
3653 /*            Enum values, see field(s): */
3686 /*            Enum values, see field(s): */
3705 /*            Enum values, see field(s): */
3729 /*            Enum values, see field(s): */
3734 /*            Enum values, see field(s): */
3786 /*            Enum values, see field(s): */
3811 #define          MC_CMD_LED_OFF 0x0 /* enum */
3812 #define          MC_CMD_LED_ON 0x1 /* enum */
3813 #define          MC_CMD_LED_DEFAULT 0x2 /* enum */
3848 /* enum: Flow control is off. */
3850 /* enum: Respond to flow control. */
3852 /* enum: Respond to and Issue flow control. */
3854 /* enum: Auto neg flow control. */
3856 /* enum: Priority flow control (eftest builds only). */
3858 /* enum: Issue flow control. */
3886 /* enum: Flow control is off. */
3888 /* enum: Respond to flow control. */
3890 /* enum: Respond to and Issue flow control. */
3892 /* enum: Auto neg flow control. */
3894 /* enum: Priority flow control (eftest builds only). */
3896 /* enum: Issue flow control. */
3962 /* enum: OUI. */
3964 /* enum: PMA-PMD Link Up. */
3966 /* enum: PMA-PMD RX Fault. */
3968 /* enum: PMA-PMD TX Fault. */
3970 /* enum: PMA-PMD Signal */
3972 /* enum: PMA-PMD SNR A. */
3974 /* enum: PMA-PMD SNR B. */
3976 /* enum: PMA-PMD SNR C. */
3978 /* enum: PMA-PMD SNR D. */
3980 /* enum: PCS Link Up. */
3982 /* enum: PCS RX Fault. */
3984 /* enum: PCS TX Fault. */
3986 /* enum: PCS BER. */
3988 /* enum: PCS Block Errors. */
3990 /* enum: PhyXS Link Up. */
3992 /* enum: PhyXS RX Fault. */
3994 /* enum: PhyXS TX Fault. */
3996 /* enum: PhyXS Align. */
3998 /* enum: PhyXS Sync. */
4000 /* enum: AN link-up. */
4002 /* enum: AN Complete. */
4004 /* enum: AN 10GBaseT Status. */
4006 /* enum: Clause 22 Link-Up. */
4008 /* enum: (Last entry) */
4071 #define          MC_CMD_MAC_GENERATION_START 0x0 /* enum */
4072 #define          MC_CMD_MAC_DMABUF_START 0x1 /* enum */
4073 #define          MC_CMD_MAC_TX_PKTS 0x1 /* enum */
4074 #define          MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
4075 #define          MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
4076 #define          MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
4077 #define          MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
4078 #define          MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
4079 #define          MC_CMD_MAC_TX_BYTES 0x7 /* enum */
4080 #define          MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
4081 #define          MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
4082 #define          MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
4083 #define          MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
4084 #define          MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
4085 #define          MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
4086 #define          MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
4087 #define          MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
4088 #define          MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
4089 #define          MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
4090 #define          MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
4091 #define          MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
4092 #define          MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
4093 #define          MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
4094 #define          MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
4095 #define          MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
4096 #define          MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
4097 #define          MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
4098 #define          MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
4099 #define          MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
4100 #define          MC_CMD_MAC_RX_PKTS 0x1c /* enum */
4101 #define          MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
4102 #define          MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
4103 #define          MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
4104 #define          MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
4105 #define          MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
4106 #define          MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
4107 #define          MC_CMD_MAC_RX_BYTES 0x23 /* enum */
4108 #define          MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
4109 #define          MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
4110 #define          MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
4111 #define          MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
4112 #define          MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
4113 #define          MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
4114 #define          MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
4115 #define          MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
4116 #define          MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
4117 #define          MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
4118 #define          MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
4119 #define          MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
4120 #define          MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
4121 #define          MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
4122 #define          MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
4123 #define          MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
4124 #define          MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
4125 #define          MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
4126 #define          MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
4127 #define          MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
4128 #define          MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
4129 #define          MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
4130 #define          MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
4131 #define          MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
4132 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4136 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
4140 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4144 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
4148 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4152 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4156 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
4160 /* enum: RXDP counter: Number of packets dropped due to the queue being
4164 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
4168 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
4172 /* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
4176 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
4180 #define          MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
4181 #define          MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
4182 #define          MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
4183 #define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
4184 #define          MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
4185 #define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
4186 #define          MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
4187 #define          MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
4188 #define          MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
4189 #define          MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
4190 #define          MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
4191 #define          MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
4192 #define          MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
4193 #define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
4194 #define          MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
4195 #define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
4196 #define          MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
4197 #define          MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
4198 #define          MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
4199 #define          MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
4200 /* enum: Start of GMAC stats buffer space, for Siena only. */
4202 /* enum: End of GMAC stats buffer space, for Siena only. */
4204 /* enum: GENERATION_END value, used together with GENERATION_START to verify
4215 #define          MC_CMD_MAC_NSTATS 0x61 /* enum */
4227 /* enum: Start of FEC stats buffer space, Medford2 and up */
4229 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
4232 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
4235 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
4237 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
4239 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
4241 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
4243 /* enum: This includes the space at offset 103 which is the final
4247 /*            Other enum values, see field(s): */
4260 /* enum: Start of CTPIO stats buffer space, Medford2 and up */
4262 /* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
4266 /* enum: Number of times a CTPIO send wrote beyond frame end (informational
4270 /* enum: Number of CTPIO failures because the TX doorbell was written before
4274 /* enum: Number of CTPIO failures because the internal FIFO overflowed */
4276 /* enum: Number of CTPIO failures because the host did not deliver data fast
4280 /* enum: Number of CTPIO failures because the host did not deliver all the
4284 /* enum: Number of CTPIO failures because the frame data arrived out of order
4288 /* enum: Number of CTPIO failures because the host started a new frame before
4292 /* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
4296 /* enum: Number of CTPIO fallbacks because another VI on the same port was
4300 /* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
4303 /* enum: Number of CTPIO fallbacks because length in header was less than 29
4307 /* enum: Total number of successful CTPIO sends on this port */
4309 /* enum: Total number of CTPIO fallbacks on this port */
4311 /* enum: Total number of CTPIO poisoned frames on this port, whether erased or
4315 /* enum: Total number of CTPIO erased frames on this port */
4317 /* enum: This includes the space at offset 120 which is the final
4321 /*            Other enum values, see field(s): */
4366 #define          MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
4429 #define          MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
4430 #define          MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
4434 /* enum: Magic */
4436 /* enum: MS Windows Magic */
4438 /* enum: IPv4 Syn */
4440 /* enum: IPv6 Syn */
4442 /* enum: Bitmap */
4444 /* enum: Link */
4446 /* enum: (Above this for future use) */
4559 #define          MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
4560 #define          MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
4600 /* enum: Disabled callisto. */
4602 /* enum: MC firmware. */
4604 /* enum: MC backup firmware. */
4606 /* enum: Static configuration Port0. */
4608 /* enum: Static configuration Port1. */
4610 /* enum: Dynamic configuration Port0. */
4612 /* enum: Dynamic configuration Port1. */
4614 /* enum: Expansion Rom. */
4616 /* enum: Expansion Rom Configuration Port0. */
4618 /* enum: Expansion Rom Configuration Port1. */
4620 /* enum: Phy Configuration Port0. */
4622 /* enum: Phy Configuration Port1. */
4624 /* enum: Log. */
4626 /* enum: FPGA image. */
4628 /* enum: FPGA backup image */
4630 /* enum: FC firmware. */
4632 /* enum: FC backup firmware. */
4634 /* enum: CPLD image. */
4636 /* enum: Licensing information. */
4638 /* enum: FC Log. */
4640 /* enum: Additional flash on FPGA. */
4657 /*            Enum values, see field(s): */
4664 /*            Enum values, see field(s): */
4693 /*            Enum values, see field(s): */
4741 /*            Enum values, see field(s): */
4752 /*            Enum values, see field(s): */
4777 /*            Enum values, see field(s): */
4789 /*            Enum values, see field(s): */
4806 /* enum: Same as omitting MODE: caller sees data in current partition unless it
4811 /* enum: Read from the current partition of an A/B pair, even if holding the
4815 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
4846 /*            Enum values, see field(s): */
4875 /*            Enum values, see field(s): */
4906 /*            Enum values, see field(s): */
4919 /*            Enum values, see field(s): */
4952 /* enum: Invalid return code; only non-zero values are defined. Defined as
4956 /* enum: Verify succeeded without any errors. */
4958 /* enum: CMS format verification failed due to an internal error. */
4960 /* enum: Invalid CMS format in image metadata. */
4962 /* enum: Message digest verification failed due to an internal error. */
4964 /* enum: Error in message digest calculated over the reflash-header, payload
4968 /* enum: Signature verification failed due to an internal error. */
4970 /* enum: There are no valid signatures in the image. */
4972 /* enum: Trusted approvers verification failed due to an internal error. */
4974 /* enum: The Trusted approver's list is empty. */
4976 /* enum: Signature chain verification failed due to an internal error. */
4978 /* enum: The signers of the signatures in the image are not listed in the
4982 /* enum: The image contains a test-signed certificate, but the adapter accepts
4986 /* enum: The image has a lower security level than the current firmware. */
5016 #define          MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
5058 /* enum: Normal. */
5060 /* enum: Power-on Reset. */
5062 /* enum: Snapper. */
5064 /* enum: snapper fake POR */
5130 /* enum: Controller temperature: degC */
5132 /* enum: Phy common temperature: degC */
5134 /* enum: Controller cooling: bool */
5136 /* enum: Phy 0 temperature: degC */
5138 /* enum: Phy 0 cooling: bool */
5140 /* enum: Phy 1 temperature: degC */
5142 /* enum: Phy 1 cooling: bool */
5144 /* enum: 1.0v power: mV */
5146 /* enum: 1.2v power: mV */
5148 /* enum: 1.8v power: mV */
5150 /* enum: 2.5v power: mV */
5152 /* enum: 3.3v power: mV */
5154 /* enum: 12v power: mV */
5156 /* enum: 1.2v analogue power: mV */
5158 /* enum: reference voltage: mV */
5160 /* enum: AOE FPGA power: mV */
5162 /* enum: AOE FPGA temperature: degC */
5164 /* enum: AOE FPGA PSU temperature: degC */
5166 /* enum: AOE PSU temperature: degC */
5168 /* enum: Fan 0 speed: RPM */
5170 /* enum: Fan 1 speed: RPM */
5172 /* enum: Fan 2 speed: RPM */
5174 /* enum: Fan 3 speed: RPM */
5176 /* enum: Fan 4 speed: RPM */
5178 /* enum: AOE FPGA input power: mV */
5180 /* enum: AOE FPGA current: mA */
5182 /* enum: AOE FPGA input current: mA */
5184 /* enum: NIC power consumption: W */
5186 /* enum: 0.9v power voltage: mV */
5188 /* enum: 0.9v power current: mA */
5190 /* enum: 1.2v power current: mA */
5192 /* enum: Not a sensor: reserved for the next page flag */
5194 /* enum: 0.9v power voltage (at ADC): mV */
5196 /* enum: Controller temperature 2: degC */
5198 /* enum: Voltage regulator internal temperature: degC */
5200 /* enum: 0.9V voltage regulator temperature: degC */
5202 /* enum: 1.2V voltage regulator temperature: degC */
5204 /* enum: controller internal temperature sensor voltage (internal ADC): mV */
5206 /* enum: controller internal temperature (internal ADC): degC */
5208 /* enum: controller internal temperature sensor voltage (external ADC): mV */
5210 /* enum: controller internal temperature (external ADC): degC */
5212 /* enum: ambient temperature: degC */
5214 /* enum: air flow: bool */
5216 /* enum: voltage between VSS08D and VSS08D at CSR: mV */
5218 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
5220 /* enum: Hotpoint temperature: degC */
5222 /* enum: Port 0 PHY power switch over-current: bool */
5224 /* enum: Port 1 PHY power switch over-current: bool */
5226 /* enum: Mop-up microcontroller reference voltage: mV */
5228 /* enum: 0.9v power phase A voltage: mV */
5230 /* enum: 0.9v power phase A current: mA */
5232 /* enum: 0.9V voltage regulator phase A temperature: degC */
5234 /* enum: 0.9v power phase B voltage: mV */
5236 /* enum: 0.9v power phase B current: mA */
5238 /* enum: 0.9V voltage regulator phase B temperature: degC */
5240 /* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
5242 /* enum: CCOM AVREG 1v2 supply (external ADC): mV */
5244 /* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
5246 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */
5248 /* enum: CCOM RTS temperature: degC */
5250 /* enum: Not a sensor: reserved for the next page flag */
5252 /* enum: controller internal temperature sensor voltage on master core
5256 /* enum: controller internal temperature on master core (internal ADC): degC */
5258 /* enum: controller internal temperature sensor voltage on master core
5262 /* enum: controller internal temperature on master core (external ADC): degC */
5264 /* enum: controller internal temperature on slave core sensor voltage (internal
5268 /* enum: controller internal temperature on slave core (internal ADC): degC */
5270 /* enum: controller internal temperature on slave core sensor voltage (external
5274 /* enum: controller internal temperature on slave core (external ADC): degC */
5276 /* enum: Voltage supplied to the SODIMMs from their power supply: mV */
5278 /* enum: Temperature of SODIMM 0 (if installed): degC */
5280 /* enum: Temperature of SODIMM 1 (if installed): degC */
5282 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
5284 /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
5286 /* enum: Controller die temperature (TDIODE): degC */
5288 /* enum: Board temperature (front): degC */
5290 /* enum: Board temperature (back): degC */
5292 /* enum: 1.8v power current: mA */
5294 /* enum: 2.5v power current: mA */
5296 /* enum: 3.3v power current: mA */
5298 /* enum: 12v power current: mA */
5300 /* enum: 1.3v power: mV */
5302 /* enum: 1.3v power current: mA */
5304 /* enum: Not a sensor: reserved for the next page flag */
5320 /*            Enum values, see field(s): */
5406 /* enum: Ok. */
5408 /* enum: Breached warning threshold. */
5410 /* enum: Breached fatal threshold. */
5412 /* enum: Fault with sensor. */
5414 /* enum: Sensor is working but does not currently have a reading. */
5416 /* enum: Sensor initialisation failed. */
5422 /*            Enum values, see field(s): */
5445 /* enum: Ok. */
5447 /* enum: Faulty. */
5499 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
5500 #define          MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
5586 /* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
5590 /* enum: Assert using assert(0); */
5592 /* enum: Deliberately trigger a watchdog */
5594 /* enum: Deliberately trigger a trap by loading from an invalid address */
5596 /* enum: Deliberately trigger a trap by storing to an invalid address */
5598 /* enum: Jump to an invalid address */
5622 /* enum: Bug 17230 work around. */
5624 /* enum: Bug 35388 work around (unsafe EVQ writes). */
5626 /* enum: Bug35017 workaround (A64 tables must be identity map) */
5628 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
5630 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
5636 /* enum: Bug 26807 features present in firmware (multicast filter chaining)
5644 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
5709 /*            Enum values, see field(s): */
5716 /* enum: Passed. */
5718 /* enum: Failed. */
5720 /* enum: Not supported. */
5761 /* enum: Out. */
5763 /* enum: In. */
5781 /*            Enum values, see field(s): */
5938 /* enum: Return to factory default settings */
5940 /* enum: Set MAC address */
5942 /* enum: Get MAC address */
5944 /* enum: Set UEFI/GPXE boot mode */
5946 /* enum: Get UEFI/GPXE boot mode */
6028 /* enum: NULL MCDI command to MUM */
6030 /* enum: Get MUM version */
6032 /* enum: Issue raw I2C command to MUM */
6034 /* enum: Read from registers on devices connected to MUM. */
6036 /* enum: Write to registers on devices connected to MUM. */
6038 /* enum: Control UART logging. */
6040 /* enum: Operations on MUM GPIO lines */
6042 /* enum: Get sensor readings from MUM */
6044 /* enum: Initiate clock programming on the MUM */
6046 /* enum: Initiate FPGA load from flash on the MUM */
6048 /* enum: Request sensor reading from MUM ADC resulting from earlier request via
6052 /* enum: Send commands relating to the QSFP ports via the MUM for PHY
6056 /* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage
6081 /* enum: Hittite HMC1035 clock generator on Sorrento board */
6083 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
6102 /* enum: Hittite HMC1035 clock generator on Sorrento board */
6142 #define          MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
6163 #define          MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
6164 #define          MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
6165 #define          MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
6166 #define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
6167 #define          MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
6168 #define          MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
6225 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
6226 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
6227 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
6228 #define          MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
6286 #define          MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
6287 #define          MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
6288 #define          MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
6323 #define          MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
6324 #define          MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
6325 #define          MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
6326 #define          MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
6327 #define          MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
6328 #define          MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
6584 /* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */
6586 /* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */
6588 /* enum: Total number of SODIMM banks */
6596 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
6597 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
6598 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
6599 #define          MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
6600 /* enum: Values 5-15 are reserved for future usage */
6608 /* enum: No module present */
6610 /* enum: Module present supported and powered on */
6612 /* enum: Module present but bad type */
6614 /* enum: Module present but incompatible voltage */
6616 /* enum: Module present but unknown SPD */
6618 /* enum: Module present but slot cannot support it */
6620 /* enum: Modules may or may not be present, but cannot establish contact by I2C
6626 /* MC_CMD_RESOURCE_SPECIFIER enum */
6627 /* enum: Any */
6629 /* enum: None */
6636 /* enum: An invalid port handle. */
6638 /* enum: The port assigned to this function.. */
6640 /* enum: External network port 0 */
6642 /* enum: External network port 1 */
6644 /* enum: External network port 2 */
6646 /* enum: External network port 3 */
6658 /* enum: Insert the VLAN. */
6660 /* enum: Replace the VLAN if already present. */
6687 /* enum: Primary MC firmware partition */
6689 /* enum: Secondary MC firmware partition */
6691 /* enum: Expansion ROM partition */
6693 /* enum: Static configuration TLV partition */
6695 /* enum: Dynamic configuration TLV partition */
6697 /* enum: Expansion ROM configuration data for port 0 */
6699 /* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
6701 /* enum: Expansion ROM configuration data for port 1 */
6703 /* enum: Expansion ROM configuration data for port 2 */
6705 /* enum: Expansion ROM configuration data for port 3 */
6707 /* enum: Non-volatile log output partition */
6709 /* enum: Non-volatile log output of second core on dual-core device */
6711 /* enum: Device state dump output partition */
6713 /* enum: Application license key storage partition */
6715 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
6717 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
6719 /* enum: Primary FPGA partition */
6721 /* enum: Secondary FPGA partition */
6723 /* enum: FC firmware partition */
6725 /* enum: FC License partition */
6727 /* enum: Non-volatile log output partition for FC */
6729 /* enum: MUM firmware partition */
6731 /* enum: SUC firmware partition (this is intentionally an alias of
6735 /* enum: MUM Non-volatile log output partition. */
6737 /* enum: MUM Application table partition. */
6739 /* enum: MUM boot rom partition. */
6741 /* enum: MUM production signatures & calibration rom partition. */
6743 /* enum: MUM user signatures & calibration rom partition. */
6745 /* enum: MUM fuses and lockbits partition. */
6747 /* enum: UEFI expansion ROM if separate from PXE */
6749 /* enum: Used by the expansion ROM for logging */
6751 /* enum: Used for XIP code of shmbooted images */
6753 /* enum: Spare partition 2 */
6755 /* enum: Manufacturing partition. Used during manufacture to pass information
6759 /* enum: Spare partition 4 */
6761 /* enum: Spare partition 5 */
6763 /* enum: Partition for reporting MC status. See mc_flash_layout.h
6767 /* enum: Spare partition 13 */
6769 /* enum: Spare partition 14 */
6771 /* enum: Spare partition 15 */
6773 /* enum: Spare partition 16 */
6775 /* enum: Factory defaults for dynamic configuration */
6777 /* enum: Factory defaults for expansion ROM configuration */
6779 /* enum: Field Replaceable Unit inventory information for use on IPMI
6784 /* enum: Bundle image partition */
6786 /* enum: Bundle metadata partition that holds additional information related to
6790 /* enum: Bundle update non-volatile log output partition */
6792 /* enum: Start of reserved value range (firmware may use for any purpose) */
6794 /* enum: End of reserved value range (firmware may use for any purpose) */
6796 /* enum: Recovery partition map (provided if real map is missing or corrupt) */
6798 /* enum: Partition map (real map as stored in flash) */
6807 /* enum: OpenOnload */
6809 /* enum: PTP timestamping */
6811 /* enum: SolarCapture Pro */
6813 /* enum: SolarSecure filter engine */
6815 /* enum: Performance monitor */
6817 /* enum: SolarCapture Live */
6819 /* enum: Capture SolarSystem */
6821 /* enum: Network Access Control */
6823 /* enum: TCP Direct */
6825 /* enum: Low Latency */
6827 /* enum: SolarCapture Tap */
6829 /* enum: Capture SolarSystem 40G */
6831 /* enum: Capture SolarSystem 1G */
6833 /* enum: ScaleOut Onload */
6835 /* enum: SCS Network Analytics Dashboard */
6837 /* enum: SolarCapture Trading Analytics */
6955 /* enum: This is a TX completion event, not a timestamp */
6957 /* enum: This is a TX completion event for a CTPIO transmit. The event format
6961 /* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
6965 /* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
6969 /* enum: This is the low part of a TX timestamp event */
6971 /* enum: This is the high part of a TX timestamp event */
7087 /* enum: Disabled */
7089 /* enum: Immediate */
7091 /* enum: Triggered */
7093 /* enum: Hold-off */
7107 /* enum: Disabled */
7109 /* enum: Disabled */
7111 /* enum: Disabled */
7113 /* enum: Disabled */
7170 /* enum: All initialisation flags specified by host. */
7172 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
7178 /* enum: MEDFORD only. Certain initialisation flags specified by host may be
7184 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
7191 /* enum: Disabled */
7193 /* enum: Immediate */
7195 /* enum: Triggered */
7197 /* enum: Hold-off */
7211 /* enum: Disabled */
7213 /* enum: Disabled */
7215 /* enum: Disabled */
7217 /* enum: Disabled */
7251 /* enum: No CRC. */
7253 /* enum: CRC Fiber channel over ethernet. */
7255 /* enum: CRC (digest) iSCSI header only. */
7257 /* enum: CRC (digest) iSCSI header and payload. */
7259 /* enum: CRC Fiber channel over IP over ethernet. */
7261 /* enum: CRC MPA. */
7373 /* enum: One packet per descriptor (for normal networking) */
7375 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7377 /* enum: Pack multiple packets into large descriptors using the format designed
7388 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
7389 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
7390 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
7391 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
7392 #define          MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
7453 /* enum: One packet per descriptor (for normal networking) */
7455 /* enum: Pack multiple packets into large descriptors (for SolarCapture) */
7457 /* enum: Pack multiple packets into large descriptors using the format designed
7468 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
7469 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
7470 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
7471 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
7472 #define          MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
7768 #define          MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
7780 /* enum: An invalid handle. */
7935 /* enum: The operation has been completed by using MC_CMD_PROXY_CMD, the reply
7939 /* enum: The operation has been authorized. The originating function may now
7943 /* enum: The operation has been declined. */
7945 /* enum: The authorization failed because the relevant application did not
8049 /* enum: single-recipient filter insert */
8051 /* enum: single-recipient filter remove */
8053 /* enum: multi-recipient filter subscribe */
8055 /* enum: multi-recipient filter unsubscribe */
8057 /* enum: replace one recipient with another (warning - the filter handle may
8104 /* enum: drop packets */
8106 /* enum: receive to host */
8108 /* enum: receive to MC */
8110 /* enum: loop back to TXDP 0 */
8112 /* enum: loop back to TXDP 1 */
8120 /* enum: receive to just the specified queue */
8122 /* enum: receive to multiple queues using RSS context */
8124 /* enum: receive to multiple queues using .1p mapping */
8126 /* enum: install a filter entry that will never match; for test purposes only
8144 /* enum: request default behaviour (based on filter type) */
8199 /*            Enum values, see field(s): */
8272 /* enum: drop packets */
8274 /* enum: receive to host */
8276 /* enum: receive to MC */
8278 /* enum: loop back to TXDP 0 */
8280 /* enum: loop back to TXDP 1 */
8288 /* enum: receive to just the specified queue */
8290 /* enum: receive to multiple queues using RSS context */
8292 /* enum: receive to multiple queues using .1p mapping */
8294 /* enum: install a filter entry that will never match; for test purposes only
8312 /* enum: request default behaviour (based on filter type) */
8355 /* enum: Match VXLAN traffic with this VNI */
8357 /* enum: Match Geneve traffic with this VNI */
8359 /* enum: Reserved for experimental development use */
8365 /* enum: Match NVGRE traffic with this VSID */
8443 /*            Enum values, see field(s): */
8516 /* enum: drop packets */
8518 /* enum: receive to host */
8520 /* enum: receive to MC */
8522 /* enum: loop back to TXDP 0 */
8524 /* enum: loop back to TXDP 1 */
8532 /* enum: receive to just the specified queue */
8534 /* enum: receive to multiple queues using RSS context */
8536 /* enum: receive to multiple queues using .1p mapping */
8538 /* enum: install a filter entry that will never match; for test purposes only
8556 /* enum: request default behaviour (based on filter type) */
8599 /* enum: Match VXLAN traffic with this VNI */
8601 /* enum: Match Geneve traffic with this VNI */
8603 /* enum: Reserved for experimental development use */
8609 /* enum: Match NVGRE traffic with this VSID */
8684 /* enum: do nothing extra */
8686 /* enum: Set the match flag in the packet prefix for packets matching the
8691 /* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
8705 /*            Enum values, see field(s): */
8715 /* enum: guaranteed invalid filter handle (low 32 bits) */
8717 /* enum: guaranteed invalid filter handle (high 32 bits) */
8725 /*            Enum values, see field(s): */
8735 /*            Enum values, see field(s): */
8752 /* enum: read the list of supported RX filter matches */
8754 /* enum: read flags indicating restrictions on filter insertion for the calling
8758 /* enum: read properties relating to security rules (Medford-only; for use by
8762 /* enum: read the list of supported RX filter matches for VXLAN/NVGRE
8775 /*            Enum values, see field(s): */
8793 /*            Enum values, see field(s): */
8820 /* enum: RX dispatcher CPU */
8822 /* enum: TX dispatcher CPU */
8824 /* enum: Lookup engine (with original metadata format). Deprecated; used only
8830 /* enum: Lookup engine (with requested metadata format) */
8832 /* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
8834 /* enum: RX1 dispatcher CPU (only valid for Medford) */
8836 /* enum: Miscellaneous other state (only valid for Medford) */
8841 /* enum: Read a word of DICPU DMEM or a LUE entry */
8843 /* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
8847 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
8857 /* enum: Port to datapath mapping */
8892 #define          MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
8893 #define          MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
9357 /* enum: MISC. */
9359 /* enum: IDO. */
9361 /* enum: RO. */
9363 /* enum: TPH Type. */
9370 /*            Enum values, see field(s): */
9423 /*            Enum values, see field(s): */
9495 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
9496 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
9497 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
9498 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
9499 #define          MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
9505 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9507 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9509 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9511 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9513 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9515 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9517 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9519 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9521 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9523 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9525 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9527 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
9529 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9531 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9533 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9535 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
9537 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
9542 /* enum: Last chunk, containing checksum rather than data */
9544 /* enum: Abort download of this item */
9563 /* enum: Code download OK, completed. */
9565 /* enum: Code download aborted as requested. */
9567 /* enum: Code download OK so far, send next chunk. */
9569 /* enum: Download phases out of sequence */
9571 /* enum: Bad target for this phase */
9573 /* enum: Chunk ID out of sequence */
9575 /* enum: Chunk length zero or too large */
9577 /* enum: Checksum was incorrect */
9661 /* enum: Standard RXDP firmware */
9663 /* enum: Low latency RXDP firmware */
9665 /* enum: Packed stream RXDP firmware */
9667 /* enum: Rules engine RXDP firmware */
9669 /* enum: DPDK RXDP firmware */
9671 /* enum: BIST RXDP firmware */
9673 /* enum: RXDP Test firmware image 1 */
9675 /* enum: RXDP Test firmware image 2 */
9677 /* enum: RXDP Test firmware image 3 */
9679 /* enum: RXDP Test firmware image 4 */
9681 /* enum: RXDP Test firmware image 5 */
9683 /* enum: RXDP Test firmware image 6 */
9685 /* enum: RXDP Test firmware image 7 */
9687 /* enum: RXDP Test firmware image 8 */
9689 /* enum: RXDP Test firmware image 9 */
9691 /* enum: RXDP Test firmware image 10 */
9696 /* enum: Standard TXDP firmware */
9698 /* enum: Low latency TXDP firmware */
9700 /* enum: High packet rate TXDP firmware */
9702 /* enum: Rules engine TXDP firmware */
9704 /* enum: DPDK TXDP firmware */
9706 /* enum: BIST TXDP firmware */
9708 /* enum: TXDP Test firmware image 1 */
9710 /* enum: TXDP Test firmware image 2 */
9712 /* enum: TXDP CSR bus test firmware */
9720 /* enum: reserved value - do not use (may indicate alternative interpretation
9724 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9728 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9732 /* enum: Full featured RX PD production firmware */
9734 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9736 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9740 /* enum: Low latency RX PD production firmware */
9742 /* enum: Packed stream RX PD production firmware */
9744 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9748 /* enum: Rules engine RX PD production firmware */
9750 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9752 /* enum: DPDK RX PD production firmware */
9754 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9756 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9766 /* enum: reserved value - do not use (may indicate alternative interpretation
9770 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9774 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9778 /* enum: Full featured TX PD production firmware */
9780 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9782 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
9786 #define          MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
9787 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
9791 /* enum: Rules engine TX PD production firmware */
9793 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9795 /* enum: DPDK TX PD production firmware */
9797 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9875 /* enum: Standard RXDP firmware */
9877 /* enum: Low latency RXDP firmware */
9879 /* enum: Packed stream RXDP firmware */
9881 /* enum: Rules engine RXDP firmware */
9883 /* enum: DPDK RXDP firmware */
9885 /* enum: BIST RXDP firmware */
9887 /* enum: RXDP Test firmware image 1 */
9889 /* enum: RXDP Test firmware image 2 */
9891 /* enum: RXDP Test firmware image 3 */
9893 /* enum: RXDP Test firmware image 4 */
9895 /* enum: RXDP Test firmware image 5 */
9897 /* enum: RXDP Test firmware image 6 */
9899 /* enum: RXDP Test firmware image 7 */
9901 /* enum: RXDP Test firmware image 8 */
9903 /* enum: RXDP Test firmware image 9 */
9905 /* enum: RXDP Test firmware image 10 */
9910 /* enum: Standard TXDP firmware */
9912 /* enum: Low latency TXDP firmware */
9914 /* enum: High packet rate TXDP firmware */
9916 /* enum: Rules engine TXDP firmware */
9918 /* enum: DPDK TXDP firmware */
9920 /* enum: BIST TXDP firmware */
9922 /* enum: TXDP Test firmware image 1 */
9924 /* enum: TXDP Test firmware image 2 */
9926 /* enum: TXDP CSR bus test firmware */
9934 /* enum: reserved value - do not use (may indicate alternative interpretation
9938 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
9942 /* enum: RX PD firmware with approximately Siena-compatible behaviour
9946 /* enum: Full featured RX PD production firmware */
9948 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9950 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
9954 /* enum: Low latency RX PD production firmware */
9956 /* enum: Packed stream RX PD production firmware */
9958 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
9962 /* enum: Rules engine RX PD production firmware */
9964 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
9966 /* enum: DPDK RX PD production firmware */
9968 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
9970 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
9980 /* enum: reserved value - do not use (may indicate alternative interpretation
9984 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
9988 /* enum: TX PD firmware with approximately Siena-compatible behaviour
9992 /* enum: Full featured TX PD production firmware */
9994 /* enum: (deprecated original name for the FULL_FEATURED variant) */
9996 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10000 #define          MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10001 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10005 /* enum: Rules engine TX PD production firmware */
10007 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10009 /* enum: DPDK TX PD production firmware */
10011 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10084 /* enum: The caller is not permitted to access information on this PF. */
10086 /* enum: PF does not exist. */
10088 /* enum: PF does exist but is not assigned to any external port. */
10090 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10103 /* enum: The caller is not permitted to access information on this PF. */
10105 /* enum: PF does not exist. */
10194 /* enum: Standard RXDP firmware */
10196 /* enum: Low latency RXDP firmware */
10198 /* enum: Packed stream RXDP firmware */
10200 /* enum: Rules engine RXDP firmware */
10202 /* enum: DPDK RXDP firmware */
10204 /* enum: BIST RXDP firmware */
10206 /* enum: RXDP Test firmware image 1 */
10208 /* enum: RXDP Test firmware image 2 */
10210 /* enum: RXDP Test firmware image 3 */
10212 /* enum: RXDP Test firmware image 4 */
10214 /* enum: RXDP Test firmware image 5 */
10216 /* enum: RXDP Test firmware image 6 */
10218 /* enum: RXDP Test firmware image 7 */
10220 /* enum: RXDP Test firmware image 8 */
10222 /* enum: RXDP Test firmware image 9 */
10224 /* enum: RXDP Test firmware image 10 */
10229 /* enum: Standard TXDP firmware */
10231 /* enum: Low latency TXDP firmware */
10233 /* enum: High packet rate TXDP firmware */
10235 /* enum: Rules engine TXDP firmware */
10237 /* enum: DPDK TXDP firmware */
10239 /* enum: BIST TXDP firmware */
10241 /* enum: TXDP Test firmware image 1 */
10243 /* enum: TXDP Test firmware image 2 */
10245 /* enum: TXDP CSR bus test firmware */
10253 /* enum: reserved value - do not use (may indicate alternative interpretation
10257 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10261 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10265 /* enum: Full featured RX PD production firmware */
10267 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10269 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10273 /* enum: Low latency RX PD production firmware */
10275 /* enum: Packed stream RX PD production firmware */
10277 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10281 /* enum: Rules engine RX PD production firmware */
10283 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10285 /* enum: DPDK RX PD production firmware */
10287 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10289 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10299 /* enum: reserved value - do not use (may indicate alternative interpretation
10303 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10307 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10311 /* enum: Full featured TX PD production firmware */
10313 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10315 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10319 #define          MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10320 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10324 /* enum: Rules engine TX PD production firmware */
10326 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10328 /* enum: DPDK TX PD production firmware */
10330 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10403 /* enum: The caller is not permitted to access information on this PF. */
10405 /* enum: PF does not exist. */
10407 /* enum: PF does exist but is not assigned to any external port. */
10409 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10422 /* enum: The caller is not permitted to access information on this PF. */
10424 /* enum: PF does not exist. */
10453 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10457 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10459 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10538 /* enum: Standard RXDP firmware */
10540 /* enum: Low latency RXDP firmware */
10542 /* enum: Packed stream RXDP firmware */
10544 /* enum: Rules engine RXDP firmware */
10546 /* enum: DPDK RXDP firmware */
10548 /* enum: BIST RXDP firmware */
10550 /* enum: RXDP Test firmware image 1 */
10552 /* enum: RXDP Test firmware image 2 */
10554 /* enum: RXDP Test firmware image 3 */
10556 /* enum: RXDP Test firmware image 4 */
10558 /* enum: RXDP Test firmware image 5 */
10560 /* enum: RXDP Test firmware image 6 */
10562 /* enum: RXDP Test firmware image 7 */
10564 /* enum: RXDP Test firmware image 8 */
10566 /* enum: RXDP Test firmware image 9 */
10568 /* enum: RXDP Test firmware image 10 */
10573 /* enum: Standard TXDP firmware */
10575 /* enum: Low latency TXDP firmware */
10577 /* enum: High packet rate TXDP firmware */
10579 /* enum: Rules engine TXDP firmware */
10581 /* enum: DPDK TXDP firmware */
10583 /* enum: BIST TXDP firmware */
10585 /* enum: TXDP Test firmware image 1 */
10587 /* enum: TXDP Test firmware image 2 */
10589 /* enum: TXDP CSR bus test firmware */
10597 /* enum: reserved value - do not use (may indicate alternative interpretation
10601 /* enum: Trivial RX PD firmware for early Huntington development (Huntington
10605 /* enum: RX PD firmware with approximately Siena-compatible behaviour
10609 /* enum: Full featured RX PD production firmware */
10611 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10613 /* enum: siena_compat variant RX PD firmware using PM rather than MAC
10617 /* enum: Low latency RX PD production firmware */
10619 /* enum: Packed stream RX PD production firmware */
10621 /* enum: RX PD firmware handling layer 2 only for high packet rate performance
10625 /* enum: Rules engine RX PD production firmware */
10627 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10629 /* enum: DPDK RX PD production firmware */
10631 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10633 /* enum: RX PD firmware parsing but not filtering network overlay tunnel
10643 /* enum: reserved value - do not use (may indicate alternative interpretation
10647 /* enum: Trivial TX PD firmware for early Huntington development (Huntington
10651 /* enum: TX PD firmware with approximately Siena-compatible behaviour
10655 /* enum: Full featured TX PD production firmware */
10657 /* enum: (deprecated original name for the FULL_FEATURED variant) */
10659 /* enum: siena_compat variant TX PD firmware using PM rather than MAC
10663 #define          MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
10664 /* enum: TX PD firmware handling layer 2 only for high packet rate performance
10668 /* enum: Rules engine TX PD production firmware */
10670 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
10672 /* enum: DPDK TX PD production firmware */
10674 /* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
10747 /* enum: The caller is not permitted to access information on this PF. */
10749 /* enum: PF does not exist. */
10751 /* enum: PF does exist but is not assigned to any external port. */
10753 /* enum: This value indicates that PF is assigned, but it cannot be expressed
10766 /* enum: The caller is not permitted to access information on this PF. */
10768 /* enum: PF does not exist. */
10797 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
10801 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
10803 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
10848 /* enum: MCDI command directed to or response originating from the MC. */
10850 /* enum: MCDI command directed to a TSA controller. MCDI responses of this type
11063 /* enum: VLAN */
11065 /* enum: VEB */
11067 /* enum: VEPA (obsolete) */
11069 /* enum: MUX */
11071 /* enum: Snapper specific; semantics TBD */
11146 /* enum: VLAN (obsolete) */
11148 /* enum: VEB (obsolete) */
11150 /* enum: VEPA (obsolete) */
11152 /* enum: A normal v-port receives packets which match a specified MAC and/or
11156 /* enum: An expansion v-port packets traffic which don't match any other
11160 /* enum: An test v-port receives packets which match any filters installed by
11246 /* enum: Derive the MAC address from the upstream port */
11458 /* enum: Allocate a context for exclusive use. The key and indirection table
11462 /* enum: Allocate a context for shared use; this will spread across a range of
11481 /* enum: guaranteed invalid RSS context handle value */
11724 /* enum: guaranteed invalid .1p mapping handle value */
12036 /* enum: pad to 64 bytes */
12038 /* enum: pad to 128 bytes (Medford only) */
12040 /* enum: pad to 256 bytes (Medford only) */
12066 /*             Enum values, see field(s): */
12104 /* enum: Leave the system clock domain frequency unchanged */
12109 /* enum: Leave the inter-core clock domain frequency unchanged */
12114 /* enum: Leave the DPCPU clock domain frequency unchanged */
12119 /* enum: Leave the PCS clock domain frequency unchanged */
12124 /* enum: Leave the MC clock domain frequency unchanged */
12129 /* enum: Leave the rmon clock domain frequency unchanged */
12134 /* enum: Leave the vswitch clock domain frequency unchanged */
12142 /* enum: The system clock domain doesn't exist */
12147 /* enum: The inter-core clock domain doesn't exist / isn't used */
12152 /* enum: The dpcpu clock domain doesn't exist */
12157 /* enum: The PCS clock domain doesn't exist / isn't controlled */
12162 /* enum: The MC clock domain doesn't exist / isn't controlled */
12167 /* enum: The rmon clock domain doesn't exist / isn't controlled */
12172 /* enum: The vswitch clock domain doesn't exist / isn't controlled */
12188 /* enum: RxDPCPU0 */
12190 /* enum: TxDPCPU0 */
12192 /* enum: TxDPCPU1 */
12194 /* enum: RxDPCPU1 (Medford only) */
12196 /* enum: RxDPCPU (will be for the calling function; for now, just an alias of
12200 /* enum: TxDPCPU (will be for the calling function; for now, just an alias of
12211 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
12212 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
12213 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
12214 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
12215 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
12216 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
12217 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
12218 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
12219 #define          MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
12230 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
12231 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
12232 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
12233 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
12234 #define          MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
12243 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
12244 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
12245 #define          MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
12311 /* enum: Copy slave_data section to the slave core. (Greenport only) */
12361 #define          MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
12362 #define          MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
12365 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
12366 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
12367 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
12368 #define          MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
12379 #define          MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
12384 #define          MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
12387 /* enum: The uart port this command was received over (if using a uart
12395 #define          MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
12396 #define          MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
12399 /*            Enum values, see field(s): */
12440 /*            Enum values, see field(s): */
12444 /*            Enum values, see field(s): */
12466 /*            Enum values, see field(s): */
12470 /*            Enum values, see field(s): */
12506 #define          MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
12509 #define          MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
12510 #define          MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
12682 /* enum: Get current RXEQ settings */
12684 /* enum: Override RXEQ settings */
12686 /* enum: Get current TX Driver settings */
12688 /* enum: Override TX Driver settings */
12690 /* enum: Force KR Serdes reset / recalibration */
12692 /* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
12696 /* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
12701 /* enum: Read Figure Of Merit (eye quality, higher is better). */
12703 /* enum: Start/stop link training frames */
12705 /* enum: Issue KR link training command (control training coefficients) */
12739 /* enum: Attenuation (0-15, Huntington) */
12741 /* enum: CTLE Boost (0-15, Huntington) */
12743 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
12747 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
12751 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
12755 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
12759 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
12763 /* enum: Edge DFE DLEV (0-128 for Medford) */
12765 /* enum: Variable Gain Amplifier (0-15, Medford) */
12767 /* enum: CTLE EQ Capacitor (0-15, Medford) */
12769 /* enum: CTLE EQ Resistor (0-7, Medford) */
12771 /* enum: CTLE gain (0-31, Medford2) */
12773 /* enum: CTLE pole (0-31, Medford2) */
12775 /* enum: CTLE peaking (0-31, Medford2) */
12777 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
12779 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
12781 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
12783 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
12785 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
12787 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
12789 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
12791 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
12793 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
12795 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
12797 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
12799 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
12801 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
12803 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
12805 /* enum: Negative h1 polarity data sampler offset calibration code, even path
12809 /* enum: Negative h1 polarity data sampler offset calibration code, odd path
12813 /* enum: Positive h1 polarity data sampler offset calibration code, even path
12817 /* enum: Positive h1 polarity data sampler offset calibration code, odd path
12821 /* enum: CDR calibration loop code (Medford2) */
12823 /* enum: CDR integral loop code (Medford2) */
12827 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
12828 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
12829 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
12830 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
12831 #define          MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12858 /*             Enum values, see field(s): */
12862 /*             Enum values, see field(s): */
12896 /* enum: TX Amplitude (Huntington, Medford, Medford2) */
12898 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
12900 /* enum: De-Emphasis Tap1 Fine */
12902 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
12904 /* enum: De-Emphasis Tap2 Fine (Huntington) */
12906 /* enum: Pre-Emphasis Magnitude (Huntington) */
12908 /* enum: Pre-Emphasis Fine (Huntington) */
12910 /* enum: TX Slew Rate Coarse control (Huntington) */
12912 /* enum: TX Slew Rate Fine control (Huntington) */
12914 /* enum: TX Termination Impedance control (Huntington) */
12916 /* enum: TX Amplitude Fine control (Medford) */
12918 /* enum: Pre-shoot Tap (Medford, Medford2) */
12920 /* enum: De-emphasis Tap (Medford, Medford2) */
12924 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
12925 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
12926 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
12927 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
12928 #define          MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
12953 /*             Enum values, see field(s): */
12957 /*             Enum values, see field(s): */
13062 #define          MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
13063 #define          MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
13084 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
13085 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
13086 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
13090 /*            Enum values, see field(s): */
13095 /*            Enum values, see field(s): */
13103 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
13104 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
13105 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
13106 #define          MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
13110 /*            Enum values, see field(s): */
13115 /*            Enum values, see field(s): */
13143 /* enum: Get current RXEQ settings */
13145 /* enum: Override RXEQ settings */
13147 /* enum: Get current TX Driver settings */
13149 /* enum: Override TX Driver settings */
13151 /* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
13153 /* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
13158 /* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */
13192 /* enum: Attenuation (0-15) */
13194 /* enum: CTLE Boost (0-15) */
13196 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
13198 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
13200 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
13202 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
13204 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
13206 /* enum: DFE DLev */
13208 /* enum: Figure of Merit */
13210 /* enum: CTLE EQ Capacitor (HF Gain) */
13212 /* enum: CTLE EQ Resistor (DC Gain) */
13216 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
13217 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
13218 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
13219 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
13220 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
13221 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
13222 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
13223 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
13224 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
13225 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
13226 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
13227 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
13228 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
13229 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
13230 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
13231 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
13232 #define          MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
13257 /*             Enum values, see field(s): */
13261 /*             Enum values, see field(s): */
13295 /* enum: TxMargin (PIPE) */
13297 /* enum: TxSwing (PIPE) */
13299 /* enum: De-emphasis coefficient C(-1) (PIPE) */
13301 /* enum: De-emphasis coefficient C(0) (PIPE) */
13303 /* enum: De-emphasis coefficient C(+1) (PIPE) */
13307 /*             Enum values, see field(s): */
13367 /* enum: re-read and apply licenses after a license key partition update; note
13371 /* enum: report counts of installed licenses */
13402 /* enum: licensing subsystem self-test failed */
13404 /* enum: licensing subsystem self-test passed */
13422 /* enum: re-read and apply licenses after a license key partition update; note
13426 /* enum: report counts of installed licenses Returns EAGAIN if license
13455 /* enum: licensing subsystem self-test failed */
13457 /* enum: licensing subsystem self-test passed */
13543 /* enum: no (or invalid) license is present for the application */
13545 /* enum: a valid license is present for the application */
13574 /* enum: no (or invalid) license is present for the application */
13576 /* enum: a valid license is present for the application */
13628 /* enum: validate application */
13630 /* enum: mask application */
13721 /* enum: expiry units are accounting units */
13723 /* enum: expiry units are calendar days */
13756 /* enum: turn the features off */
13758 /* enum: turn the features back on */
13782 /* enum: install a new license, overwriting any existing temporary license.
13787 /* enum: clear the license immediately rather than waiting for the next power
13791 /* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
13819 /* enum: finished validating and installing license */
13821 /* enum: license validation and installation in progress */
13823 /* enum: licensing error. More specific error messages are not provided to
13861 /* enum: receive to just the specified queue */
13863 /* enum: receive to multiple queues using RSS context */
13904 /* enum: receiving to just the specified queue */
13906 /* enum: receiving to multiple queues using RSS context */
13928 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
13932 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
13967 /*            Enum values, see field(s): */
14015 /* enum: receive to just the specified queue */
14017 /* enum: receive to multiple queues using RSS context */
14056 /* enum: receiving to just the specified queue */
14058 /* enum: receiving to multiple queues using RSS context */
14169 #define          MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
14170 #define          MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
14171 #define          MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
14202 /* enum: Bug 17230 work around. */
14204 /* enum: Bug 35388 work around (unsafe EVQ writes). */
14206 /* enum: Bug35017 workaround (A64 tables must be identity map) */
14208 /* enum: Bug 41750 present (MC_CMD_TRIGGER_INTERRUPT won't work) */
14210 /* enum: Bug 42008 present (Interrupts can overtake associated events). Caution
14216 /* enum: Bug 26807 features present in firmware (multicast filter chaining) */
14218 /* enum: Bug 61265 work around (broken EVQ TMR writes). */
14241 #define          MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
14247 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
14248 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
14249 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
14250 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
14251 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
14252 /* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
14254 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
14255 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
14256 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
14257 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
14258 #define          MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
14259 /* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
14263 /* enum: Privilege that allows a Function to change the MAC address configured
14267 /* enum: Privilege that allows a Function to install filters that specify VLANs
14273 /* enum: Privilege for insecure commands. Commands that belong to this group
14277 /* enum: Set this bit to indicate that a new privilege mask is to be set,
14311 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
14312 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
14313 #define          MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
14314 /* enum: Use this value to just read the existing setting without modifying it.
14412 #define          MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
14413 #define          MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
14414 #define          MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
14415 #define          MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
14416 #define          MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
14417 #define          MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
14520 #define          MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
14521 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
14522 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
14523 #define          MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
14524 #define          MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
14556 /*            Enum values, see field(s): */
14738 /* enum: the IANA allocated UDP port for VXLAN */
14740 /* enum: the IANA allocated UDP port for Geneve */
14747 /* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
14749 /* enum: This port will be used for Geneve on both IPv4 and IPv6 */
14918 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
14919 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
14920 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
14921 #define          MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
15019 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
15020 /* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
15028 /* enum: Extracts information from function */
15033 /* enum: Extracts information from function */
15035 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
15036 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
15037 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
15038 #define          MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
15039 /* enum: To enable Switch loopback with Rx engine 0 */
15041 /* enum: To enable Switch loopback with Rx engine 1 */
15069 /* enum: Extracts information from common pool */
15071 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
15072 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
15073 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
15074 #define          MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
15075 /* enum: To enable Switch loopback with Rx engine 0 */
15077 /* enum: To enable Switch loopback with Rx engine 1 */
15082 /* enum: Do not check the space available */
15090 /* enum: Search for the lowest unused priority */