3273 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3308 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_force_linkspeed()
3310 			txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_force_linkspeed()
3312 		txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_force_linkspeed()
3314 	writel(txreg, base + NvRegTxDeferral);  in nv_force_linkspeed()
3317 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_force_linkspeed()
3321 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_force_linkspeed()
3323 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_force_linkspeed()
3325 	writel(txreg, base + NvRegTxWatermark);  in nv_force_linkspeed()
3357 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3489 			txreg = NVREG_TX_DEFERRAL_RGMII_1000;  in nv_update_linkspeed()
3493 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;  in nv_update_linkspeed()
3495 					txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;  in nv_update_linkspeed()
3497 				txreg = NVREG_TX_DEFERRAL_RGMII_10_100;  in nv_update_linkspeed()
3502 			txreg = NVREG_TX_DEFERRAL_MII_STRETCH;  in nv_update_linkspeed()
3504 			txreg = NVREG_TX_DEFERRAL_DEFAULT;  in nv_update_linkspeed()
3506 	writel(txreg, base + NvRegTxDeferral);  in nv_update_linkspeed()
3509 		txreg = NVREG_TX_WM_DESC1_DEFAULT;  in nv_update_linkspeed()
3512 			txreg = NVREG_TX_WM_DESC2_3_1000;  in nv_update_linkspeed()
3514 			txreg = NVREG_TX_WM_DESC2_3_DEFAULT;  in nv_update_linkspeed()
3516 	writel(txreg, base + NvRegTxWatermark);  in nv_update_linkspeed()
5676 	u32 powerstate, txreg;  in nv_probe()  local
5854 	txreg = readl(base + NvRegTransmitPoll);  in nv_probe()
5863 	} else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {  in nv_probe()
5887 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);  in nv_probe()