3273 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3283 		phyreg = readl(base + NvRegSlotTime);  in nv_force_linkspeed()
3284 		phyreg &= ~(0x3FF00);  in nv_force_linkspeed()
3286 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3288 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3290 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_force_linkspeed()
3291 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3294 	phyreg = readl(base + NvRegPhyInterface);  in nv_force_linkspeed()
3295 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_force_linkspeed()
3297 		phyreg |= PHY_HALF;  in nv_force_linkspeed()
3299 		phyreg |= PHY_100;  in nv_force_linkspeed()
3302 		phyreg |= PHY_1000;  in nv_force_linkspeed()
3303 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3305 	if (phyreg & PHY_RGMII) {  in nv_force_linkspeed()
3357 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3466 		phyreg = readl(base + NvRegSlotTime);  in nv_update_linkspeed()
3467 		phyreg &= ~(0x3FF00);  in nv_update_linkspeed()
3470 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_update_linkspeed()
3472 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_update_linkspeed()
3473 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3476 	phyreg = readl(base + NvRegPhyInterface);  in nv_update_linkspeed()
3477 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_update_linkspeed()
3479 		phyreg |= PHY_HALF;  in nv_update_linkspeed()
3481 		phyreg |= PHY_100;  in nv_update_linkspeed()
3483 		phyreg |= PHY_1000;  in nv_update_linkspeed()
3484 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3487 	if (phyreg & PHY_RGMII) {  in nv_update_linkspeed()