Lines Matching refs:phyaddr
768 int phyaddr; member
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1246 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1255 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1267 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1270 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1283 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1286 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1290 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1293 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1329 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1332 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1335 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1339 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1345 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1348 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1351 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1357 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1361 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1364 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1367 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1371 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1377 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1380 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1446 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
3280 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3364 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3377 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3378 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3413 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3414 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3418 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3419 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3486 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4344 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4354 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4366 cmd->base.phy_address = np->phyaddr; in nv_get_link_ksettings()
4390 if (cmd->base.phy_address != np->phyaddr) { in nv_set_link_ksettings()
4449 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4463 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4466 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4470 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4475 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4486 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4493 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4512 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4516 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4518 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4521 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4534 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4595 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4605 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4801 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4807 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4811 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4813 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4842 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4852 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
4996 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
4997 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5426 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5427 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5512 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5625 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5626 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
6011 int phyaddr = i & 0x1F; in nv_probe() local
6014 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
6019 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
6027 np->phyaddr = phyaddr; in nv_probe()
6035 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6049 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6079 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6128 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6129 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6132 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6133 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6136 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6138 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()