Lines Matching refs:np
727 __this_cpu_inc(np->txrx_stats->member)
729 __this_cpu_add(np->txrx_stats->member, (count))
961 static bool nv_optimized(struct fe_priv *np) in nv_optimized() argument
963 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) in nv_optimized()
998 struct fe_priv *np = get_nvpriv(dev); in setup_hw_rings() local
1001 if (!nv_optimized(np)) { in setup_hw_rings()
1003 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings()
1005 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysA… in setup_hw_rings()
1008 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings()
1009 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); in setup_hw_rings()
1012 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPh… in setup_hw_rings()
1013 …writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingP… in setup_hw_rings()
1020 struct fe_priv *np = get_nvpriv(dev); in free_rings() local
1022 if (!nv_optimized(np)) { in free_rings()
1023 if (np->rx_ring.orig) in free_rings()
1024 dma_free_coherent(&np->pci_dev->dev, in free_rings()
1026 (np->rx_ring_size + in free_rings()
1027 np->tx_ring_size), in free_rings()
1028 np->rx_ring.orig, np->ring_addr); in free_rings()
1030 if (np->rx_ring.ex) in free_rings()
1031 dma_free_coherent(&np->pci_dev->dev, in free_rings()
1033 (np->rx_ring_size + in free_rings()
1034 np->tx_ring_size), in free_rings()
1035 np->rx_ring.ex, np->ring_addr); in free_rings()
1037 kfree(np->rx_skb); in free_rings()
1038 kfree(np->tx_skb); in free_rings()
1043 struct fe_priv *np = get_nvpriv(dev); in using_multi_irqs() local
1045 if (!(np->msi_flags & NV_MSI_X_ENABLED) || in using_multi_irqs()
1046 ((np->msi_flags & NV_MSI_X_ENABLED) && in using_multi_irqs()
1047 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) in using_multi_irqs()
1055 struct fe_priv *np = get_nvpriv(dev); in nv_txrx_gate() local
1059 if (!np->mac_in_use && in nv_txrx_gate()
1060 (np->driver_data & DEV_HAS_POWER_CNTRL)) { in nv_txrx_gate()
1072 struct fe_priv *np = get_nvpriv(dev); in nv_enable_irq() local
1075 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_enable_irq()
1076 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); in nv_enable_irq()
1078 enable_irq(np->pci_dev->irq); in nv_enable_irq()
1080 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); in nv_enable_irq()
1081 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); in nv_enable_irq()
1082 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); in nv_enable_irq()
1088 struct fe_priv *np = get_nvpriv(dev); in nv_disable_irq() local
1091 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_disable_irq()
1092 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); in nv_disable_irq()
1094 disable_irq(np->pci_dev->irq); in nv_disable_irq()
1096 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); in nv_disable_irq()
1097 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); in nv_disable_irq()
1098 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); in nv_disable_irq()
1112 struct fe_priv *np = get_nvpriv(dev); in nv_disable_hw_interrupts() local
1115 if (np->msi_flags & NV_MSI_X_ENABLED) { in nv_disable_hw_interrupts()
1118 if (np->msi_flags & NV_MSI_ENABLED) in nv_disable_hw_interrupts()
1126 struct fe_priv *np = get_nvpriv(dev); in nv_napi_enable() local
1128 napi_enable(&np->napi); in nv_napi_enable()
1133 struct fe_priv *np = get_nvpriv(dev); in nv_napi_disable() local
1135 napi_disable(&np->napi); in nv_napi_disable()
1181 struct fe_priv *np = netdev_priv(dev); in phy_reset() local
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1203 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np) in init_realtek_8211b() argument
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1227 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np) in init_realtek_8211c() argument
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1246 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1255 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1262 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np) in init_realtek_8201() argument
1266 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { in init_realtek_8201()
1267 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1270 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1278 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np) in init_realtek_8201_cross() argument
1283 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1286 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1290 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1293 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1301 static int init_cicada(struct net_device *dev, struct fe_priv *np, in init_cicada() argument
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1325 static int init_vitesse(struct net_device *dev, struct fe_priv *np) in init_vitesse() argument
1329 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1332 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1335 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1339 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1345 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1348 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1351 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1357 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1361 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1364 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1367 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1371 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1377 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1380 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1389 struct fe_priv *np = get_nvpriv(dev); in phy_init() local
1395 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { in phy_init()
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1400 pci_name(np->pci_dev)); in phy_init()
1404 if (np->phy_oui == PHY_OUI_REALTEK) { in phy_init()
1405 if (np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1406 np->phy_rev == PHY_REV_REALTEK_8211B) { in phy_init()
1407 if (init_realtek_8211b(dev, np)) { in phy_init()
1409 pci_name(np->pci_dev)); in phy_init()
1412 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1413 np->phy_rev == PHY_REV_REALTEK_8211C) { in phy_init()
1414 if (init_realtek_8211c(dev, np)) { in phy_init()
1416 pci_name(np->pci_dev)); in phy_init()
1419 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { in phy_init()
1420 if (init_realtek_8201(dev, np)) { in phy_init()
1422 pci_name(np->pci_dev)); in phy_init()
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1435 pci_name(np->pci_dev)); in phy_init()
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1445 np->gigabit = PHY_GIGABIT; in phy_init()
1446 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1456 pci_name(np->pci_dev)); in phy_init()
1460 np->gigabit = 0; in phy_init()
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1465 if (np->phy_oui == PHY_OUI_REALTEK && in phy_init()
1466 np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1467 np->phy_rev == PHY_REV_REALTEK_8211C) { in phy_init()
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1472 pci_name(np->pci_dev)); in phy_init()
1481 pci_name(np->pci_dev)); in phy_init()
1487 if (np->phy_oui == PHY_OUI_CICADA) { in phy_init()
1488 if (init_cicada(dev, np, phyinterface)) { in phy_init()
1490 pci_name(np->pci_dev)); in phy_init()
1493 } else if (np->phy_oui == PHY_OUI_VITESSE) { in phy_init()
1494 if (init_vitesse(dev, np)) { in phy_init()
1496 pci_name(np->pci_dev)); in phy_init()
1499 } else if (np->phy_oui == PHY_OUI_REALTEK) { in phy_init()
1500 if (np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1501 np->phy_rev == PHY_REV_REALTEK_8211B) { in phy_init()
1503 if (init_realtek_8211b(dev, np)) { in phy_init()
1505 pci_name(np->pci_dev)); in phy_init()
1508 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { in phy_init()
1509 if (init_realtek_8201(dev, np) || in phy_init()
1510 init_realtek_8201_cross(dev, np)) { in phy_init()
1512 pci_name(np->pci_dev)); in phy_init()
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
1534 struct fe_priv *np = netdev_priv(dev); in nv_start_rx() local
1539 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { in nv_start_rx()
1544 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_start_rx()
1547 if (np->mac_in_use) in nv_start_rx()
1555 struct fe_priv *np = netdev_priv(dev); in nv_stop_rx() local
1559 if (!np->mac_in_use) in nv_stop_rx()
1570 if (!np->mac_in_use) in nv_stop_rx()
1576 struct fe_priv *np = netdev_priv(dev); in nv_start_tx() local
1581 if (np->mac_in_use) in nv_start_tx()
1589 struct fe_priv *np = netdev_priv(dev); in nv_stop_tx() local
1593 if (!np->mac_in_use) in nv_stop_tx()
1604 if (!np->mac_in_use) in nv_stop_tx()
1623 struct fe_priv *np = netdev_priv(dev); in nv_txrx_reset() local
1626 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); in nv_txrx_reset()
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); in nv_txrx_reset()
1635 struct fe_priv *np = netdev_priv(dev); in nv_mac_reset() local
1639 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); in nv_mac_reset()
1659 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); in nv_mac_reset()
1666 struct fe_priv *np = netdev_priv(dev); in nv_update_stats() local
1673 assert_spin_locked(&np->hwstats_lock); in nv_update_stats()
1676 np->estats.tx_bytes += readl(base + NvRegTxCnt); in nv_update_stats()
1677 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); in nv_update_stats()
1678 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); in nv_update_stats()
1679 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); in nv_update_stats()
1680 np->estats.tx_late_collision += readl(base + NvRegTxLateCol); in nv_update_stats()
1681 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); in nv_update_stats()
1682 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); in nv_update_stats()
1683 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); in nv_update_stats()
1684 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); in nv_update_stats()
1685 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); in nv_update_stats()
1686 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); in nv_update_stats()
1687 np->estats.rx_late_collision += readl(base + NvRegRxLateCol); in nv_update_stats()
1688 np->estats.rx_runt += readl(base + NvRegRxRunt); in nv_update_stats()
1689 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); in nv_update_stats()
1690 np->estats.rx_over_errors += readl(base + NvRegRxOverflow); in nv_update_stats()
1691 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); in nv_update_stats()
1692 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); in nv_update_stats()
1693 np->estats.rx_length_error += readl(base + NvRegRxLenErr); in nv_update_stats()
1694 np->estats.rx_unicast += readl(base + NvRegRxUnicast); in nv_update_stats()
1695 np->estats.rx_multicast += readl(base + NvRegRxMulticast); in nv_update_stats()
1696 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); in nv_update_stats()
1697 np->estats.rx_packets = in nv_update_stats()
1698 np->estats.rx_unicast + in nv_update_stats()
1699 np->estats.rx_multicast + in nv_update_stats()
1700 np->estats.rx_broadcast; in nv_update_stats()
1701 np->estats.rx_errors_total = in nv_update_stats()
1702 np->estats.rx_crc_errors + in nv_update_stats()
1703 np->estats.rx_over_errors + in nv_update_stats()
1704 np->estats.rx_frame_error + in nv_update_stats()
1705 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + in nv_update_stats()
1706 np->estats.rx_late_collision + in nv_update_stats()
1707 np->estats.rx_runt + in nv_update_stats()
1708 np->estats.rx_frame_too_long; in nv_update_stats()
1709 np->estats.tx_errors_total = in nv_update_stats()
1710 np->estats.tx_late_collision + in nv_update_stats()
1711 np->estats.tx_fifo_errors + in nv_update_stats()
1712 np->estats.tx_carrier_errors + in nv_update_stats()
1713 np->estats.tx_excess_deferral + in nv_update_stats()
1714 np->estats.tx_retry_error; in nv_update_stats()
1716 if (np->driver_data & DEV_HAS_STATISTICS_V2) { in nv_update_stats()
1717 np->estats.tx_deferral += readl(base + NvRegTxDef); in nv_update_stats()
1718 np->estats.tx_packets += readl(base + NvRegTxFrame); in nv_update_stats()
1719 np->estats.rx_bytes += readl(base + NvRegRxCnt); in nv_update_stats()
1720 np->estats.tx_pause += readl(base + NvRegTxPause); in nv_update_stats()
1721 np->estats.rx_pause += readl(base + NvRegRxPause); in nv_update_stats()
1722 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); in nv_update_stats()
1723 np->estats.rx_errors_total += np->estats.rx_drop_frame; in nv_update_stats()
1726 if (np->driver_data & DEV_HAS_STATISTICS_V3) { in nv_update_stats()
1727 np->estats.tx_unicast += readl(base + NvRegTxUnicast); in nv_update_stats()
1728 np->estats.tx_multicast += readl(base + NvRegTxMulticast); in nv_update_stats()
1729 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); in nv_update_stats()
1733 static void nv_get_stats(int cpu, struct fe_priv *np, in nv_get_stats() argument
1736 struct nv_txrx_stats *src = per_cpu_ptr(np->txrx_stats, cpu); in nv_get_stats()
1742 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_rx_syncp); in nv_get_stats()
1747 } while (u64_stats_fetch_retry_irq(&np->swstats_rx_syncp, syncp_start)); in nv_get_stats()
1755 syncp_start = u64_stats_fetch_begin_irq(&np->swstats_tx_syncp); in nv_get_stats()
1759 } while (u64_stats_fetch_retry_irq(&np->swstats_tx_syncp, syncp_start)); in nv_get_stats()
1777 struct fe_priv *np = netdev_priv(dev); in nv_get_stats64() local
1792 nv_get_stats(cpu, np, storage); in nv_get_stats64()
1795 if (np->driver_data & DEV_HAS_STATISTICS_V123) { in nv_get_stats64()
1796 spin_lock_bh(&np->hwstats_lock); in nv_get_stats64()
1801 storage->rx_errors = np->estats.rx_errors_total; in nv_get_stats64()
1802 storage->tx_errors = np->estats.tx_errors_total; in nv_get_stats64()
1805 storage->multicast = np->estats.rx_multicast; in nv_get_stats64()
1808 storage->rx_length_errors = np->estats.rx_length_error; in nv_get_stats64()
1809 storage->rx_over_errors = np->estats.rx_over_errors; in nv_get_stats64()
1810 storage->rx_crc_errors = np->estats.rx_crc_errors; in nv_get_stats64()
1811 storage->rx_frame_errors = np->estats.rx_frame_align_error; in nv_get_stats64()
1812 storage->rx_fifo_errors = np->estats.rx_drop_frame; in nv_get_stats64()
1815 storage->tx_carrier_errors = np->estats.tx_carrier_errors; in nv_get_stats64()
1816 storage->tx_fifo_errors = np->estats.tx_fifo_errors; in nv_get_stats64()
1818 spin_unlock_bh(&np->hwstats_lock); in nv_get_stats64()
1829 struct fe_priv *np = netdev_priv(dev); in nv_alloc_rx() local
1832 less_rx = np->get_rx.orig; in nv_alloc_rx()
1833 if (less_rx-- == np->rx_ring.orig) in nv_alloc_rx()
1834 less_rx = np->last_rx.orig; in nv_alloc_rx()
1836 while (np->put_rx.orig != less_rx) { in nv_alloc_rx()
1837 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); in nv_alloc_rx()
1839 np->put_rx_ctx->skb = skb; in nv_alloc_rx()
1840 np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_alloc_rx()
1844 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_alloc_rx()
1845 np->put_rx_ctx->dma))) { in nv_alloc_rx()
1849 np->put_rx_ctx->dma_len = skb_tailroom(skb); in nv_alloc_rx()
1850 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); in nv_alloc_rx()
1852 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); in nv_alloc_rx()
1853 if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) in nv_alloc_rx()
1854 np->put_rx.orig = np->rx_ring.orig; in nv_alloc_rx()
1855 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) in nv_alloc_rx()
1856 np->put_rx_ctx = np->rx_skb; in nv_alloc_rx()
1859 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_alloc_rx()
1861 u64_stats_update_end(&np->swstats_rx_syncp); in nv_alloc_rx()
1870 struct fe_priv *np = netdev_priv(dev); in nv_alloc_rx_optimized() local
1873 less_rx = np->get_rx.ex; in nv_alloc_rx_optimized()
1874 if (less_rx-- == np->rx_ring.ex) in nv_alloc_rx_optimized()
1875 less_rx = np->last_rx.ex; in nv_alloc_rx_optimized()
1877 while (np->put_rx.ex != less_rx) { in nv_alloc_rx_optimized()
1878 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); in nv_alloc_rx_optimized()
1880 np->put_rx_ctx->skb = skb; in nv_alloc_rx_optimized()
1881 np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_alloc_rx_optimized()
1885 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_alloc_rx_optimized()
1886 np->put_rx_ctx->dma))) { in nv_alloc_rx_optimized()
1890 np->put_rx_ctx->dma_len = skb_tailroom(skb); in nv_alloc_rx_optimized()
1891 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); in nv_alloc_rx_optimized()
1892 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); in nv_alloc_rx_optimized()
1894 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); in nv_alloc_rx_optimized()
1895 if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) in nv_alloc_rx_optimized()
1896 np->put_rx.ex = np->rx_ring.ex; in nv_alloc_rx_optimized()
1897 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) in nv_alloc_rx_optimized()
1898 np->put_rx_ctx = np->rx_skb; in nv_alloc_rx_optimized()
1901 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_alloc_rx_optimized()
1903 u64_stats_update_end(&np->swstats_rx_syncp); in nv_alloc_rx_optimized()
1913 struct fe_priv *np = from_timer(np, t, oom_kick); in nv_do_rx_refill() local
1916 napi_schedule(&np->napi); in nv_do_rx_refill()
1921 struct fe_priv *np = netdev_priv(dev); in nv_init_rx() local
1924 np->get_rx = np->rx_ring; in nv_init_rx()
1925 np->put_rx = np->rx_ring; in nv_init_rx()
1927 if (!nv_optimized(np)) in nv_init_rx()
1928 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; in nv_init_rx()
1930 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; in nv_init_rx()
1931 np->get_rx_ctx = np->rx_skb; in nv_init_rx()
1932 np->put_rx_ctx = np->rx_skb; in nv_init_rx()
1933 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; in nv_init_rx()
1935 for (i = 0; i < np->rx_ring_size; i++) { in nv_init_rx()
1936 if (!nv_optimized(np)) { in nv_init_rx()
1937 np->rx_ring.orig[i].flaglen = 0; in nv_init_rx()
1938 np->rx_ring.orig[i].buf = 0; in nv_init_rx()
1940 np->rx_ring.ex[i].flaglen = 0; in nv_init_rx()
1941 np->rx_ring.ex[i].txvlan = 0; in nv_init_rx()
1942 np->rx_ring.ex[i].bufhigh = 0; in nv_init_rx()
1943 np->rx_ring.ex[i].buflow = 0; in nv_init_rx()
1945 np->rx_skb[i].skb = NULL; in nv_init_rx()
1946 np->rx_skb[i].dma = 0; in nv_init_rx()
1952 struct fe_priv *np = netdev_priv(dev); in nv_init_tx() local
1955 np->get_tx = np->tx_ring; in nv_init_tx()
1956 np->put_tx = np->tx_ring; in nv_init_tx()
1958 if (!nv_optimized(np)) in nv_init_tx()
1959 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; in nv_init_tx()
1961 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; in nv_init_tx()
1962 np->get_tx_ctx = np->tx_skb; in nv_init_tx()
1963 np->put_tx_ctx = np->tx_skb; in nv_init_tx()
1964 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; in nv_init_tx()
1965 netdev_reset_queue(np->dev); in nv_init_tx()
1966 np->tx_pkts_in_progress = 0; in nv_init_tx()
1967 np->tx_change_owner = NULL; in nv_init_tx()
1968 np->tx_end_flip = NULL; in nv_init_tx()
1969 np->tx_stop = 0; in nv_init_tx()
1971 for (i = 0; i < np->tx_ring_size; i++) { in nv_init_tx()
1972 if (!nv_optimized(np)) { in nv_init_tx()
1973 np->tx_ring.orig[i].flaglen = 0; in nv_init_tx()
1974 np->tx_ring.orig[i].buf = 0; in nv_init_tx()
1976 np->tx_ring.ex[i].flaglen = 0; in nv_init_tx()
1977 np->tx_ring.ex[i].txvlan = 0; in nv_init_tx()
1978 np->tx_ring.ex[i].bufhigh = 0; in nv_init_tx()
1979 np->tx_ring.ex[i].buflow = 0; in nv_init_tx()
1981 np->tx_skb[i].skb = NULL; in nv_init_tx()
1982 np->tx_skb[i].dma = 0; in nv_init_tx()
1983 np->tx_skb[i].dma_len = 0; in nv_init_tx()
1984 np->tx_skb[i].dma_single = 0; in nv_init_tx()
1985 np->tx_skb[i].first_tx_desc = NULL; in nv_init_tx()
1986 np->tx_skb[i].next_tx_ctx = NULL; in nv_init_tx()
1992 struct fe_priv *np = netdev_priv(dev); in nv_init_ring() local
1997 if (!nv_optimized(np)) in nv_init_ring()
2003 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) in nv_unmap_txskb() argument
2007 dma_unmap_single(&np->pci_dev->dev, tx_skb->dma, in nv_unmap_txskb()
2011 dma_unmap_page(&np->pci_dev->dev, tx_skb->dma, in nv_unmap_txskb()
2018 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) in nv_release_txskb() argument
2020 nv_unmap_txskb(np, tx_skb); in nv_release_txskb()
2031 struct fe_priv *np = netdev_priv(dev); in nv_drain_tx() local
2034 for (i = 0; i < np->tx_ring_size; i++) { in nv_drain_tx()
2035 if (!nv_optimized(np)) { in nv_drain_tx()
2036 np->tx_ring.orig[i].flaglen = 0; in nv_drain_tx()
2037 np->tx_ring.orig[i].buf = 0; in nv_drain_tx()
2039 np->tx_ring.ex[i].flaglen = 0; in nv_drain_tx()
2040 np->tx_ring.ex[i].txvlan = 0; in nv_drain_tx()
2041 np->tx_ring.ex[i].bufhigh = 0; in nv_drain_tx()
2042 np->tx_ring.ex[i].buflow = 0; in nv_drain_tx()
2044 if (nv_release_txskb(np, &np->tx_skb[i])) { in nv_drain_tx()
2045 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_drain_tx()
2047 u64_stats_update_end(&np->swstats_tx_syncp); in nv_drain_tx()
2049 np->tx_skb[i].dma = 0; in nv_drain_tx()
2050 np->tx_skb[i].dma_len = 0; in nv_drain_tx()
2051 np->tx_skb[i].dma_single = 0; in nv_drain_tx()
2052 np->tx_skb[i].first_tx_desc = NULL; in nv_drain_tx()
2053 np->tx_skb[i].next_tx_ctx = NULL; in nv_drain_tx()
2055 np->tx_pkts_in_progress = 0; in nv_drain_tx()
2056 np->tx_change_owner = NULL; in nv_drain_tx()
2057 np->tx_end_flip = NULL; in nv_drain_tx()
2062 struct fe_priv *np = netdev_priv(dev); in nv_drain_rx() local
2065 for (i = 0; i < np->rx_ring_size; i++) { in nv_drain_rx()
2066 if (!nv_optimized(np)) { in nv_drain_rx()
2067 np->rx_ring.orig[i].flaglen = 0; in nv_drain_rx()
2068 np->rx_ring.orig[i].buf = 0; in nv_drain_rx()
2070 np->rx_ring.ex[i].flaglen = 0; in nv_drain_rx()
2071 np->rx_ring.ex[i].txvlan = 0; in nv_drain_rx()
2072 np->rx_ring.ex[i].bufhigh = 0; in nv_drain_rx()
2073 np->rx_ring.ex[i].buflow = 0; in nv_drain_rx()
2076 if (np->rx_skb[i].skb) { in nv_drain_rx()
2077 dma_unmap_single(&np->pci_dev->dev, np->rx_skb[i].dma, in nv_drain_rx()
2078 (skb_end_pointer(np->rx_skb[i].skb) - in nv_drain_rx()
2079 np->rx_skb[i].skb->data), in nv_drain_rx()
2081 dev_kfree_skb(np->rx_skb[i].skb); in nv_drain_rx()
2082 np->rx_skb[i].skb = NULL; in nv_drain_rx()
2093 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) in nv_get_empty_tx_slots() argument
2095 …return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_r… in nv_get_empty_tx_slots()
2212 struct fe_priv *np = netdev_priv(dev); in nv_start_xmit() local
2214 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); in nv_start_xmit()
2237 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit()
2238 empty_slots = nv_get_empty_tx_slots(np); in nv_start_xmit()
2241 np->tx_stop = 1; in nv_start_xmit()
2242 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit()
2245 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit()
2247 start_tx = put_tx = np->put_tx.orig; in nv_start_xmit()
2252 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_start_xmit()
2255 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit()
2256 np->put_tx_ctx->dma))) { in nv_start_xmit()
2259 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit()
2261 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit()
2264 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit()
2265 np->put_tx_ctx->dma_single = 1; in nv_start_xmit()
2266 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); in nv_start_xmit()
2269 tx_flags = np->tx_flags; in nv_start_xmit()
2272 if (unlikely(put_tx++ == np->last_tx.orig)) in nv_start_xmit()
2273 put_tx = np->tx_ring.orig; in nv_start_xmit()
2274 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit()
2275 np->put_tx_ctx = np->tx_skb; in nv_start_xmit()
2286 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; in nv_start_xmit()
2289 np->put_tx_ctx->dma = skb_frag_dma_map( in nv_start_xmit()
2290 &np->pci_dev->dev, in nv_start_xmit()
2294 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit()
2295 np->put_tx_ctx->dma))) { in nv_start_xmit()
2299 nv_unmap_txskb(np, start_tx_ctx); in nv_start_xmit()
2300 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit()
2301 tmp_tx_ctx = np->tx_skb; in nv_start_xmit()
2302 } while (tmp_tx_ctx != np->put_tx_ctx); in nv_start_xmit()
2304 np->put_tx_ctx = start_tx_ctx; in nv_start_xmit()
2305 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit()
2307 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit()
2311 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit()
2312 np->put_tx_ctx->dma_single = 0; in nv_start_xmit()
2313 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); in nv_start_xmit()
2318 if (unlikely(put_tx++ == np->last_tx.orig)) in nv_start_xmit()
2319 put_tx = np->tx_ring.orig; in nv_start_xmit()
2320 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit()
2321 np->put_tx_ctx = np->tx_skb; in nv_start_xmit()
2325 if (unlikely(put_tx == np->tx_ring.orig)) in nv_start_xmit()
2326 prev_tx = np->last_tx.orig; in nv_start_xmit()
2330 if (unlikely(np->put_tx_ctx == np->tx_skb)) in nv_start_xmit()
2331 prev_tx_ctx = np->last_tx_ctx; in nv_start_xmit()
2333 prev_tx_ctx = np->put_tx_ctx - 1; in nv_start_xmit()
2347 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit()
2352 netdev_sent_queue(np->dev, skb->len); in nv_start_xmit()
2356 np->put_tx.orig = put_tx; in nv_start_xmit()
2358 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit()
2360 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_start_xmit()
2367 struct fe_priv *np = netdev_priv(dev); in nv_start_xmit_optimized() local
2393 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit_optimized()
2394 empty_slots = nv_get_empty_tx_slots(np); in nv_start_xmit_optimized()
2397 np->tx_stop = 1; in nv_start_xmit_optimized()
2398 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit_optimized()
2401 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit_optimized()
2403 start_tx = put_tx = np->put_tx.ex; in nv_start_xmit_optimized()
2404 start_tx_ctx = np->put_tx_ctx; in nv_start_xmit_optimized()
2409 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_start_xmit_optimized()
2412 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit_optimized()
2413 np->put_tx_ctx->dma))) { in nv_start_xmit_optimized()
2416 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2418 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2421 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit_optimized()
2422 np->put_tx_ctx->dma_single = 1; in nv_start_xmit_optimized()
2423 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2424 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2430 if (unlikely(put_tx++ == np->last_tx.ex)) in nv_start_xmit_optimized()
2431 put_tx = np->tx_ring.ex; in nv_start_xmit_optimized()
2432 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit_optimized()
2433 np->put_tx_ctx = np->tx_skb; in nv_start_xmit_optimized()
2445 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; in nv_start_xmit_optimized()
2446 np->put_tx_ctx->dma = skb_frag_dma_map( in nv_start_xmit_optimized()
2447 &np->pci_dev->dev, in nv_start_xmit_optimized()
2452 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit_optimized()
2453 np->put_tx_ctx->dma))) { in nv_start_xmit_optimized()
2457 nv_unmap_txskb(np, start_tx_ctx); in nv_start_xmit_optimized()
2458 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit_optimized()
2459 tmp_tx_ctx = np->tx_skb; in nv_start_xmit_optimized()
2460 } while (tmp_tx_ctx != np->put_tx_ctx); in nv_start_xmit_optimized()
2462 np->put_tx_ctx = start_tx_ctx; in nv_start_xmit_optimized()
2463 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2465 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2468 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit_optimized()
2469 np->put_tx_ctx->dma_single = 0; in nv_start_xmit_optimized()
2470 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2471 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2476 if (unlikely(put_tx++ == np->last_tx.ex)) in nv_start_xmit_optimized()
2477 put_tx = np->tx_ring.ex; in nv_start_xmit_optimized()
2478 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit_optimized()
2479 np->put_tx_ctx = np->tx_skb; in nv_start_xmit_optimized()
2483 if (unlikely(put_tx == np->tx_ring.ex)) in nv_start_xmit_optimized()
2484 prev_tx = np->last_tx.ex; in nv_start_xmit_optimized()
2488 if (unlikely(np->put_tx_ctx == np->tx_skb)) in nv_start_xmit_optimized()
2489 prev_tx_ctx = np->last_tx_ctx; in nv_start_xmit_optimized()
2491 prev_tx_ctx = np->put_tx_ctx - 1; in nv_start_xmit_optimized()
2512 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit_optimized()
2514 if (np->tx_limit) { in nv_start_xmit_optimized()
2520 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { in nv_start_xmit_optimized()
2521 if (!np->tx_change_owner) in nv_start_xmit_optimized()
2522 np->tx_change_owner = start_tx_ctx; in nv_start_xmit_optimized()
2527 start_tx_ctx->next_tx_ctx = np->put_tx_ctx; in nv_start_xmit_optimized()
2528 np->tx_end_flip = np->put_tx_ctx; in nv_start_xmit_optimized()
2530 np->tx_pkts_in_progress++; in nv_start_xmit_optimized()
2537 netdev_sent_queue(np->dev, skb->len); in nv_start_xmit_optimized()
2541 np->put_tx.ex = put_tx; in nv_start_xmit_optimized()
2543 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit_optimized()
2545 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_start_xmit_optimized()
2551 struct fe_priv *np = netdev_priv(dev); in nv_tx_flip_ownership() local
2553 np->tx_pkts_in_progress--; in nv_tx_flip_ownership()
2554 if (np->tx_change_owner) { in nv_tx_flip_ownership()
2555 np->tx_change_owner->first_tx_desc->flaglen |= in nv_tx_flip_ownership()
2557 np->tx_pkts_in_progress++; in nv_tx_flip_ownership()
2559 np->tx_change_owner = np->tx_change_owner->next_tx_ctx; in nv_tx_flip_ownership()
2560 if (np->tx_change_owner == np->tx_end_flip) in nv_tx_flip_ownership()
2561 np->tx_change_owner = NULL; in nv_tx_flip_ownership()
2563 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_tx_flip_ownership()
2574 struct fe_priv *np = netdev_priv(dev); in nv_tx_done() local
2577 struct ring_desc *orig_get_tx = np->get_tx.orig; in nv_tx_done()
2580 while ((np->get_tx.orig != np->put_tx.orig) && in nv_tx_done()
2581 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && in nv_tx_done()
2584 nv_unmap_txskb(np, np->get_tx_ctx); in nv_tx_done()
2586 if (np->desc_ver == DESC_VER_1) { in nv_tx_done()
2595 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_tx_done()
2597 len = np->get_tx_ctx->skb->len; in nv_tx_done()
2599 u64_stats_update_end(&np->swstats_tx_syncp); in nv_tx_done()
2601 bytes_compl += np->get_tx_ctx->skb->len; in nv_tx_done()
2602 dev_kfree_skb_any(np->get_tx_ctx->skb); in nv_tx_done()
2603 np->get_tx_ctx->skb = NULL; in nv_tx_done()
2615 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_tx_done()
2617 len = np->get_tx_ctx->skb->len; in nv_tx_done()
2619 u64_stats_update_end(&np->swstats_tx_syncp); in nv_tx_done()
2621 bytes_compl += np->get_tx_ctx->skb->len; in nv_tx_done()
2622 dev_kfree_skb_any(np->get_tx_ctx->skb); in nv_tx_done()
2623 np->get_tx_ctx->skb = NULL; in nv_tx_done()
2627 if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) in nv_tx_done()
2628 np->get_tx.orig = np->tx_ring.orig; in nv_tx_done()
2629 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) in nv_tx_done()
2630 np->get_tx_ctx = np->tx_skb; in nv_tx_done()
2633 netdev_completed_queue(np->dev, tx_work, bytes_compl); in nv_tx_done()
2635 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { in nv_tx_done()
2636 np->tx_stop = 0; in nv_tx_done()
2644 struct fe_priv *np = netdev_priv(dev); in nv_tx_done_optimized() local
2647 struct ring_desc_ex *orig_get_tx = np->get_tx.ex; in nv_tx_done_optimized()
2650 while ((np->get_tx.ex != np->put_tx.ex) && in nv_tx_done_optimized()
2651 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && in nv_tx_done_optimized()
2654 nv_unmap_txskb(np, np->get_tx_ctx); in nv_tx_done_optimized()
2660 if (np->driver_data & DEV_HAS_GEAR_MODE) in nv_tx_done_optimized()
2668 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_tx_done_optimized()
2670 len = np->get_tx_ctx->skb->len; in nv_tx_done_optimized()
2672 u64_stats_update_end(&np->swstats_tx_syncp); in nv_tx_done_optimized()
2675 bytes_cleaned += np->get_tx_ctx->skb->len; in nv_tx_done_optimized()
2676 dev_kfree_skb_any(np->get_tx_ctx->skb); in nv_tx_done_optimized()
2677 np->get_tx_ctx->skb = NULL; in nv_tx_done_optimized()
2680 if (np->tx_limit) in nv_tx_done_optimized()
2684 if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) in nv_tx_done_optimized()
2685 np->get_tx.ex = np->tx_ring.ex; in nv_tx_done_optimized()
2686 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) in nv_tx_done_optimized()
2687 np->get_tx_ctx = np->tx_skb; in nv_tx_done_optimized()
2690 netdev_completed_queue(np->dev, tx_work, bytes_cleaned); in nv_tx_done_optimized()
2692 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { in nv_tx_done_optimized()
2693 np->tx_stop = 0; in nv_tx_done_optimized()
2705 struct fe_priv *np = netdev_priv(dev); in nv_tx_timeout() local
2711 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_tx_timeout()
2721 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); in nv_tx_timeout()
2723 for (i = 0; i <= np->register_size; i += 32) { in nv_tx_timeout()
2734 for (i = 0; i < np->tx_ring_size; i += 4) { in nv_tx_timeout()
2735 if (!nv_optimized(np)) { in nv_tx_timeout()
2740 le32_to_cpu(np->tx_ring.orig[i].buf), in nv_tx_timeout()
2741 le32_to_cpu(np->tx_ring.orig[i].flaglen), in nv_tx_timeout()
2742 le32_to_cpu(np->tx_ring.orig[i+1].buf), in nv_tx_timeout()
2743 le32_to_cpu(np->tx_ring.orig[i+1].flaglen), in nv_tx_timeout()
2744 le32_to_cpu(np->tx_ring.orig[i+2].buf), in nv_tx_timeout()
2745 le32_to_cpu(np->tx_ring.orig[i+2].flaglen), in nv_tx_timeout()
2746 le32_to_cpu(np->tx_ring.orig[i+3].buf), in nv_tx_timeout()
2747 le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); in nv_tx_timeout()
2755 le32_to_cpu(np->tx_ring.ex[i].bufhigh), in nv_tx_timeout()
2756 le32_to_cpu(np->tx_ring.ex[i].buflow), in nv_tx_timeout()
2757 le32_to_cpu(np->tx_ring.ex[i].flaglen), in nv_tx_timeout()
2758 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), in nv_tx_timeout()
2759 le32_to_cpu(np->tx_ring.ex[i+1].buflow), in nv_tx_timeout()
2760 le32_to_cpu(np->tx_ring.ex[i+1].flaglen), in nv_tx_timeout()
2761 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), in nv_tx_timeout()
2762 le32_to_cpu(np->tx_ring.ex[i+2].buflow), in nv_tx_timeout()
2763 le32_to_cpu(np->tx_ring.ex[i+2].flaglen), in nv_tx_timeout()
2764 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), in nv_tx_timeout()
2765 le32_to_cpu(np->tx_ring.ex[i+3].buflow), in nv_tx_timeout()
2766 le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); in nv_tx_timeout()
2771 spin_lock_irq(&np->lock); in nv_tx_timeout()
2777 saved_tx_limit = np->tx_limit; in nv_tx_timeout()
2778 np->tx_limit = 0; /* prevent giving HW any limited pkts */ in nv_tx_timeout()
2779 np->tx_stop = 0; /* prevent waking tx queue */ in nv_tx_timeout()
2780 if (!nv_optimized(np)) in nv_tx_timeout()
2781 nv_tx_done(dev, np->tx_ring_size); in nv_tx_timeout()
2783 nv_tx_done_optimized(dev, np->tx_ring_size); in nv_tx_timeout()
2786 if (np->tx_change_owner) in nv_tx_timeout()
2787 put_tx.ex = np->tx_change_owner->first_tx_desc; in nv_tx_timeout()
2789 put_tx = np->put_tx; in nv_tx_timeout()
2796 np->get_tx = np->put_tx = put_tx; in nv_tx_timeout()
2797 np->tx_limit = saved_tx_limit; in nv_tx_timeout()
2802 spin_unlock_irq(&np->lock); in nv_tx_timeout()
2848 static void rx_missing_handler(u32 flags, struct fe_priv *np) in rx_missing_handler() argument
2851 u64_stats_update_begin(&np->swstats_rx_syncp); in rx_missing_handler()
2853 u64_stats_update_end(&np->swstats_rx_syncp); in rx_missing_handler()
2859 struct fe_priv *np = netdev_priv(dev); in nv_rx_process() local
2865 while ((np->get_rx.orig != np->put_rx.orig) && in nv_rx_process()
2866 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && in nv_rx_process()
2874 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma, in nv_rx_process()
2875 np->get_rx_ctx->dma_len, in nv_rx_process()
2877 skb = np->get_rx_ctx->skb; in nv_rx_process()
2878 np->get_rx_ctx->skb = NULL; in nv_rx_process()
2881 if (np->desc_ver == DESC_VER_1) { in nv_rx_process()
2899 rx_missing_handler(flags, np); in nv_rx_process()
2941 napi_gro_receive(&np->napi, skb); in nv_rx_process()
2942 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_rx_process()
2945 u64_stats_update_end(&np->swstats_rx_syncp); in nv_rx_process()
2947 if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) in nv_rx_process()
2948 np->get_rx.orig = np->rx_ring.orig; in nv_rx_process()
2949 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) in nv_rx_process()
2950 np->get_rx_ctx = np->rx_skb; in nv_rx_process()
2960 struct fe_priv *np = netdev_priv(dev); in nv_rx_process_optimized() local
2967 while ((np->get_rx.ex != np->put_rx.ex) && in nv_rx_process_optimized()
2968 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && in nv_rx_process_optimized()
2976 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma, in nv_rx_process_optimized()
2977 np->get_rx_ctx->dma_len, in nv_rx_process_optimized()
2979 skb = np->get_rx_ctx->skb; in nv_rx_process_optimized()
2980 np->get_rx_ctx->skb = NULL; in nv_rx_process_optimized()
3014 vlanflags = le32_to_cpu(np->get_rx.ex->buflow); in nv_rx_process_optimized()
3027 napi_gro_receive(&np->napi, skb); in nv_rx_process_optimized()
3028 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_rx_process_optimized()
3031 u64_stats_update_end(&np->swstats_rx_syncp); in nv_rx_process_optimized()
3036 if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) in nv_rx_process_optimized()
3037 np->get_rx.ex = np->rx_ring.ex; in nv_rx_process_optimized()
3038 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) in nv_rx_process_optimized()
3039 np->get_rx_ctx = np->rx_skb; in nv_rx_process_optimized()
3049 struct fe_priv *np = netdev_priv(dev); in set_bufsize() local
3052 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; in set_bufsize()
3054 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; in set_bufsize()
3063 struct fe_priv *np = netdev_priv(dev); in nv_change_mtu() local
3086 spin_lock(&np->lock); in nv_change_mtu()
3095 if (!np->in_shutdown) in nv_change_mtu()
3096 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_change_mtu()
3099 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_change_mtu()
3101 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_change_mtu()
3104 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_change_mtu()
3109 spin_unlock(&np->lock); in nv_change_mtu()
3137 struct fe_priv *np = netdev_priv(dev); in nv_set_mac_address() local
3149 spin_lock_irq(&np->lock); in nv_set_mac_address()
3159 spin_unlock_irq(&np->lock); in nv_set_mac_address()
3174 struct fe_priv *np = netdev_priv(dev); in nv_set_multicast() local
3221 spin_lock_irq(&np->lock); in nv_set_multicast()
3229 spin_unlock_irq(&np->lock); in nv_set_multicast()
3234 struct fe_priv *np = netdev_priv(dev); in nv_update_pause() local
3237 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); in nv_update_pause()
3239 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { in nv_update_pause()
3243 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; in nv_update_pause()
3248 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { in nv_update_pause()
3252 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) in nv_update_pause()
3254 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { in nv_update_pause()
3261 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; in nv_update_pause()
3271 struct fe_priv *np = netdev_priv(dev); in nv_force_linkspeed() local
3276 np->linkspeed = NVREG_LINKSPEED_FORCE|speed; in nv_force_linkspeed()
3277 np->duplex = duplex; in nv_force_linkspeed()
3280 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3282 np->gigabit = PHY_GIGABIT; in nv_force_linkspeed()
3285 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) in nv_force_linkspeed()
3287 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) in nv_force_linkspeed()
3289 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) in nv_force_linkspeed()
3296 if (np->duplex == 0) in nv_force_linkspeed()
3298 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) in nv_force_linkspeed()
3300 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == in nv_force_linkspeed()
3306 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == in nv_force_linkspeed()
3316 if (np->desc_ver == DESC_VER_1) { in nv_force_linkspeed()
3319 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == in nv_force_linkspeed()
3327 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in nv_force_linkspeed()
3330 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_force_linkspeed()
3347 struct fe_priv *np = netdev_priv(dev); in nv_update_linkspeed() local
3352 int newls = np->linkspeed; in nv_update_linkspeed()
3353 int newdup = np->duplex; in nv_update_linkspeed()
3364 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3377 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3378 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3387 if (np->autoneg == 0) { in nv_update_linkspeed()
3388 if (np->fixed_mode & LPA_100FULL) { in nv_update_linkspeed()
3391 } else if (np->fixed_mode & LPA_100HALF) { in nv_update_linkspeed()
3394 } else if (np->fixed_mode & LPA_10FULL) { in nv_update_linkspeed()
3413 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3414 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3417 if (np->gigabit == PHY_GIGABIT) { in nv_update_linkspeed()
3418 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3419 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3449 if (np->duplex == newdup && np->linkspeed == newls) in nv_update_linkspeed()
3452 np->duplex = newdup; in nv_update_linkspeed()
3453 np->linkspeed = newls; in nv_update_linkspeed()
3465 if (np->gigabit == PHY_GIGABIT) { in nv_update_linkspeed()
3468 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || in nv_update_linkspeed()
3469 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) in nv_update_linkspeed()
3471 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3478 if (np->duplex == 0) in nv_update_linkspeed()
3480 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) in nv_update_linkspeed()
3482 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3486 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
3488 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { in nv_update_linkspeed()
3491 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { in nv_update_linkspeed()
3492 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) in nv_update_linkspeed()
3501 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) in nv_update_linkspeed()
3508 if (np->desc_ver == DESC_VER_1) { in nv_update_linkspeed()
3511 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3518 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in nv_update_linkspeed()
3521 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_update_linkspeed()
3526 if (netif_running(dev) && (np->duplex != 0)) { in nv_update_linkspeed()
3527 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { in nv_update_linkspeed()
3535 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_update_linkspeed()
3546 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_update_linkspeed()
3554 pause_flags = np->pause_flags; in nv_update_linkspeed()
3598 static void nv_msi_workaround(struct fe_priv *np) in nv_msi_workaround() argument
3604 if (np->msi_flags & NV_MSI_ENABLED) { in nv_msi_workaround()
3605 u8 __iomem *base = np->base; in nv_msi_workaround()
3614 struct fe_priv *np = netdev_priv(dev); in nv_change_interrupt_mode() local
3619 np->quiet_count = 0; in nv_change_interrupt_mode()
3620 if (np->irqmask != NVREG_IRQMASK_CPU) { in nv_change_interrupt_mode()
3621 np->irqmask = NVREG_IRQMASK_CPU; in nv_change_interrupt_mode()
3625 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { in nv_change_interrupt_mode()
3626 np->quiet_count++; in nv_change_interrupt_mode()
3630 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { in nv_change_interrupt_mode()
3631 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_change_interrupt_mode()
3643 struct fe_priv *np = netdev_priv(dev); in nv_nic_irq() local
3646 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { in nv_nic_irq()
3647 np->events = readl(base + NvRegIrqStatus); in nv_nic_irq()
3648 writel(np->events, base + NvRegIrqStatus); in nv_nic_irq()
3650 np->events = readl(base + NvRegMSIXIrqStatus); in nv_nic_irq()
3651 writel(np->events, base + NvRegMSIXIrqStatus); in nv_nic_irq()
3653 if (!(np->events & np->irqmask)) in nv_nic_irq()
3656 nv_msi_workaround(np); in nv_nic_irq()
3658 if (napi_schedule_prep(&np->napi)) { in nv_nic_irq()
3663 __napi_schedule(&np->napi); in nv_nic_irq()
3676 struct fe_priv *np = netdev_priv(dev); in nv_nic_irq_optimized() local
3679 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { in nv_nic_irq_optimized()
3680 np->events = readl(base + NvRegIrqStatus); in nv_nic_irq_optimized()
3681 writel(np->events, base + NvRegIrqStatus); in nv_nic_irq_optimized()
3683 np->events = readl(base + NvRegMSIXIrqStatus); in nv_nic_irq_optimized()
3684 writel(np->events, base + NvRegMSIXIrqStatus); in nv_nic_irq_optimized()
3686 if (!(np->events & np->irqmask)) in nv_nic_irq_optimized()
3689 nv_msi_workaround(np); in nv_nic_irq_optimized()
3691 if (napi_schedule_prep(&np->napi)) { in nv_nic_irq_optimized()
3696 __napi_schedule(&np->napi); in nv_nic_irq_optimized()
3705 struct fe_priv *np = netdev_priv(dev); in nv_nic_irq_tx() local
3715 if (!(events & np->irqmask)) in nv_nic_irq_tx()
3718 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_tx()
3720 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_tx()
3723 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_tx()
3728 if (!np->in_shutdown) { in nv_nic_irq_tx()
3729 np->nic_poll_irq |= NVREG_IRQ_TX_ALL; in nv_nic_irq_tx()
3730 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_tx()
3732 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_tx()
3745 struct fe_priv *np = container_of(napi, struct fe_priv, napi); in nv_napi_poll() local
3746 struct net_device *dev = np->dev; in nv_napi_poll()
3753 if (!nv_optimized(np)) { in nv_napi_poll()
3754 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3755 tx_work += nv_tx_done(dev, np->tx_ring_size); in nv_napi_poll()
3756 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3761 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3762 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); in nv_napi_poll()
3763 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3773 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3774 if (!np->in_shutdown) in nv_napi_poll()
3775 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_napi_poll()
3776 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3781 if (unlikely(np->events & NVREG_IRQ_LINK)) { in nv_napi_poll()
3782 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3784 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3786 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { in nv_napi_poll()
3787 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3789 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3790 np->link_timeout = jiffies + LINK_TIMEOUT; in nv_napi_poll()
3792 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { in nv_napi_poll()
3793 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3794 if (!np->in_shutdown) { in nv_napi_poll()
3795 np->nic_poll_irq = np->irqmask; in nv_napi_poll()
3796 np->recover_error = 1; in nv_napi_poll()
3797 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_napi_poll()
3799 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3809 writel(np->irqmask, base + NvRegIrqMask); in nv_napi_poll()
3817 struct fe_priv *np = netdev_priv(dev); in nv_nic_irq_rx() local
3827 if (!(events & np->irqmask)) in nv_nic_irq_rx()
3832 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_rx()
3833 if (!np->in_shutdown) in nv_nic_irq_rx()
3834 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_nic_irq_rx()
3835 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_rx()
3840 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_rx()
3845 if (!np->in_shutdown) { in nv_nic_irq_rx()
3846 np->nic_poll_irq |= NVREG_IRQ_RX_ALL; in nv_nic_irq_rx()
3847 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_rx()
3849 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_rx()
3862 struct fe_priv *np = netdev_priv(dev); in nv_nic_irq_other() local
3872 if (!(events & np->irqmask)) in nv_nic_irq_other()
3876 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3878 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3881 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3883 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3885 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { in nv_nic_irq_other()
3886 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3888 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3889 np->link_timeout = jiffies + LINK_TIMEOUT; in nv_nic_irq_other()
3892 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3897 if (!np->in_shutdown) { in nv_nic_irq_other()
3898 np->nic_poll_irq |= NVREG_IRQ_OTHER; in nv_nic_irq_other()
3899 np->recover_error = 1; in nv_nic_irq_other()
3900 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_other()
3902 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3906 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3911 if (!np->in_shutdown) { in nv_nic_irq_other()
3912 np->nic_poll_irq |= NVREG_IRQ_OTHER; in nv_nic_irq_other()
3913 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_other()
3915 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3929 struct fe_priv *np = netdev_priv(dev); in nv_nic_irq_test() local
3933 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { in nv_nic_irq_test()
3944 nv_msi_workaround(np); in nv_nic_irq_test()
3946 spin_lock(&np->lock); in nv_nic_irq_test()
3947 np->intr_test = 1; in nv_nic_irq_test()
3948 spin_unlock(&np->lock); in nv_nic_irq_test()
3979 struct fe_priv *np = get_nvpriv(dev); in nv_request_irq() local
3988 if (nv_optimized(np)) in nv_request_irq()
3994 if (np->msi_flags & NV_MSI_X_CAPABLE) { in nv_request_irq()
3995 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) in nv_request_irq()
3996 np->msi_x_entry[i].entry = i; in nv_request_irq()
3997 ret = pci_enable_msix_range(np->pci_dev, in nv_request_irq()
3998 np->msi_x_entry, in nv_request_irq()
3999 np->msi_flags & NV_MSI_X_VECTORS_MASK, in nv_request_irq()
4000 np->msi_flags & NV_MSI_X_VECTORS_MASK); in nv_request_irq()
4002 np->msi_flags |= NV_MSI_X_ENABLED; in nv_request_irq()
4005 sprintf(np->name_rx, "%s-rx", dev->name); in nv_request_irq()
4006 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, in nv_request_irq()
4007 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev); in nv_request_irq()
4012 pci_disable_msix(np->pci_dev); in nv_request_irq()
4013 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4017 sprintf(np->name_tx, "%s-tx", dev->name); in nv_request_irq()
4018 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, in nv_request_irq()
4019 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev); in nv_request_irq()
4024 pci_disable_msix(np->pci_dev); in nv_request_irq()
4025 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4029 sprintf(np->name_other, "%s-other", dev->name); in nv_request_irq()
4030 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, in nv_request_irq()
4031 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev); in nv_request_irq()
4036 pci_disable_msix(np->pci_dev); in nv_request_irq()
4037 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4048 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, in nv_request_irq()
4054 pci_disable_msix(np->pci_dev); in nv_request_irq()
4055 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4067 if (np->msi_flags & NV_MSI_CAPABLE) { in nv_request_irq()
4068 ret = pci_enable_msi(np->pci_dev); in nv_request_irq()
4070 np->msi_flags |= NV_MSI_ENABLED; in nv_request_irq()
4071 ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev); in nv_request_irq()
4075 pci_disable_msi(np->pci_dev); in nv_request_irq()
4076 np->msi_flags &= ~NV_MSI_ENABLED; in nv_request_irq()
4090 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) in nv_request_irq()
4095 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); in nv_request_irq()
4097 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); in nv_request_irq()
4104 struct fe_priv *np = get_nvpriv(dev); in nv_free_irq() local
4107 if (np->msi_flags & NV_MSI_X_ENABLED) { in nv_free_irq()
4108 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) in nv_free_irq()
4109 free_irq(np->msi_x_entry[i].vector, dev); in nv_free_irq()
4110 pci_disable_msix(np->pci_dev); in nv_free_irq()
4111 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_free_irq()
4113 free_irq(np->pci_dev->irq, dev); in nv_free_irq()
4114 if (np->msi_flags & NV_MSI_ENABLED) { in nv_free_irq()
4115 pci_disable_msi(np->pci_dev); in nv_free_irq()
4116 np->msi_flags &= ~NV_MSI_ENABLED; in nv_free_irq()
4123 struct fe_priv *np = from_timer(np, t, nic_poll); in nv_do_nic_poll() local
4124 struct net_device *dev = np->dev; in nv_do_nic_poll()
4137 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_do_nic_poll()
4138 irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector; in nv_do_nic_poll()
4140 irq = np->pci_dev->irq; in nv_do_nic_poll()
4141 mask = np->irqmask; in nv_do_nic_poll()
4143 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { in nv_do_nic_poll()
4144 irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector; in nv_do_nic_poll()
4147 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { in nv_do_nic_poll()
4148 irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector; in nv_do_nic_poll()
4151 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { in nv_do_nic_poll()
4152 irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector; in nv_do_nic_poll()
4160 if (np->recover_error) { in nv_do_nic_poll()
4161 np->recover_error = 0; in nv_do_nic_poll()
4166 spin_lock(&np->lock); in nv_do_nic_poll()
4169 if (np->driver_data & DEV_HAS_POWER_CNTRL) in nv_do_nic_poll()
4177 if (!np->in_shutdown) in nv_do_nic_poll()
4178 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_do_nic_poll()
4181 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_do_nic_poll()
4183 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_do_nic_poll()
4186 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_do_nic_poll()
4189 if (!(np->msi_flags & NV_MSI_X_ENABLED)) in nv_do_nic_poll()
4196 spin_unlock(&np->lock); in nv_do_nic_poll()
4206 np->nic_poll_irq = 0; in nv_do_nic_poll()
4207 if (nv_optimized(np)) in nv_do_nic_poll()
4212 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { in nv_do_nic_poll()
4213 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; in nv_do_nic_poll()
4216 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { in nv_do_nic_poll()
4217 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; in nv_do_nic_poll()
4220 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { in nv_do_nic_poll()
4221 np->nic_poll_irq &= ~NVREG_IRQ_OTHER; in nv_do_nic_poll()
4232 struct fe_priv *np = netdev_priv(dev); in nv_poll_controller() local
4234 nv_do_nic_poll(&np->nic_poll); in nv_poll_controller()
4242 struct fe_priv *np = from_timer(np, t, stats_poll); in nv_do_stats_poll() local
4243 struct net_device *dev = np->dev; in nv_do_stats_poll()
4247 if (spin_trylock(&np->hwstats_lock)) { in nv_do_stats_poll()
4249 spin_unlock(&np->hwstats_lock); in nv_do_stats_poll()
4252 if (!np->in_shutdown) in nv_do_stats_poll()
4253 mod_timer(&np->stats_poll, in nv_do_stats_poll()
4259 struct fe_priv *np = netdev_priv(dev); in nv_get_drvinfo() local
4262 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); in nv_get_drvinfo()
4267 struct fe_priv *np = netdev_priv(dev); in nv_get_wol() local
4270 spin_lock_irq(&np->lock); in nv_get_wol()
4271 if (np->wolenabled) in nv_get_wol()
4273 spin_unlock_irq(&np->lock); in nv_get_wol()
4278 struct fe_priv *np = netdev_priv(dev); in nv_set_wol() local
4283 np->wolenabled = 0; in nv_set_wol()
4285 np->wolenabled = 1; in nv_set_wol()
4289 spin_lock_irq(&np->lock); in nv_set_wol()
4291 spin_unlock_irq(&np->lock); in nv_set_wol()
4293 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled); in nv_set_wol()
4300 struct fe_priv *np = netdev_priv(dev); in nv_get_link_ksettings() local
4304 spin_lock_irq(&np->lock); in nv_get_link_ksettings()
4317 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { in nv_get_link_ksettings()
4332 if (np->duplex) in nv_get_link_ksettings()
4339 cmd->base.autoneg = np->autoneg; in nv_get_link_ksettings()
4342 if (np->autoneg) { in nv_get_link_ksettings()
4344 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4353 if (np->gigabit == PHY_GIGABIT) { in nv_get_link_ksettings()
4354 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4363 if (np->gigabit == PHY_GIGABIT) in nv_get_link_ksettings()
4366 cmd->base.phy_address = np->phyaddr; in nv_get_link_ksettings()
4374 spin_unlock_irq(&np->lock); in nv_get_link_ksettings()
4381 struct fe_priv *np = netdev_priv(dev); in nv_set_link_ksettings() local
4390 if (cmd->base.phy_address != np->phyaddr) { in nv_set_link_ksettings()
4400 if (np->gigabit == PHY_GIGABIT) in nv_set_link_ksettings()
4427 spin_lock_irqsave(&np->lock, flags); in nv_set_link_ksettings()
4438 spin_unlock_irqrestore(&np->lock, flags); in nv_set_link_ksettings()
4446 np->autoneg = 1; in nv_set_link_ksettings()
4449 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4459 …if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx p… in nv_set_link_ksettings()
4461 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_set_link_ksettings()
4463 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4465 if (np->gigabit == PHY_GIGABIT) { in nv_set_link_ksettings()
4466 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4470 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4475 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4476 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { in nv_set_link_ksettings()
4486 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4491 np->autoneg = 0; in nv_set_link_ksettings()
4493 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4503 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); in nv_set_link_ksettings()
4504 …if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx p… in nv_set_link_ksettings()
4506 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; in nv_set_link_ksettings()
4508 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { in nv_set_link_ksettings()
4510 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; in nv_set_link_ksettings()
4512 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4513 np->fixed_mode = adv; in nv_set_link_ksettings()
4515 if (np->gigabit == PHY_GIGABIT) { in nv_set_link_ksettings()
4516 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4518 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4521 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4523 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) in nv_set_link_ksettings()
4525 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) in nv_set_link_ksettings()
4527 if (np->phy_oui == PHY_OUI_MARVELL) { in nv_set_link_ksettings()
4534 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4555 struct fe_priv *np = netdev_priv(dev); in nv_get_regs_len() local
4556 return np->register_size; in nv_get_regs_len()
4561 struct fe_priv *np = netdev_priv(dev); in nv_get_regs() local
4567 spin_lock_irq(&np->lock); in nv_get_regs()
4568 for (i = 0; i < np->register_size/sizeof(u32); i++) in nv_get_regs()
4570 spin_unlock_irq(&np->lock); in nv_get_regs()
4575 struct fe_priv *np = netdev_priv(dev); in nv_nway_reset() local
4578 if (np->autoneg) { in nv_nway_reset()
4586 spin_lock(&np->lock); in nv_nway_reset()
4589 spin_unlock(&np->lock); in nv_nway_reset()
4595 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4596 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { in nv_nway_reset()
4605 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4622 struct fe_priv *np = netdev_priv(dev); in nv_get_ringparam() local
4624 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; in nv_get_ringparam()
4625 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; in nv_get_ringparam()
4627 ring->rx_pending = np->rx_ring_size; in nv_get_ringparam()
4628 ring->tx_pending = np->tx_ring_size; in nv_get_ringparam()
4633 struct fe_priv *np = netdev_priv(dev); in nv_set_ringparam() local
4642 (np->desc_ver == DESC_VER_1 && in nv_set_ringparam()
4645 (np->desc_ver != DESC_VER_1 && in nv_set_ringparam()
4652 if (!nv_optimized(np)) { in nv_set_ringparam()
4653 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4659 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4671 if (!nv_optimized(np)) { in nv_set_ringparam()
4673 dma_free_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4680 dma_free_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4697 spin_lock(&np->lock); in nv_set_ringparam()
4708 np->rx_ring_size = ring->rx_pending; in nv_set_ringparam()
4709 np->tx_ring_size = ring->tx_pending; in nv_set_ringparam()
4711 if (!nv_optimized(np)) { in nv_set_ringparam()
4712 np->rx_ring.orig = (struct ring_desc *)rxtx_ring; in nv_set_ringparam()
4713 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; in nv_set_ringparam()
4715 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; in nv_set_ringparam()
4716 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; in nv_set_ringparam()
4718 np->rx_skb = (struct nv_skb_map *)rx_skbuff; in nv_set_ringparam()
4719 np->tx_skb = (struct nv_skb_map *)tx_skbuff; in nv_set_ringparam()
4720 np->ring_addr = ring_addr; in nv_set_ringparam()
4722 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); in nv_set_ringparam()
4723 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); in nv_set_ringparam()
4729 if (!np->in_shutdown) in nv_set_ringparam()
4730 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_set_ringparam()
4734 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_set_ringparam()
4736 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_set_ringparam()
4739 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_set_ringparam()
4744 spin_unlock(&np->lock); in nv_set_ringparam()
4757 struct fe_priv *np = netdev_priv(dev); in nv_get_pauseparam() local
4759 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; in nv_get_pauseparam()
4760 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; in nv_get_pauseparam()
4761 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; in nv_get_pauseparam()
4766 struct fe_priv *np = netdev_priv(dev); in nv_set_pauseparam() local
4769 if ((!np->autoneg && np->duplex == 0) || in nv_set_pauseparam()
4770 (np->autoneg && !pause->autoneg && np->duplex == 0)) { in nv_set_pauseparam()
4774 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { in nv_set_pauseparam()
4784 spin_lock(&np->lock); in nv_set_pauseparam()
4787 spin_unlock(&np->lock); in nv_set_pauseparam()
4792 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); in nv_set_pauseparam()
4794 np->pause_flags |= NV_PAUSEFRAME_RX_REQ; in nv_set_pauseparam()
4796 np->pause_flags |= NV_PAUSEFRAME_TX_REQ; in nv_set_pauseparam()
4798 if (np->autoneg && pause->autoneg) { in nv_set_pauseparam()
4799 np->pause_flags |= NV_PAUSEFRAME_AUTONEG; in nv_set_pauseparam()
4801 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4803 …if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pa… in nv_set_pauseparam()
4805 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_set_pauseparam()
4807 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4811 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4813 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4815 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); in nv_set_pauseparam()
4817 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; in nv_set_pauseparam()
4819 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; in nv_set_pauseparam()
4824 nv_update_pause(dev, np->pause_flags); in nv_set_pauseparam()
4836 struct fe_priv *np = netdev_priv(dev); in nv_set_loopback() local
4841 spin_lock_irqsave(&np->lock, flags); in nv_set_loopback()
4842 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4845 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4852 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
4855 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4865 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4871 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4877 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4882 spin_lock_irqsave(&np->lock, flags); in nv_set_loopback()
4884 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4901 struct fe_priv *np = get_nvpriv(dev); in nv_vlan_mode() local
4903 spin_lock_irq(&np->lock); in nv_vlan_mode()
4906 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP; in nv_vlan_mode()
4908 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; in nv_vlan_mode()
4911 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS; in nv_vlan_mode()
4913 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; in nv_vlan_mode()
4915 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_vlan_mode()
4917 spin_unlock_irq(&np->lock); in nv_vlan_mode()
4922 struct fe_priv *np = netdev_priv(dev); in nv_set_features() local
4934 spin_lock_irq(&np->lock); in nv_set_features()
4937 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; in nv_set_features()
4939 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; in nv_set_features()
4942 writel(np->txrxctl_bits, base + NvRegTxRxControl); in nv_set_features()
4944 spin_unlock_irq(&np->lock); in nv_set_features()
4955 struct fe_priv *np = netdev_priv(dev); in nv_get_sset_count() local
4959 if (np->driver_data & DEV_HAS_TEST_EXTENDED) in nv_get_sset_count()
4964 if (np->driver_data & DEV_HAS_STATISTICS_V3) in nv_get_sset_count()
4966 else if (np->driver_data & DEV_HAS_STATISTICS_V2) in nv_get_sset_count()
4968 else if (np->driver_data & DEV_HAS_STATISTICS_V1) in nv_get_sset_count()
4982 struct fe_priv *np = netdev_priv(dev); in nv_get_ethtool_stats() local
4984 spin_lock_bh(&np->hwstats_lock); in nv_get_ethtool_stats()
4986 memcpy(buffer, &np->estats, in nv_get_ethtool_stats()
4988 spin_unlock_bh(&np->hwstats_lock); in nv_get_ethtool_stats()
4993 struct fe_priv *np = netdev_priv(dev); in nv_link_test() local
4996 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
4997 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5036 struct fe_priv *np = netdev_priv(dev); in nv_interrupt_test() local
5049 np->intr_test = 0; in nv_interrupt_test()
5052 save_msi_flags = np->msi_flags; in nv_interrupt_test()
5053 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; in nv_interrupt_test()
5054 np->msi_flags |= 0x001; /* setup 1 vector */ in nv_interrupt_test()
5067 spin_lock_irq(&np->lock); in nv_interrupt_test()
5070 testcnt = np->intr_test; in nv_interrupt_test()
5075 if (!(np->msi_flags & NV_MSI_X_ENABLED)) in nv_interrupt_test()
5080 spin_unlock_irq(&np->lock); in nv_interrupt_test()
5084 np->msi_flags = save_msi_flags; in nv_interrupt_test()
5099 struct fe_priv *np = netdev_priv(dev); in nv_loopback_test() local
5103 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); in nv_loopback_test()
5128 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_loopback_test()
5130 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_loopback_test()
5144 test_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data, in nv_loopback_test()
5147 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_loopback_test()
5156 if (!nv_optimized(np)) { in nv_loopback_test()
5157 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); in nv_loopback_test()
5158 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); in nv_loopback_test()
5160 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); in nv_loopback_test()
5161 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); in nv_loopback_test()
5162 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); in nv_loopback_test()
5164 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_loopback_test()
5170 if (!nv_optimized(np)) { in nv_loopback_test()
5171 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); in nv_loopback_test()
5172 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); in nv_loopback_test()
5175 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); in nv_loopback_test()
5176 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); in nv_loopback_test()
5181 } else if (np->desc_ver == DESC_VER_1) { in nv_loopback_test()
5193 rx_skb = np->rx_skb[0].skb; in nv_loopback_test()
5203 dma_unmap_single(&np->pci_dev->dev, test_dma_addr, in nv_loopback_test()
5225 struct fe_priv *np = netdev_priv(dev); in nv_self_test() local
5243 spin_lock_irq(&np->lock); in nv_self_test()
5244 nv_disable_hw_interrupts(dev, np->irqmask); in nv_self_test()
5245 if (!(np->msi_flags & NV_MSI_X_ENABLED)) in nv_self_test()
5254 spin_unlock_irq(&np->lock); in nv_self_test()
5283 if (!np->in_shutdown) in nv_self_test()
5284 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_self_test()
5287 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_self_test()
5289 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_self_test()
5292 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_self_test()
5298 nv_enable_hw_interrupts(dev, np->irqmask); in nv_self_test()
5339 struct fe_priv *np = netdev_priv(dev); in nv_mgmt_acquire_sema() local
5363 np->mgmt_sema = 1; in nv_mgmt_acquire_sema()
5374 struct fe_priv *np = netdev_priv(dev); in nv_mgmt_release_sema() local
5378 if (np->driver_data & DEV_HAS_MGMT_UNIT) { in nv_mgmt_release_sema()
5379 if (np->mgmt_sema) { in nv_mgmt_release_sema()
5390 struct fe_priv *np = netdev_priv(dev); in nv_mgmt_get_version() local
5412 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; in nv_mgmt_get_version()
5419 struct fe_priv *np = netdev_priv(dev); in nv_open() local
5426 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5427 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5431 if (np->driver_data & DEV_HAS_POWER_CNTRL) in nv_open()
5444 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) in nv_open()
5456 np->in_shutdown = 0; in nv_open()
5460 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_open()
5463 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_open()
5464 if (np->desc_ver == DESC_VER_1) in nv_open()
5468 writel(np->txrxctl_bits, base + NvRegTxRxControl); in nv_open()
5469 writel(np->vlanctl_bits, base + NvRegVlanControl); in nv_open()
5471 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); in nv_open()
5485 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_open()
5491 if (np->desc_ver == DESC_VER_1) { in nv_open()
5494 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { in nv_open()
5512 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5516 if (np->wolenabled) in nv_open()
5527 nv_disable_hw_interrupts(dev, np->irqmask); in nv_open()
5537 nv_enable_hw_interrupts(dev, np->irqmask); in nv_open()
5539 spin_lock_irq(&np->lock); in nv_open()
5553 np->linkspeed = 0; in nv_open()
5566 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_open()
5569 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) in nv_open()
5570 mod_timer(&np->stats_poll, in nv_open()
5573 spin_unlock_irq(&np->lock); in nv_open()
5589 struct fe_priv *np = netdev_priv(dev); in nv_close() local
5592 spin_lock_irq(&np->lock); in nv_close()
5593 np->in_shutdown = 1; in nv_close()
5594 spin_unlock_irq(&np->lock); in nv_close()
5596 synchronize_irq(np->pci_dev->irq); in nv_close()
5598 del_timer_sync(&np->oom_kick); in nv_close()
5599 del_timer_sync(&np->nic_poll); in nv_close()
5600 del_timer_sync(&np->stats_poll); in nv_close()
5603 spin_lock_irq(&np->lock); in nv_close()
5610 nv_disable_hw_interrupts(dev, np->irqmask); in nv_close()
5613 spin_unlock_irq(&np->lock); in nv_close()
5619 if (np->wolenabled || !phy_power_down) { in nv_close()
5625 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5626 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
5672 struct fe_priv *np; in nv_probe() local
5690 np = netdev_priv(dev); in nv_probe()
5691 np->dev = dev; in nv_probe()
5692 np->pci_dev = pci_dev; in nv_probe()
5693 spin_lock_init(&np->lock); in nv_probe()
5694 spin_lock_init(&np->hwstats_lock); in nv_probe()
5696 u64_stats_init(&np->swstats_rx_syncp); in nv_probe()
5697 u64_stats_init(&np->swstats_tx_syncp); in nv_probe()
5698 np->txrx_stats = alloc_percpu(struct nv_txrx_stats); in nv_probe()
5699 if (!np->txrx_stats) { in nv_probe()
5705 timer_setup(&np->oom_kick, nv_do_rx_refill, 0); in nv_probe()
5706 timer_setup(&np->nic_poll, nv_do_nic_poll, 0); in nv_probe()
5707 timer_setup(&np->stats_poll, nv_do_stats_poll, TIMER_DEFERRABLE); in nv_probe()
5720 np->register_size = NV_PCI_REGSZ_VER3; in nv_probe()
5722 np->register_size = NV_PCI_REGSZ_VER2; in nv_probe()
5724 np->register_size = NV_PCI_REGSZ_VER1; in nv_probe()
5730 pci_resource_len(pci_dev, i) >= np->register_size) { in nv_probe()
5741 np->driver_data = id->driver_data; in nv_probe()
5743 np->device_id = id->device; in nv_probe()
5748 np->desc_ver = DESC_VER_3; in nv_probe()
5749 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; in nv_probe()
5763 np->desc_ver = DESC_VER_2; in nv_probe()
5764 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; in nv_probe()
5767 np->desc_ver = DESC_VER_1; in nv_probe()
5768 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; in nv_probe()
5771 np->pkt_limit = NV_PKTLIMIT_1; in nv_probe()
5773 np->pkt_limit = NV_PKTLIMIT_2; in nv_probe()
5776 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; in nv_probe()
5781 np->vlanctl_bits = 0; in nv_probe()
5783 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; in nv_probe()
5795 dev->max_mtu = np->pkt_limit; in nv_probe()
5797 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; in nv_probe()
5801 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; in nv_probe()
5805 np->base = ioremap(addr, np->register_size); in nv_probe()
5806 if (!np->base) in nv_probe()
5809 np->rx_ring_size = RX_RING_DEFAULT; in nv_probe()
5810 np->tx_ring_size = TX_RING_DEFAULT; in nv_probe()
5812 if (!nv_optimized(np)) { in nv_probe()
5813 np->rx_ring.orig = dma_alloc_coherent(&pci_dev->dev, in nv_probe()
5815 (np->rx_ring_size + in nv_probe()
5816 np->tx_ring_size), in nv_probe()
5817 &np->ring_addr, in nv_probe()
5819 if (!np->rx_ring.orig) in nv_probe()
5821 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; in nv_probe()
5823 np->rx_ring.ex = dma_alloc_coherent(&pci_dev->dev, in nv_probe()
5825 (np->rx_ring_size + in nv_probe()
5826 np->tx_ring_size), in nv_probe()
5827 &np->ring_addr, GFP_KERNEL); in nv_probe()
5828 if (!np->rx_ring.ex) in nv_probe()
5830 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; in nv_probe()
5832 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); in nv_probe()
5833 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); in nv_probe()
5834 if (!np->rx_skb || !np->tx_skb) in nv_probe()
5837 if (!nv_optimized(np)) in nv_probe()
5842 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); in nv_probe()
5850 np->orig_mac[0] = readl(base + NvRegMacAddrA); in nv_probe()
5851 np->orig_mac[1] = readl(base + NvRegMacAddrB); in nv_probe()
5857 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5858 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5859 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5860 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5861 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5862 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5865 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5866 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5867 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5868 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5869 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5870 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5876 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + in nv_probe()
5878 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); in nv_probe()
5881 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5882 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5883 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5884 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5885 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5886 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5911 np->wolenabled = 0; in nv_probe()
5925 if (np->desc_ver == DESC_VER_1) in nv_probe()
5926 np->tx_flags = NV_TX_VALID; in nv_probe()
5928 np->tx_flags = NV_TX2_VALID; in nv_probe()
5930 np->msi_flags = 0; in nv_probe()
5932 np->msi_flags |= NV_MSI_CAPABLE; in nv_probe()
5939 np->msi_flags |= NV_MSI_X_CAPABLE; in nv_probe()
5944 np->irqmask = NVREG_IRQMASK_CPU; in nv_probe()
5945 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ in nv_probe()
5946 np->msi_flags |= 0x0001; in nv_probe()
5950 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_probe()
5952 np->msi_flags &= ~NV_MSI_X_CAPABLE; in nv_probe()
5955 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_probe()
5956 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ in nv_probe()
5957 np->msi_flags |= 0x0003; in nv_probe()
5961 np->irqmask |= NVREG_IRQ_TIMER; in nv_probe()
5963 np->need_linktimer = 1; in nv_probe()
5964 np->link_timeout = jiffies + LINK_TIMEOUT; in nv_probe()
5966 np->need_linktimer = 0; in nv_probe()
5971 np->tx_limit = 1; in nv_probe()
5974 np->tx_limit = 0; in nv_probe()
5993 np->mac_in_use = 1; in nv_probe()
5994 if (np->mgmt_version > 0) in nv_probe()
5995 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; in nv_probe()
5997 if (np->mac_in_use && in nv_probe()
6013 spin_lock_irq(&np->lock); in nv_probe()
6015 spin_unlock_irq(&np->lock); in nv_probe()
6018 spin_lock_irq(&np->lock); in nv_probe()
6020 spin_unlock_irq(&np->lock); in nv_probe()
6024 np->phy_model = id2 & PHYID2_MODEL_MASK; in nv_probe()
6027 np->phyaddr = phyaddr; in nv_probe()
6028 np->phy_oui = id1 | id2; in nv_probe()
6031 if (np->phy_oui == PHY_OUI_REALTEK2) in nv_probe()
6032 np->phy_oui = PHY_OUI_REALTEK; in nv_probe()
6034 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) in nv_probe()
6035 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6049 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6051 np->gigabit = PHY_GIGABIT; in nv_probe()
6055 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; in nv_probe()
6056 np->duplex = 0; in nv_probe()
6057 np->autoneg = 1; in nv_probe()
6079 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6093 np->gigabit == PHY_GIGABIT ? "gbit " : "", in nv_probe()
6094 np->need_linktimer ? "lnktim " : "", in nv_probe()
6095 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", in nv_probe()
6096 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", in nv_probe()
6097 np->desc_ver); in nv_probe()
6113 free_percpu(np->txrx_stats); in nv_probe()
6122 struct fe_priv *np = netdev_priv(dev); in nv_restore_phy() local
6125 if (np->phy_oui == PHY_OUI_REALTEK && in nv_restore_phy()
6126 np->phy_model == PHY_MODEL_REALTEK_8201 && in nv_restore_phy()
6128 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6129 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6132 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6133 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6136 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6138 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()
6145 struct fe_priv *np = netdev_priv(dev); in nv_restore_mac_addr() local
6151 writel(np->orig_mac[0], base + NvRegMacAddrA); in nv_restore_mac_addr()
6152 writel(np->orig_mac[1], base + NvRegMacAddrB); in nv_restore_mac_addr()
6160 struct fe_priv *np = netdev_priv(dev); in nv_remove() local
6162 free_percpu(np->txrx_stats); in nv_remove()
6185 struct fe_priv *np = netdev_priv(dev); in nv_suspend() local
6196 for (i = 0; i <= np->register_size/sizeof(u32); i++) in nv_suspend()
6197 np->saved_config_space[i] = readl(base + i*sizeof(u32)); in nv_suspend()
6206 struct fe_priv *np = netdev_priv(dev); in nv_resume() local
6211 for (i = 0; i <= np->register_size/sizeof(u32); i++) in nv_resume()
6212 writel(np->saved_config_space[i], base+i*sizeof(u32)); in nv_resume()
6214 if (np->driver_data & DEV_NEED_MSI_FIX) in nv_resume()
6239 struct fe_priv *np = netdev_priv(dev); in nv_shutdown() local
6258 pci_wake_from_d3(pdev, np->wolenabled); in nv_shutdown()