Lines Matching refs:DESC_SIZE

394 #define DESC_SIZE	8		/* Should be cache line sized */  macro
464 			(4 * DESC_SIZE * dev->rx_info.next_rx),  in kick_rx()
523 	sg = dev->rx_info.descs + (next_empty * DESC_SIZE);  in ns83820_add_rx_skb()
534 …_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_em…  in ns83820_add_rx_skb()
595 	build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);  in clear_rx_desc()
832 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
834 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
913 		desc = info->descs + (DESC_SIZE * next_rx);
916 	info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
962 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1004 		desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1025 			__le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1035 	memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1126 	first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1129 		volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1135 		desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1456 		dev->tx_idx = txdp / (DESC_SIZE * 4);
1562 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1580 	desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1627 	memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1629 		dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1632 				  + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1942 			4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1944 			4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
2186 	pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2187 …pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_desc…
2208 	pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2210 	pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,