725 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)  in mlx4_QUERY_DEV_CAP()  argument
831 	dev_cap->flags2 = 0;  in mlx4_QUERY_DEV_CAP()
845 	dev_cap->reserved_qps = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
847 	dev_cap->max_qps = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
849 	dev_cap->reserved_srqs = 1 << (field >> 4);  in mlx4_QUERY_DEV_CAP()
851 	dev_cap->max_srqs = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
853 	dev_cap->max_cq_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
855 	dev_cap->reserved_cqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
857 	dev_cap->max_cqs = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
859 	dev_cap->max_mpts = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
861 	dev_cap->reserved_eqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
863 	dev_cap->max_eqs = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
865 	dev_cap->reserved_mtts = 1 << (field >> 4);  in mlx4_QUERY_DEV_CAP()
867 	dev_cap->reserved_mrws = 1 << (field & 0xf);  in mlx4_QUERY_DEV_CAP()
869 	dev_cap->num_sys_eqs = size & 0xfff;  in mlx4_QUERY_DEV_CAP()
871 	dev_cap->max_requester_per_qp = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
873 	dev_cap->max_responder_per_qp = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
877 		dev_cap->max_gso_sz = 0;  in mlx4_QUERY_DEV_CAP()
879 		dev_cap->max_gso_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
883 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;  in mlx4_QUERY_DEV_CAP()
885 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;  in mlx4_QUERY_DEV_CAP()
888 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;  in mlx4_QUERY_DEV_CAP()
889 		dev_cap->max_rss_tbl_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
891 		dev_cap->max_rss_tbl_sz = 0;  in mlx4_QUERY_DEV_CAP()
893 	dev_cap->max_rdma_global = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
895 	dev_cap->local_ca_ack_delay = field & 0x1f;  in mlx4_QUERY_DEV_CAP()
897 	dev_cap->num_ports = field & 0xf;  in mlx4_QUERY_DEV_CAP()
899 	dev_cap->max_msg_sz = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
902 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;  in mlx4_QUERY_DEV_CAP()
905 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;  in mlx4_QUERY_DEV_CAP()
906 	dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;  in mlx4_QUERY_DEV_CAP()
908 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;  in mlx4_QUERY_DEV_CAP()
911 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;  in mlx4_QUERY_DEV_CAP()
914 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;  in mlx4_QUERY_DEV_CAP()
916 	dev_cap->fs_max_num_qp_per_entry = field;  in mlx4_QUERY_DEV_CAP()
919 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT;  in mlx4_QUERY_DEV_CAP()
922 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;  in mlx4_QUERY_DEV_CAP()
924 	dev_cap->stat_rate_support = stat_rate;  in mlx4_QUERY_DEV_CAP()
927 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;  in mlx4_QUERY_DEV_CAP()
930 	dev_cap->flags = flags | (u64)ext_flags << 32;  in mlx4_QUERY_DEV_CAP()
932 	dev_cap->wol_port[1] = !!(field & 0x20);  in mlx4_QUERY_DEV_CAP()
933 	dev_cap->wol_port[2] = !!(field & 0x40);  in mlx4_QUERY_DEV_CAP()
935 	dev_cap->reserved_uars = field >> 4;  in mlx4_QUERY_DEV_CAP()
937 	dev_cap->uar_size = 1 << ((field & 0x3f) + 20);  in mlx4_QUERY_DEV_CAP()
939 	dev_cap->min_page_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
944 		dev_cap->bf_reg_size = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
946 		if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))  in mlx4_QUERY_DEV_CAP()
948 		dev_cap->bf_regs_per_page = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
950 		dev_cap->bf_reg_size = 0;  in mlx4_QUERY_DEV_CAP()
954 	dev_cap->max_sq_sg = field;  in mlx4_QUERY_DEV_CAP()
956 	dev_cap->max_sq_desc_sz = size;  in mlx4_QUERY_DEV_CAP()
960 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_USER_MAC_EN;  in mlx4_QUERY_DEV_CAP()
963 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP;  in mlx4_QUERY_DEV_CAP()
965 	dev_cap->max_qp_per_mcg = 1 << field;  in mlx4_QUERY_DEV_CAP()
967 	dev_cap->reserved_mgms = field & 0xf;  in mlx4_QUERY_DEV_CAP()
969 	dev_cap->max_mcgs = 1 << field;  in mlx4_QUERY_DEV_CAP()
971 	dev_cap->reserved_pds = field >> 4;  in mlx4_QUERY_DEV_CAP()
973 	dev_cap->max_pds = 1 << (field & 0x3f);  in mlx4_QUERY_DEV_CAP()
975 	dev_cap->reserved_xrcds = field >> 4;  in mlx4_QUERY_DEV_CAP()
977 	dev_cap->max_xrcds = 1 << (field & 0x1f);  in mlx4_QUERY_DEV_CAP()
980 	dev_cap->rdmarc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
982 	dev_cap->qpc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
984 	dev_cap->aux_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
986 	dev_cap->altc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
988 	dev_cap->eqc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
990 	dev_cap->cqc_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
992 	dev_cap->srq_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
994 	dev_cap->cmpt_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
996 	dev_cap->mtt_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
998 	dev_cap->dmpt_entry_sz = size;  in mlx4_QUERY_DEV_CAP()
1001 	dev_cap->max_srq_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
1003 	dev_cap->max_qp_sz = 1 << field;  in mlx4_QUERY_DEV_CAP()
1005 	dev_cap->resize_srq = field & 1;  in mlx4_QUERY_DEV_CAP()
1007 	dev_cap->max_rq_sg = field;  in mlx4_QUERY_DEV_CAP()
1009 	dev_cap->max_rq_desc_sz = size;  in mlx4_QUERY_DEV_CAP()
1012 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;  in mlx4_QUERY_DEV_CAP()
1014 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;  in mlx4_QUERY_DEV_CAP()
1016 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
1018 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;  in mlx4_QUERY_DEV_CAP()
1019 	MLX4_GET(dev_cap->bmme_flags, outbox,  in mlx4_QUERY_DEV_CAP()
1021 	if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)  in mlx4_QUERY_DEV_CAP()
1022 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;  in mlx4_QUERY_DEV_CAP()
1023 	if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)  in mlx4_QUERY_DEV_CAP()
1024 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;  in mlx4_QUERY_DEV_CAP()
1027 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;  in mlx4_QUERY_DEV_CAP()
1029 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;  in mlx4_QUERY_DEV_CAP()
1032 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;  in mlx4_QUERY_DEV_CAP()
1034 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;  in mlx4_QUERY_DEV_CAP()
1036 	MLX4_GET(dev_cap->reserved_lkey, outbox,  in mlx4_QUERY_DEV_CAP()
1040 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;  in mlx4_QUERY_DEV_CAP()
1042 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;  in mlx4_QUERY_DEV_CAP()
1044 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW;  in mlx4_QUERY_DEV_CAP()
1047 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT;  in mlx4_QUERY_DEV_CAP()
1050 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;  in mlx4_QUERY_DEV_CAP()
1053 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;  in mlx4_QUERY_DEV_CAP()
1055 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;  in mlx4_QUERY_DEV_CAP()
1056 	MLX4_GET(dev_cap->max_icm_sz, outbox,  in mlx4_QUERY_DEV_CAP()
1058 	if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)  in mlx4_QUERY_DEV_CAP()
1059 		MLX4_GET(dev_cap->max_counters, outbox,  in mlx4_QUERY_DEV_CAP()
1065 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;  in mlx4_QUERY_DEV_CAP()
1067 	MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,  in mlx4_QUERY_DEV_CAP()
1069 	dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;  in mlx4_QUERY_DEV_CAP()
1070 	MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,  in mlx4_QUERY_DEV_CAP()
1072 	dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;  in mlx4_QUERY_DEV_CAP()
1075 	dev_cap->rl_caps.num_rates = size;  in mlx4_QUERY_DEV_CAP()
1076 	if (dev_cap->rl_caps.num_rates) {  in mlx4_QUERY_DEV_CAP()
1077 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;  in mlx4_QUERY_DEV_CAP()
1079 		dev_cap->rl_caps.max_val  = size & 0xfff;  in mlx4_QUERY_DEV_CAP()
1080 		dev_cap->rl_caps.max_unit = size >> 14;  in mlx4_QUERY_DEV_CAP()
1082 		dev_cap->rl_caps.min_val  = size & 0xfff;  in mlx4_QUERY_DEV_CAP()
1083 		dev_cap->rl_caps.min_unit = size >> 14;  in mlx4_QUERY_DEV_CAP()
1086 	MLX4_GET(dev_cap->health_buffer_addrs, outbox,  in mlx4_QUERY_DEV_CAP()
1091 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;  in mlx4_QUERY_DEV_CAP()
1093 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;  in mlx4_QUERY_DEV_CAP()
1095 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;  in mlx4_QUERY_DEV_CAP()
1097 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;  in mlx4_QUERY_DEV_CAP()
1099 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;  in mlx4_QUERY_DEV_CAP()
1101 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;  in mlx4_QUERY_DEV_CAP()
1103 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SW_CQ_INIT;  in mlx4_QUERY_DEV_CAP()
1105 	for (i = 1; i <= dev_cap->num_ports; i++) {  in mlx4_QUERY_DEV_CAP()
1106 		err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);  in mlx4_QUERY_DEV_CAP()
1116 	if (dev_cap->num_sys_eqs == 0)  in mlx4_QUERY_DEV_CAP()
1117 		dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,  in mlx4_QUERY_DEV_CAP()
1118 					    dev_cap->reserved_eqs);  in mlx4_QUERY_DEV_CAP()
1120 		dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;  in mlx4_QUERY_DEV_CAP()
1127 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)  in mlx4_dev_cap_dump()  argument
1129 	if (dev_cap->bf_reg_size > 0)  in mlx4_dev_cap_dump()
1131 			 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);  in mlx4_dev_cap_dump()
1136 		 dev_cap->bmme_flags, dev_cap->reserved_lkey);  in mlx4_dev_cap_dump()
1138 		 (unsigned long long) dev_cap->max_icm_sz >> 20);  in mlx4_dev_cap_dump()
1140 		 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);  in mlx4_dev_cap_dump()
1142 		 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);  in mlx4_dev_cap_dump()
1144 		 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);  in mlx4_dev_cap_dump()
1146 		 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,  in mlx4_dev_cap_dump()
1147 		 dev_cap->eqc_entry_sz);  in mlx4_dev_cap_dump()
1149 		 dev_cap->reserved_mrws, dev_cap->reserved_mtts);  in mlx4_dev_cap_dump()
1151 		 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);  in mlx4_dev_cap_dump()
1153 		 dev_cap->max_pds, dev_cap->reserved_mgms);  in mlx4_dev_cap_dump()
1155 		 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);  in mlx4_dev_cap_dump()
1157 		 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,  in mlx4_dev_cap_dump()
1158 		 dev_cap->port_cap[1].max_port_width);  in mlx4_dev_cap_dump()
1160 		 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);  in mlx4_dev_cap_dump()
1162 		 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);  in mlx4_dev_cap_dump()
1163 	mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);  in mlx4_dev_cap_dump()
1164 	mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);  in mlx4_dev_cap_dump()
1165 	mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);  in mlx4_dev_cap_dump()
1167 		 dev_cap->dmfs_high_rate_qpn_base);  in mlx4_dev_cap_dump()
1169 		 dev_cap->dmfs_high_rate_qpn_range);  in mlx4_dev_cap_dump()
1171 	if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {  in mlx4_dev_cap_dump()
1172 		struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;  in mlx4_dev_cap_dump()
1179 	dump_dev_cap_flags(dev, dev_cap->flags);  in mlx4_dev_cap_dump()
1180 	dump_dev_cap_flags2(dev, dev_cap->flags2);  in mlx4_dev_cap_dump()