58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)  in mtk_w32()  function
92 	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |  in _mtk_mdio_write()
110 	mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |  in _mtk_mdio_read()
170 	mtk_w32(eth, val, INTF_MODE);  in mtk_gmac0_rgmii_adjust()
183 	mtk_w32(eth, val, TRGMII_RCK_CTRL);  in mtk_gmac0_rgmii_adjust()
187 	mtk_w32(eth, val, TRGMII_TCK_CTRL);  in mtk_gmac0_rgmii_adjust()
350 		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));  in mtk_mac_config()
414 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));  in mtk_mac_link_down()
426 	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));  in mtk_mac_link_up()
575 	mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg);  in mtk_tx_irq_disable()
586 	mtk_w32(eth, val | mask, eth->tx_int_mask_reg);  in mtk_tx_irq_enable()
597 	mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);  in mtk_rx_irq_disable()
608 	mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);  in mtk_rx_irq_enable()
627 		mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],  in mtk_set_mac_address()
629 		mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |  in mtk_set_mac_address()
633 		mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],  in mtk_set_mac_address()
635 		mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |  in mtk_set_mac_address()
791 	mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);  in mtk_init_fq_dma()
792 	mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);  in mtk_init_fq_dma()
793 	mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);  in mtk_init_fq_dma()
794 	mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);  in mtk_init_fq_dma()
1022 			mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);  in mtk_tx_map()
1026 		mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);  in mtk_tx_map()
1191 		mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);  in mtk_update_rx_cpu_idx()
1197 				mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);  in mtk_update_rx_cpu_idx()
1362 	mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);  in mtk_poll_tx_qdma()
1440 		mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),  in mtk_handle_status_irq()
1453 	mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg);  in mtk_napi_tx()
1487 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);  in mtk_napi_rx()
1563 		mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);  in mtk_tx_alloc()
1564 		mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);  in mtk_tx_alloc()
1565 		mtk_w32(eth,  in mtk_tx_alloc()
1568 		mtk_w32(eth,  in mtk_tx_alloc()
1571 		mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,  in mtk_tx_alloc()
1574 		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);  in mtk_tx_alloc()
1575 		mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0);  in mtk_tx_alloc()
1576 		mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);  in mtk_tx_alloc()
1577 		mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX);  in mtk_tx_alloc()
1681 	mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);  in mtk_rx_alloc()
1682 	mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);  in mtk_rx_alloc()
1683 	mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);  in mtk_rx_alloc()
1684 	mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);  in mtk_rx_alloc()
1742 		mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));  in mtk_hwlro_rx_init()
1743 		mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));  in mtk_hwlro_rx_init()
1744 		mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));  in mtk_hwlro_rx_init()
1754 	mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);  in mtk_hwlro_rx_init()
1757 	mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);  in mtk_hwlro_rx_init()
1760 	mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,  in mtk_hwlro_rx_init()
1772 	mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);  in mtk_hwlro_rx_init()
1773 	mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);  in mtk_hwlro_rx_init()
1784 	mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);  in mtk_hwlro_rx_uninit()
1798 		mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));  in mtk_hwlro_rx_uninit()
1801 	mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);  in mtk_hwlro_rx_uninit()
1811 	mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));  in mtk_hwlro_val_ipaddr()
1813 	mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));  in mtk_hwlro_val_ipaddr()
1816 	mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));  in mtk_hwlro_val_ipaddr()
1826 	mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));  in mtk_hwlro_inval_ipaddr()
1828 	mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));  in mtk_hwlro_inval_ipaddr()
2050 		mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN |  in mtk_dma_init()
2052 		mtk_w32(eth, 0x0, MTK_QDMA_HRED2);  in mtk_dma_init()
2163 		mtk_w32(eth,  in mtk_start_dma()
2170 		mtk_w32(eth,  in mtk_start_dma()
2175 		mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN |  in mtk_start_dma()
2225 	mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),  in mtk_stop_dma()
2331 		mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);  in mtk_hw_init()
2360 		mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i));  in mtk_hw_init()
2366 	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);  in mtk_hw_init()
2369 	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);  in mtk_hw_init()
2372 	mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);  in mtk_hw_init()
2375 	mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);  in mtk_hw_init()
2378 	mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);  in mtk_hw_init()
2379 	mtk_w32(eth, 0, MTK_RST_GL);  in mtk_hw_init()
2382 	mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);  in mtk_hw_init()
2383 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);  in mtk_hw_init()
2384 	mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);  in mtk_hw_init()
2385 	mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);  in mtk_hw_init()
2386 	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);  in mtk_hw_init()
2398 		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));  in mtk_hw_init()