Lines Matching full:hw
96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
100 static void yukon_init(struct skge_hw *hw, int port);
101 static void genesis_mac_init(struct skge_hw *hw, int port);
114 static inline bool is_genesis(const struct skge_hw *hw) in is_genesis() argument
117 return hw->chip_id == CHIP_ID_GENESIS; in is_genesis()
137 const void __iomem *io = skge->hw->regs; in skge_get_regs()
150 static u32 wol_supported(const struct skge_hw *hw) in wol_supported() argument
152 if (is_genesis(hw)) in wol_supported()
155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in wol_supported()
163 struct skge_hw *hw = skge->hw; in skge_wol_init() local
167 skge_write16(hw, B0_CTST, CS_RST_CLR); in skge_wol_init()
168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_wol_init()
171 skge_write8(hw, B0_POWER_CTRL, in skge_wol_init()
175 if (hw->chip_id == CHIP_ID_YUKON_LITE && in skge_wol_init()
176 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in skge_wol_init()
177 u32 reg = skge_read32(hw, B2_GP_IO); in skge_wol_init()
180 skge_write32(hw, B2_GP_IO, reg); in skge_wol_init()
183 skge_write32(hw, SK_REG(port, GPHY_CTRL), in skge_wol_init()
188 skge_write32(hw, SK_REG(port, GPHY_CTRL), in skge_wol_init()
193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); in skge_wol_init()
196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, in skge_wol_init()
200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); in skge_wol_init()
201 gm_phy_write(hw, port, PHY_MARV_CTRL, in skge_wol_init()
207 gma_write16(hw, port, GM_GP_CTRL, in skge_wol_init()
212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), in skge_wol_init()
216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); in skge_wol_init()
229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); in skge_wol_init()
232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_wol_init()
239 wol->supported = wol_supported(skge->hw); in skge_get_wol()
246 struct skge_hw *hw = skge->hw; in skge_set_wol() local
248 if ((wol->wolopts & ~wol_supported(hw)) || in skge_set_wol()
249 !device_can_wakeup(&hw->pdev->dev)) in skge_set_wol()
254 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); in skge_set_wol()
262 static u32 skge_supported_modes(const struct skge_hw *hw) in skge_supported_modes() argument
266 if (hw->copper) { in skge_supported_modes()
276 if (is_genesis(hw)) in skge_supported_modes()
282 else if (hw->chip_id == CHIP_ID_YUKON) in skge_supported_modes()
297 struct skge_hw *hw = skge->hw; in skge_get_link_ksettings() local
300 supported = skge_supported_modes(hw); in skge_get_link_ksettings()
302 if (hw->copper) { in skge_get_link_ksettings()
304 cmd->base.phy_address = hw->phy_addr; in skge_get_link_ksettings()
325 const struct skge_hw *hw = skge->hw; in skge_set_link_ksettings() local
326 u32 supported = skge_supported_modes(hw); in skge_set_link_ksettings()
400 strlcpy(info->bus_info, pci_name(skge->hw->pdev), in skge_get_drvinfo()
450 if (is_genesis(skge->hw)) in skge_get_ethtool_stats()
465 if (is_genesis(skge->hw)) in skge_get_stats()
600 static inline u32 hwkhz(const struct skge_hw *hw) in hwkhz() argument
602 return is_genesis(hw) ? 53125 : 78125; in hwkhz()
606 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) in skge_clk2usec() argument
608 return (ticks * 1000) / hwkhz(hw); in skge_clk2usec()
612 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) in skge_usecs2clk() argument
614 return hwkhz(hw) * usec / 1000; in skge_usecs2clk()
621 struct skge_hw *hw = skge->hw; in skge_get_coalesce() local
627 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { in skge_get_coalesce()
628 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); in skge_get_coalesce()
629 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_get_coalesce()
645 struct skge_hw *hw = skge->hw; in skge_set_coalesce() local
647 u32 msk = skge_read32(hw, B2_IRQM_MSK); in skge_set_coalesce()
670 skge_write32(hw, B2_IRQM_MSK, msk); in skge_set_coalesce()
672 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); in skge_set_coalesce()
674 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); in skge_set_coalesce()
675 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_set_coalesce()
683 struct skge_hw *hw = skge->hw; in skge_led() local
686 spin_lock_bh(&hw->phy_lock); in skge_led()
687 if (is_genesis(hw)) { in skge_led()
690 if (hw->phy_type == SK_PHY_BCOM) in skge_led()
691 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); in skge_led()
693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); in skge_led()
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); in skge_led()
696 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); in skge_led()
697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); in skge_led()
698 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); in skge_led()
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); in skge_led()
703 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); in skge_led()
705 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
706 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
711 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); in skge_led()
712 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); in skge_led()
713 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); in skge_led()
715 if (hw->phy_type == SK_PHY_BCOM) in skge_led()
716 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); in skge_led()
718 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); in skge_led()
719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); in skge_led()
720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); in skge_led()
727 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
728 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, in skge_led()
742 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
748 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); in skge_led()
749 gm_phy_write(hw, port, PHY_MARV_LED_OVER, in skge_led()
757 spin_unlock_bh(&hw->phy_lock); in skge_led()
791 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); in skge_get_eeprom_len()
824 struct pci_dev *pdev = skge->hw->pdev; in skge_get_eeprom()
850 struct pci_dev *pdev = skge->hw->pdev; in skge_set_eeprom()
941 map = pci_map_single(skge->hw->pdev, skb->data, bufsize, in skge_rx_setup()
944 if (pci_dma_mapping_error(skge->hw->pdev, map)) in skge_rx_setup()
983 struct skge_hw *hw = skge->hw; in skge_rx_clean() local
992 pci_unmap_single(hw->pdev, in skge_rx_clean()
1051 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), in skge_link_up()
1066 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); in skge_link_down()
1073 static void xm_link_down(struct skge_hw *hw, int port) in xm_link_down() argument
1075 struct net_device *dev = hw->dev[port]; in xm_link_down()
1078 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); in xm_link_down()
1084 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __xm_phy_read() argument
1088 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in __xm_phy_read()
1089 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
1091 if (hw->phy_type == SK_PHY_XMAC) in __xm_phy_read()
1095 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) in __xm_phy_read()
1102 *val = xm_read16(hw, port, XM_PHY_DATA); in __xm_phy_read()
1107 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) in xm_phy_read() argument
1110 if (__xm_phy_read(hw, port, reg, &v)) in xm_phy_read()
1111 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); in xm_phy_read()
1115 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in xm_phy_write() argument
1119 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); in xm_phy_write()
1121 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
1128 xm_write16(hw, port, XM_PHY_DATA, val); in xm_phy_write()
1130 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) in xm_phy_write()
1137 static void genesis_init(struct skge_hw *hw) in genesis_init() argument
1140 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); in genesis_init()
1141 skge_write8(hw, B2_BSC_CTRL, BSC_START); in genesis_init()
1144 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_init()
1147 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); in genesis_init()
1148 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); in genesis_init()
1149 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); in genesis_init()
1150 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); in genesis_init()
1152 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_init()
1153 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_init()
1154 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_init()
1155 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_init()
1158 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); in genesis_init()
1159 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); in genesis_init()
1160 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); in genesis_init()
1161 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); in genesis_init()
1162 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); in genesis_init()
1165 static void genesis_reset(struct skge_hw *hw, int port) in genesis_reset() argument
1170 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in genesis_reset()
1173 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); in genesis_reset()
1174 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); in genesis_reset()
1175 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ in genesis_reset()
1176 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ in genesis_reset()
1177 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ in genesis_reset()
1180 if (hw->phy_type == SK_PHY_BCOM) in genesis_reset()
1181 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); in genesis_reset()
1183 xm_outhash(hw, port, XM_HSM, zero); in genesis_reset()
1186 reg = xm_read32(hw, port, XM_MODE); in genesis_reset()
1187 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); in genesis_reset()
1188 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); in genesis_reset()
1209 static void bcom_check_link(struct skge_hw *hw, int port) in bcom_check_link() argument
1211 struct net_device *dev = hw->dev[port]; in bcom_check_link()
1216 xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
1217 status = xm_phy_read(hw, port, PHY_BCOM_STAT); in bcom_check_link()
1220 xm_link_down(hw, port); in bcom_check_link()
1230 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); in bcom_check_link()
1236 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); in bcom_check_link()
1277 struct skge_hw *hw = skge->hw; in bcom_phy_init() local
1297 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); in bcom_phy_init()
1300 r = xm_read16(hw, port, XM_MMU_CMD); in bcom_phy_init()
1302 xm_write16(hw, port, XM_MMU_CMD, r); in bcom_phy_init()
1311 xm_phy_write(hw, port, in bcom_phy_init()
1321 xm_phy_write(hw, port, in bcom_phy_init()
1330 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); in bcom_phy_init()
1332 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); in bcom_phy_init()
1335 xm_read16(hw, port, XM_ISRC); in bcom_phy_init()
1351 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); in bcom_phy_init()
1358 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); in bcom_phy_init()
1362 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, in bcom_phy_init()
1366 if (hw->dev[port]->mtu > ETH_DATA_LEN) { in bcom_phy_init()
1367 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in bcom_phy_init()
1374 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); in bcom_phy_init()
1375 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); in bcom_phy_init()
1378 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in bcom_phy_init()
1383 struct skge_hw *hw = skge->hw; in xm_phy_init() local
1395 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); in xm_phy_init()
1409 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); in xm_phy_init()
1418 struct skge_hw *hw = skge->hw; in xm_check_link() local
1423 xm_phy_read(hw, port, PHY_XMAC_STAT); in xm_check_link()
1424 status = xm_phy_read(hw, port, PHY_XMAC_STAT); in xm_check_link()
1427 xm_link_down(hw, port); in xm_check_link()
1437 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); in xm_check_link()
1443 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); in xm_check_link()
1492 struct skge_hw *hw = skge->hw; in xm_link_timer() local
1500 spin_lock_irqsave(&hw->phy_lock, flags); in xm_link_timer()
1507 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) in xm_link_timer()
1513 u16 msk = xm_read16(hw, port, XM_IMSK); in xm_link_timer()
1515 xm_write16(hw, port, XM_IMSK, msk); in xm_link_timer()
1516 xm_read16(hw, port, XM_ISRC); in xm_link_timer()
1522 spin_unlock_irqrestore(&hw->phy_lock, flags); in xm_link_timer()
1525 static void genesis_mac_init(struct skge_hw *hw, int port) in genesis_mac_init() argument
1527 struct net_device *dev = hw->dev[port]; in genesis_mac_init()
1529 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; in genesis_mac_init()
1535 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in genesis_mac_init()
1537 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) in genesis_mac_init()
1546 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_mac_init()
1553 if (hw->phy_type != SK_PHY_XMAC) { in genesis_mac_init()
1555 r = skge_read32(hw, B2_GP_IO); in genesis_mac_init()
1561 skge_write32(hw, B2_GP_IO, r); in genesis_mac_init()
1564 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); in genesis_mac_init()
1568 switch (hw->phy_type) { in genesis_mac_init()
1574 bcom_check_link(hw, port); in genesis_mac_init()
1578 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in genesis_mac_init()
1582 xm_outaddr(hw, port, XM_EXM(i), zero); in genesis_mac_init()
1585 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1588 xm_write16(hw, port, XM_STAT_CMD, in genesis_mac_init()
1592 xm_write16(hw, port, XM_RX_HI_WM, 1450); in genesis_mac_init()
1607 xm_write16(hw, port, XM_RX_CMD, r); in genesis_mac_init()
1610 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); in genesis_mac_init()
1613 if (hw->ports > 1 && jumbo) in genesis_mac_init()
1614 xm_write16(hw, port, XM_TX_THR, 1020); in genesis_mac_init()
1616 xm_write16(hw, port, XM_TX_THR, 512); in genesis_mac_init()
1632 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); in genesis_mac_init()
1640 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); in genesis_mac_init()
1647 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); in genesis_mac_init()
1650 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); in genesis_mac_init()
1653 skge_write8(hw, B3_MA_TOINI_RX1, 72); in genesis_mac_init()
1654 skge_write8(hw, B3_MA_TOINI_RX2, 72); in genesis_mac_init()
1655 skge_write8(hw, B3_MA_TOINI_TX1, 72); in genesis_mac_init()
1656 skge_write8(hw, B3_MA_TOINI_TX2, 72); in genesis_mac_init()
1658 skge_write8(hw, B3_MA_RCINI_RX1, 0); in genesis_mac_init()
1659 skge_write8(hw, B3_MA_RCINI_RX2, 0); in genesis_mac_init()
1660 skge_write8(hw, B3_MA_RCINI_TX1, 0); in genesis_mac_init()
1661 skge_write8(hw, B3_MA_RCINI_TX2, 0); in genesis_mac_init()
1664 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1665 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); in genesis_mac_init()
1666 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1669 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); in genesis_mac_init()
1670 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); in genesis_mac_init()
1671 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); in genesis_mac_init()
1675 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); in genesis_mac_init()
1678 skge_write16(hw, B3_PA_CTRL, in genesis_mac_init()
1685 struct skge_hw *hw = skge->hw; in genesis_stop() local
1691 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1693 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_stop()
1695 genesis_reset(hw, port); in genesis_stop()
1698 skge_write16(hw, B3_PA_CTRL, in genesis_stop()
1702 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); in genesis_stop()
1704 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); in genesis_stop()
1705 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) in genesis_stop()
1710 if (hw->phy_type != SK_PHY_XMAC) { in genesis_stop()
1711 u32 reg = skge_read32(hw, B2_GP_IO); in genesis_stop()
1719 skge_write32(hw, B2_GP_IO, reg); in genesis_stop()
1720 skge_read32(hw, B2_GP_IO); in genesis_stop()
1723 xm_write16(hw, port, XM_MMU_CMD, in genesis_stop()
1724 xm_read16(hw, port, XM_MMU_CMD) in genesis_stop()
1727 xm_read16(hw, port, XM_MMU_CMD); in genesis_stop()
1733 struct skge_hw *hw = skge->hw; in genesis_get_stats() local
1738 xm_write16(hw, port, in genesis_get_stats()
1742 while (xm_read16(hw, port, XM_STAT_CMD) in genesis_get_stats()
1750 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 in genesis_get_stats()
1751 | xm_read32(hw, port, XM_TXO_OK_LO); in genesis_get_stats()
1752 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 in genesis_get_stats()
1753 | xm_read32(hw, port, XM_RXO_OK_LO); in genesis_get_stats()
1756 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); in genesis_get_stats()
1759 static void genesis_mac_intr(struct skge_hw *hw, int port) in genesis_mac_intr() argument
1761 struct net_device *dev = hw->dev[port]; in genesis_mac_intr()
1763 u16 status = xm_read16(hw, port, XM_ISRC); in genesis_mac_intr()
1768 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { in genesis_mac_intr()
1769 xm_link_down(hw, port); in genesis_mac_intr()
1774 xm_write32(hw, port, XM_MODE, XM_MD_FTF); in genesis_mac_intr()
1781 struct skge_hw *hw = skge->hw; in genesis_link_up() local
1786 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1800 xm_write16(hw, port, XM_MMU_CMD, cmd); in genesis_link_up()
1802 mode = xm_read32(hw, port, XM_MODE); in genesis_link_up()
1816 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); in genesis_link_up()
1819 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); in genesis_link_up()
1828 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); in genesis_link_up()
1831 xm_write32(hw, port, XM_MODE, mode); in genesis_link_up()
1834 msk = xm_read16(hw, port, XM_IMSK); in genesis_link_up()
1836 xm_write16(hw, port, XM_IMSK, msk); in genesis_link_up()
1838 xm_read16(hw, port, XM_ISRC); in genesis_link_up()
1841 cmd = xm_read16(hw, port, XM_MMU_CMD); in genesis_link_up()
1842 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) in genesis_link_up()
1849 if (hw->phy_type == SK_PHY_BCOM) { in genesis_link_up()
1850 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, in genesis_link_up()
1851 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) in genesis_link_up()
1853 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); in genesis_link_up()
1857 xm_write16(hw, port, XM_MMU_CMD, in genesis_link_up()
1865 struct skge_hw *hw = skge->hw; in bcom_phy_intr() local
1869 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); in bcom_phy_intr()
1875 hw->dev[port]->name); in bcom_phy_intr()
1881 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); in bcom_phy_intr()
1882 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1884 xm_phy_write(hw, port, PHY_BCOM_CTRL, in bcom_phy_intr()
1889 bcom_check_link(hw, port); in bcom_phy_intr()
1893 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) in gm_phy_write() argument
1897 gma_write16(hw, port, GM_SMI_DATA, val); in gm_phy_write()
1898 gma_write16(hw, port, GM_SMI_CTRL, in gm_phy_write()
1899 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); in gm_phy_write()
1903 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) in gm_phy_write()
1907 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); in gm_phy_write()
1911 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) in __gm_phy_read() argument
1915 gma_write16(hw, port, GM_SMI_CTRL, in __gm_phy_read()
1916 GM_SMI_CT_PHY_AD(hw->phy_addr) in __gm_phy_read()
1921 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) in __gm_phy_read()
1927 *val = gma_read16(hw, port, GM_SMI_DATA); in __gm_phy_read()
1931 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) in gm_phy_read() argument
1934 if (__gm_phy_read(hw, port, reg, &v)) in gm_phy_read()
1935 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); in gm_phy_read()
1940 static void yukon_init(struct skge_hw *hw, int port) in yukon_init() argument
1942 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_init()
1946 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); in yukon_init()
1954 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); in yukon_init()
1957 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_init()
1962 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
1969 if (hw->copper) { in yukon_init()
2015 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); in yukon_init()
2017 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); in yukon_init()
2018 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_init()
2022 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); in yukon_init()
2024 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_init()
2027 static void yukon_reset(struct skge_hw *hw, int port) in yukon_reset() argument
2029 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ in yukon_reset()
2030 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ in yukon_reset()
2031 gma_write16(hw, port, GM_MC_ADDR_H2, 0); in yukon_reset()
2032 gma_write16(hw, port, GM_MC_ADDR_H3, 0); in yukon_reset()
2033 gma_write16(hw, port, GM_MC_ADDR_H4, 0); in yukon_reset()
2035 gma_write16(hw, port, GM_RX_CTRL, in yukon_reset()
2036 gma_read16(hw, port, GM_RX_CTRL) in yukon_reset()
2041 static int is_yukon_lite_a0(struct skge_hw *hw) in is_yukon_lite_a0() argument
2046 if (hw->chip_id != CHIP_ID_YUKON) in is_yukon_lite_a0()
2049 reg = skge_read32(hw, B2_FAR); in is_yukon_lite_a0()
2050 skge_write8(hw, B2_FAR + 3, 0xff); in is_yukon_lite_a0()
2051 ret = (skge_read8(hw, B2_FAR + 3) != 0); in is_yukon_lite_a0()
2052 skge_write32(hw, B2_FAR, reg); in is_yukon_lite_a0()
2056 static void yukon_mac_init(struct skge_hw *hw, int port) in yukon_mac_init() argument
2058 struct skge_port *skge = netdev_priv(hw->dev[port]); in yukon_mac_init()
2061 const u8 *addr = hw->dev[port]->dev_addr; in yukon_mac_init()
2064 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
2065 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
2066 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
2068 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
2072 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_mac_init()
2073 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_mac_init()
2076 if (hw->chip_id == CHIP_ID_YUKON_LITE && in yukon_mac_init()
2077 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { in yukon_mac_init()
2078 reg = skge_read32(hw, B2_GP_IO); in yukon_mac_init()
2081 skge_write32(hw, B2_GP_IO, reg); in yukon_mac_init()
2087 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; in yukon_mac_init()
2090 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); in yukon_mac_init()
2091 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); in yukon_mac_init()
2092 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); in yukon_mac_init()
2096 gma_write16(hw, port, GM_GP_CTRL, in yukon_mac_init()
2097 gma_read16(hw, port, GM_GP_CTRL) | reg); in yukon_mac_init()
2120 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_mac_init()
2133 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_mac_init()
2134 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_init()
2136 yukon_init(hw, port); in yukon_mac_init()
2139 reg = gma_read16(hw, port, GM_PHY_ADDR); in yukon_mac_init()
2140 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); in yukon_mac_init()
2143 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); in yukon_mac_init()
2144 gma_write16(hw, port, GM_PHY_ADDR, reg); in yukon_mac_init()
2147 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); in yukon_mac_init()
2150 gma_write16(hw, port, GM_RX_CTRL, in yukon_mac_init()
2154 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); in yukon_mac_init()
2157 gma_write16(hw, port, GM_TX_PARAM, in yukon_mac_init()
2167 if (hw->dev[port]->mtu > ETH_DATA_LEN) in yukon_mac_init()
2170 gma_write16(hw, port, GM_SERIAL_MODE, reg); in yukon_mac_init()
2173 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); in yukon_mac_init()
2175 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); in yukon_mac_init()
2178 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); in yukon_mac_init()
2179 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); in yukon_mac_init()
2180 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); in yukon_mac_init()
2185 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); in yukon_mac_init()
2189 if (is_yukon_lite_a0(hw)) in yukon_mac_init()
2192 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
2193 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); in yukon_mac_init()
2199 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); in yukon_mac_init()
2202 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); in yukon_mac_init()
2203 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); in yukon_mac_init()
2207 static void yukon_suspend(struct skge_hw *hw, int port) in yukon_suspend() argument
2211 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); in yukon_suspend()
2213 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); in yukon_suspend()
2215 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
2217 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
2220 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); in yukon_suspend()
2222 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); in yukon_suspend()
2227 struct skge_hw *hw = skge->hw; in yukon_stop() local
2230 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); in yukon_stop()
2231 yukon_reset(hw, port); in yukon_stop()
2233 gma_write16(hw, port, GM_GP_CTRL, in yukon_stop()
2234 gma_read16(hw, port, GM_GP_CTRL) in yukon_stop()
2236 gma_read16(hw, port, GM_GP_CTRL); in yukon_stop()
2238 yukon_suspend(hw, port); in yukon_stop()
2241 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); in yukon_stop()
2242 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); in yukon_stop()
2247 struct skge_hw *hw = skge->hw; in yukon_get_stats() local
2251 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 in yukon_get_stats()
2252 | gma_read32(hw, port, GM_TXO_OK_LO); in yukon_get_stats()
2253 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 in yukon_get_stats()
2254 | gma_read32(hw, port, GM_RXO_OK_LO); in yukon_get_stats()
2257 data[i] = gma_read32(hw, port, in yukon_get_stats()
2261 static void yukon_mac_intr(struct skge_hw *hw, int port) in yukon_mac_intr() argument
2263 struct net_device *dev = hw->dev[port]; in yukon_mac_intr()
2265 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); in yukon_mac_intr()
2272 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); in yukon_mac_intr()
2277 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); in yukon_mac_intr()
2282 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) in yukon_speed() argument
2296 struct skge_hw *hw = skge->hw; in yukon_link_up() local
2301 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); in yukon_link_up()
2303 reg = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_up()
2309 gma_write16(hw, port, GM_GP_CTRL, reg); in yukon_link_up()
2311 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); in yukon_link_up()
2317 struct skge_hw *hw = skge->hw; in yukon_link_down() local
2321 ctrl = gma_read16(hw, port, GM_GP_CTRL); in yukon_link_down()
2323 gma_write16(hw, port, GM_GP_CTRL, ctrl); in yukon_link_down()
2326 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); in yukon_link_down()
2329 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); in yukon_link_down()
2334 yukon_init(hw, port); in yukon_link_down()
2339 struct skge_hw *hw = skge->hw; in yukon_phy_intr() local
2344 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); in yukon_phy_intr()
2345 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); in yukon_phy_intr()
2351 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) in yukon_phy_intr()
2357 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { in yukon_phy_intr()
2369 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2388 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); in yukon_phy_intr()
2390 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); in yukon_phy_intr()
2396 skge->speed = yukon_speed(hw, phystat); in yukon_phy_intr()
2415 struct skge_hw *hw = skge->hw; in skge_phy_reset() local
2417 struct net_device *dev = hw->dev[port]; in skge_phy_reset()
2422 spin_lock_bh(&hw->phy_lock); in skge_phy_reset()
2423 if (is_genesis(hw)) { in skge_phy_reset()
2424 genesis_reset(hw, port); in skge_phy_reset()
2425 genesis_mac_init(hw, port); in skge_phy_reset()
2427 yukon_reset(hw, port); in skge_phy_reset()
2428 yukon_init(hw, port); in skge_phy_reset()
2430 spin_unlock_bh(&hw->phy_lock); in skge_phy_reset()
2440 struct skge_hw *hw = skge->hw; in skge_ioctl() local
2448 data->phy_id = hw->phy_addr; in skge_ioctl()
2453 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2455 if (is_genesis(hw)) in skge_ioctl()
2456 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2458 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); in skge_ioctl()
2459 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2465 spin_lock_bh(&hw->phy_lock); in skge_ioctl()
2466 if (is_genesis(hw)) in skge_ioctl()
2467 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2470 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, in skge_ioctl()
2472 spin_unlock_bh(&hw->phy_lock); in skge_ioctl()
2478 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) in skge_ramset() argument
2486 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); in skge_ramset()
2487 skge_write32(hw, RB_ADDR(q, RB_START), start); in skge_ramset()
2488 skge_write32(hw, RB_ADDR(q, RB_WP), start); in skge_ramset()
2489 skge_write32(hw, RB_ADDR(q, RB_RP), start); in skge_ramset()
2490 skge_write32(hw, RB_ADDR(q, RB_END), end); in skge_ramset()
2494 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), in skge_ramset()
2496 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), in skge_ramset()
2502 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); in skge_ramset()
2505 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); in skge_ramset()
2512 struct skge_hw *hw = skge->hw; in skge_qset() local
2517 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) in skge_qset()
2520 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); in skge_qset()
2521 skge_write32(hw, Q_ADDR(q, Q_F), watermark); in skge_qset()
2522 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); in skge_qset()
2523 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); in skge_qset()
2529 struct skge_hw *hw = skge->hw; in skge_up() local
2549 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); in skge_up()
2556 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n"); in skge_up()
2574 if (hw->ports == 1) { in skge_up()
2575 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, in skge_up()
2576 dev->name, hw); in skge_up()
2579 hw->pdev->irq, err); in skge_up()
2586 spin_lock_bh(&hw->phy_lock); in skge_up()
2587 if (is_genesis(hw)) in skge_up()
2588 genesis_mac_init(hw, port); in skge_up()
2590 yukon_mac_init(hw, port); in skge_up()
2591 spin_unlock_bh(&hw->phy_lock); in skge_up()
2594 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); in skge_up()
2595 ram_addr = hw->ram_offset + 2 * chunk * port; in skge_up()
2597 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); in skge_up()
2601 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); in skge_up()
2606 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2609 spin_lock_irq(&hw->hw_lock); in skge_up()
2610 hw->intr_mask |= portmask[port]; in skge_up()
2611 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_up()
2612 skge_read32(hw, B0_IMSK); in skge_up()
2613 spin_unlock_irq(&hw->hw_lock); in skge_up()
2627 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); in skge_up()
2634 static void skge_rx_stop(struct skge_hw *hw, int port) in skge_rx_stop() argument
2636 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop()
2637 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), in skge_rx_stop()
2639 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop()
2645 struct skge_hw *hw = skge->hw; in skge_down() local
2655 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) in skge_down()
2661 spin_lock_irq(&hw->hw_lock); in skge_down()
2662 hw->intr_mask &= ~portmask[port]; in skge_down()
2663 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); in skge_down()
2664 skge_read32(hw, B0_IMSK); in skge_down()
2665 spin_unlock_irq(&hw->hw_lock); in skge_down()
2667 if (hw->ports == 1) in skge_down()
2668 free_irq(hw->pdev->irq, hw); in skge_down()
2670 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); in skge_down()
2671 if (is_genesis(hw)) in skge_down()
2677 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); in skge_down()
2678 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), in skge_down()
2683 skge_write8(hw, SK_REG(port, TXA_CTRL), in skge_down()
2687 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); in skge_down()
2688 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); in skge_down()
2691 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); in skge_down()
2692 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); in skge_down()
2695 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); in skge_down()
2697 skge_rx_stop(hw, port); in skge_down()
2699 if (is_genesis(hw)) { in skge_down()
2700 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2701 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); in skge_down()
2703 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2704 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); in skge_down()
2717 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); in skge_down()
2733 struct skge_hw *hw = skge->hw; in skge_xmit_frame() local
2751 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); in skge_xmit_frame()
2752 if (pci_dma_mapping_error(hw->pdev, map)) in skge_xmit_frame()
2768 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) in skge_xmit_frame()
2788 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, in skge_xmit_frame()
2790 if (dma_mapping_error(&hw->pdev->dev, map)) in skge_xmit_frame()
2814 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); in skge_xmit_frame()
2832 pci_unmap_single(hw->pdev, in skge_xmit_frame()
2838 pci_unmap_page(hw->pdev, in skge_xmit_frame()
2846 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); in skge_xmit_frame()
2876 skge_tx_unmap(skge->hw->pdev, e, td->control); in skge_tx_clean()
2893 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); in skge_tx_timeout()
2932 struct skge_hw *hw = skge->hw; in genesis_set_multicast() local
2938 mode = xm_read32(hw, port, XM_MODE); in genesis_set_multicast()
2958 xm_write32(hw, port, XM_MODE, mode); in genesis_set_multicast()
2959 xm_outhash(hw, port, XM_HSM, filter); in genesis_set_multicast()
2971 struct skge_hw *hw = skge->hw; in yukon_set_multicast() local
2981 reg = gma_read16(hw, port, GM_RX_CTRL); in yukon_set_multicast()
3001 gma_write16(hw, port, GM_MC_ADDR_H1, in yukon_set_multicast()
3003 gma_write16(hw, port, GM_MC_ADDR_H2, in yukon_set_multicast()
3005 gma_write16(hw, port, GM_MC_ADDR_H3, in yukon_set_multicast()
3007 gma_write16(hw, port, GM_MC_ADDR_H4, in yukon_set_multicast()
3010 gma_write16(hw, port, GM_RX_CTRL, reg); in yukon_set_multicast()
3013 static inline u16 phy_length(const struct skge_hw *hw, u32 status) in phy_length() argument
3015 if (is_genesis(hw)) in phy_length()
3021 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) in bad_phy_status() argument
3023 if (is_genesis(hw)) in bad_phy_status()
3034 if (is_genesis(skge->hw)) in skge_set_multicast()
3063 if (bad_phy_status(skge->hw, status)) in skge_rx_get()
3066 if (phy_length(skge->hw, status) != len) in skge_rx_get()
3074 pci_dma_sync_single_for_cpu(skge->hw->pdev, in skge_rx_get()
3079 pci_dma_sync_single_for_device(skge->hw->pdev, in skge_rx_get()
3102 pci_unmap_single(skge->hw->pdev, in skge_rx_get()
3124 if (is_genesis(skge->hw)) { in skge_rx_get()
3153 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_tx_done()
3161 skge_tx_unmap(skge->hw->pdev, e, control); in skge_tx_done()
3196 struct skge_hw *hw = skge->hw; in skge_poll() local
3203 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll()
3225 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); in skge_poll()
3230 spin_lock_irqsave(&hw->hw_lock, flags); in skge_poll()
3231 hw->intr_mask |= napimask[skge->port]; in skge_poll()
3232 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_poll()
3233 skge_read32(hw, B0_IMSK); in skge_poll()
3234 spin_unlock_irqrestore(&hw->hw_lock, flags); in skge_poll()
3243 static void skge_mac_parity(struct skge_hw *hw, int port) in skge_mac_parity() argument
3245 struct net_device *dev = hw->dev[port]; in skge_mac_parity()
3249 if (is_genesis(hw)) in skge_mac_parity()
3250 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), in skge_mac_parity()
3253 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ in skge_mac_parity()
3254 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), in skge_mac_parity()
3255 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) in skge_mac_parity()
3259 static void skge_mac_intr(struct skge_hw *hw, int port) in skge_mac_intr() argument
3261 if (is_genesis(hw)) in skge_mac_intr()
3262 genesis_mac_intr(hw, port); in skge_mac_intr()
3264 yukon_mac_intr(hw, port); in skge_mac_intr()
3268 static void skge_error_irq(struct skge_hw *hw) in skge_error_irq() argument
3270 struct pci_dev *pdev = hw->pdev; in skge_error_irq()
3271 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
3273 if (is_genesis(hw)) { in skge_error_irq()
3276 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); in skge_error_irq()
3278 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); in skge_error_irq()
3282 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); in skge_error_irq()
3287 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); in skge_error_irq()
3292 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); in skge_error_irq()
3296 skge_mac_parity(hw, 0); in skge_error_irq()
3299 skge_mac_parity(hw, 1); in skge_error_irq()
3303 hw->dev[0]->name); in skge_error_irq()
3304 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); in skge_error_irq()
3309 hw->dev[1]->name); in skge_error_irq()
3310 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); in skge_error_irq()
3324 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_error_irq()
3328 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_error_irq()
3331 hwstatus = skge_read32(hw, B0_HWE_ISRC); in skge_error_irq()
3333 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); in skge_error_irq()
3334 hw->intr_mask &= ~IS_HW_ERR; in skge_error_irq()
3346 struct skge_hw *hw = (struct skge_hw *) arg; in skge_extirq() local
3349 for (port = 0; port < hw->ports; port++) { in skge_extirq()
3350 struct net_device *dev = hw->dev[port]; in skge_extirq()
3355 spin_lock(&hw->phy_lock); in skge_extirq()
3356 if (!is_genesis(hw)) in skge_extirq()
3358 else if (hw->phy_type == SK_PHY_BCOM) in skge_extirq()
3360 spin_unlock(&hw->phy_lock); in skge_extirq()
3364 spin_lock_irq(&hw->hw_lock); in skge_extirq()
3365 hw->intr_mask |= IS_EXT_REG; in skge_extirq()
3366 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_extirq()
3367 skge_read32(hw, B0_IMSK); in skge_extirq()
3368 spin_unlock_irq(&hw->hw_lock); in skge_extirq()
3373 struct skge_hw *hw = dev_id; in skge_intr() local
3377 spin_lock(&hw->hw_lock); in skge_intr()
3379 status = skge_read32(hw, B0_SP_ISRC); in skge_intr()
3384 status &= hw->intr_mask; in skge_intr()
3386 hw->intr_mask &= ~IS_EXT_REG; in skge_intr()
3387 tasklet_schedule(&hw->phy_task); in skge_intr()
3391 struct skge_port *skge = netdev_priv(hw->dev[0]); in skge_intr()
3392 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); in skge_intr()
3397 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); in skge_intr()
3400 ++hw->dev[0]->stats.rx_over_errors; in skge_intr()
3401 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); in skge_intr()
3406 skge_mac_intr(hw, 0); in skge_intr()
3408 if (hw->dev[1]) { in skge_intr()
3409 struct skge_port *skge = netdev_priv(hw->dev[1]); in skge_intr()
3412 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); in skge_intr()
3417 ++hw->dev[1]->stats.rx_over_errors; in skge_intr()
3418 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); in skge_intr()
3422 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); in skge_intr()
3425 skge_mac_intr(hw, 1); in skge_intr()
3429 skge_error_irq(hw); in skge_intr()
3431 skge_write32(hw, B0_IMSK, hw->intr_mask); in skge_intr()
3432 skge_read32(hw, B0_IMSK); in skge_intr()
3433 spin_unlock(&hw->hw_lock); in skge_intr()
3444 skge_intr(dev->irq, skge->hw); in skge_netpoll()
3452 struct skge_hw *hw = skge->hw; in skge_set_mac_address() local
3463 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3464 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3467 spin_lock_bh(&hw->phy_lock); in skge_set_mac_address()
3468 ctrl = gma_read16(hw, port, GM_GP_CTRL); in skge_set_mac_address()
3469 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); in skge_set_mac_address()
3471 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3472 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); in skge_set_mac_address()
3474 if (is_genesis(hw)) in skge_set_mac_address()
3475 xm_outaddr(hw, port, XM_SA, dev->dev_addr); in skge_set_mac_address()
3477 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); in skge_set_mac_address()
3478 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); in skge_set_mac_address()
3481 gma_write16(hw, port, GM_GP_CTRL, ctrl); in skge_set_mac_address()
3482 spin_unlock_bh(&hw->phy_lock); in skge_set_mac_address()
3498 static const char *skge_board_name(const struct skge_hw *hw) in skge_board_name() argument
3504 if (skge_chips[i].id == hw->chip_id) in skge_board_name()
3507 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id); in skge_board_name()
3516 static int skge_reset(struct skge_hw *hw) in skge_reset() argument
3523 ctst = skge_read16(hw, B0_CTST); in skge_reset()
3526 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_reset()
3527 skge_write8(hw, B0_CTST, CS_RST_CLR); in skge_reset()
3530 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3531 skge_write8(hw, B2_TST_CTRL2, 0); in skge_reset()
3533 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); in skge_reset()
3534 pci_write_config_word(hw->pdev, PCI_STATUS, in skge_reset()
3536 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3537 skge_write8(hw, B0_CTST, CS_MRST_CLR); in skge_reset()
3540 skge_write16(hw, B0_CTST, in skge_reset()
3543 hw->chip_id = skge_read8(hw, B2_CHIP_ID); in skge_reset()
3544 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; in skge_reset()
3545 pmd_type = skge_read8(hw, B2_PMD_TYP); in skge_reset()
3546 hw->copper = (pmd_type == 'T' || pmd_type == '1'); in skge_reset()
3548 switch (hw->chip_id) { in skge_reset()
3551 switch (hw->phy_type) { in skge_reset()
3553 hw->phy_addr = PHY_ADDR_XMAC; in skge_reset()
3556 hw->phy_addr = PHY_ADDR_BCOM; in skge_reset()
3559 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", in skge_reset()
3560 hw->phy_type); in skge_reset()
3565 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); in skge_reset()
3572 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') in skge_reset()
3573 hw->copper = 1; in skge_reset()
3575 hw->phy_addr = PHY_ADDR_MARV; in skge_reset()
3579 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", in skge_reset()
3580 hw->chip_id); in skge_reset()
3584 mac_cfg = skge_read8(hw, B2_MAC_CFG); in skge_reset()
3585 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; in skge_reset()
3586 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; in skge_reset()
3589 t8 = skge_read8(hw, B2_E_0); in skge_reset()
3590 if (is_genesis(hw)) { in skge_reset()
3593 hw->ram_size = 0x100000; in skge_reset()
3594 hw->ram_offset = 0x80000; in skge_reset()
3596 hw->ram_size = t8 * 512; in skge_reset()
3598 hw->ram_size = 0x20000; in skge_reset()
3600 hw->ram_size = t8 * 4096; in skge_reset()
3602 hw->intr_mask = IS_HW_ERR; in skge_reset()
3605 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) in skge_reset()
3606 hw->intr_mask |= IS_EXT_REG; in skge_reset()
3608 if (is_genesis(hw)) in skge_reset()
3609 genesis_init(hw); in skge_reset()
3612 skge_write8(hw, B0_POWER_CTRL, in skge_reset()
3616 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && in skge_reset()
3617 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { in skge_reset()
3618 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); in skge_reset()
3619 hw->intr_mask &= ~IS_HW_ERR; in skge_reset()
3623 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); in skge_reset()
3624 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); in skge_reset()
3626 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); in skge_reset()
3627 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in skge_reset()
3630 for (i = 0; i < hw->ports; i++) { in skge_reset()
3631 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); in skge_reset()
3632 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); in skge_reset()
3637 skge_write8(hw, B2_TI_CTRL, TIM_STOP); in skge_reset()
3638 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); in skge_reset()
3639 skge_write8(hw, B0_LED, LED_STAT_ON); in skge_reset()
3642 for (i = 0; i < hw->ports; i++) in skge_reset()
3643 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); in skge_reset()
3646 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); in skge_reset()
3648 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); in skge_reset()
3649 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); in skge_reset()
3650 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); in skge_reset()
3651 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); in skge_reset()
3652 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); in skge_reset()
3653 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); in skge_reset()
3654 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); in skge_reset()
3655 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); in skge_reset()
3656 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); in skge_reset()
3657 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); in skge_reset()
3658 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); in skge_reset()
3659 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); in skge_reset()
3661 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); in skge_reset()
3666 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); in skge_reset()
3667 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); in skge_reset()
3668 skge_write32(hw, B2_IRQM_CTRL, TIM_START); in skge_reset()
3671 skge_write32(hw, B0_IMSK, 0); in skge_reset()
3673 for (i = 0; i < hw->ports; i++) { in skge_reset()
3674 if (is_genesis(hw)) in skge_reset()
3675 genesis_reset(hw, i); in skge_reset()
3677 yukon_reset(hw, i); in skge_reset()
3692 const struct skge_hw *hw = skge->hw; in skge_debug_show() local
3698 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), in skge_debug_show()
3699 skge_read32(hw, B0_IMSK)); in skge_debug_show()
3806 static struct net_device *skge_devinit(struct skge_hw *hw, int port, in skge_devinit() argument
3815 SET_NETDEV_DEV(dev, &hw->pdev->dev); in skge_devinit()
3819 dev->irq = hw->pdev->irq; in skge_devinit()
3831 skge->hw = hw; in skge_devinit()
3842 skge->advertising = skge_supported_modes(hw); in skge_devinit()
3844 if (device_can_wakeup(&hw->pdev->dev)) { in skge_devinit()
3845 skge->wol = wol_supported(hw) & WAKE_MAGIC; in skge_devinit()
3846 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); in skge_devinit()
3849 hw->dev[port] = dev; in skge_devinit()
3854 if (is_genesis(hw)) in skge_devinit()
3863 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); in skge_devinit()
3880 struct skge_hw *hw; in skge_probe() local
3923 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") in skge_probe()
3925 if (!hw) in skge_probe()
3928 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); in skge_probe()
3930 hw->pdev = pdev; in skge_probe()
3931 spin_lock_init(&hw->hw_lock); in skge_probe()
3932 spin_lock_init(&hw->phy_lock); in skge_probe()
3933 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw); in skge_probe()
3935 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); in skge_probe()
3936 if (!hw->regs) { in skge_probe()
3941 err = skge_reset(hw); in skge_probe()
3948 skge_board_name(hw), hw->chip_rev); in skge_probe()
3950 dev = skge_devinit(hw, 0, using_dac); in skge_probe()
3968 if (hw->ports > 1) { in skge_probe()
3969 dev1 = skge_devinit(hw, 1, using_dac); in skge_probe()
3982 hw->irq_name, hw); in skge_probe()
3991 pci_set_drvdata(pdev, hw); in skge_probe()
4004 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_probe()
4006 iounmap(hw->regs); in skge_probe()
4008 kfree(hw); in skge_probe()
4019 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_remove() local
4022 if (!hw) in skge_remove()
4025 dev1 = hw->dev[1]; in skge_remove()
4028 dev0 = hw->dev[0]; in skge_remove()
4031 tasklet_kill(&hw->phy_task); in skge_remove()
4033 spin_lock_irq(&hw->hw_lock); in skge_remove()
4034 hw->intr_mask = 0; in skge_remove()
4036 if (hw->ports > 1) { in skge_remove()
4037 skge_write32(hw, B0_IMSK, 0); in skge_remove()
4038 skge_read32(hw, B0_IMSK); in skge_remove()
4040 spin_unlock_irq(&hw->hw_lock); in skge_remove()
4042 skge_write16(hw, B0_LED, LED_STAT_OFF); in skge_remove()
4043 skge_write8(hw, B0_CTST, CS_RST_SET); in skge_remove()
4045 if (hw->ports > 1) in skge_remove()
4046 free_irq(pdev->irq, hw); in skge_remove()
4053 iounmap(hw->regs); in skge_remove()
4054 kfree(hw); in skge_remove()
4060 struct skge_hw *hw = dev_get_drvdata(dev); in skge_suspend() local
4063 if (!hw) in skge_suspend()
4066 for (i = 0; i < hw->ports; i++) { in skge_suspend()
4067 struct net_device *dev = hw->dev[i]; in skge_suspend()
4077 skge_write32(hw, B0_IMSK, 0); in skge_suspend()
4084 struct skge_hw *hw = dev_get_drvdata(dev); in skge_resume() local
4087 if (!hw) in skge_resume()
4090 err = skge_reset(hw); in skge_resume()
4094 for (i = 0; i < hw->ports; i++) { in skge_resume()
4095 struct net_device *dev = hw->dev[i]; in skge_resume()
4121 struct skge_hw *hw = pci_get_drvdata(pdev); in skge_shutdown() local
4124 if (!hw) in skge_shutdown()
4127 for (i = 0; i < hw->ports; i++) { in skge_shutdown()
4128 struct net_device *dev = hw->dev[i]; in skge_shutdown()