Lines Matching refs:mvpp2_write
75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) in mvpp2_write() function
380 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
382 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
386 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
405 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
509 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
556 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); in mvpp2_bm_init()
558 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); in mvpp2_bm_init()
606 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
627 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
1018 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
1029 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
1037 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_enable()
1045 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_disable()
1415 mvpp2_write(priv, MVPP2_CTRS_IDX, index); in mvpp2_read_index()
1709 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
1711 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
1714 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); in mvpp2_defaults_set()
1718 mvpp2_write(port->priv, in mvpp2_defaults_set()
1724 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
1730 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
1732 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
1735 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
1745 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
1762 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
1775 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
1797 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
1798 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
1811 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
1815 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
1860 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
1890 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
2108 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
2114 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
2123 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
2135 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
2210 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
2226 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); in mvpp2_tx_time_coal_set()
2343 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); in mvpp2_aggr_txq_init()
2344 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), in mvpp2_aggr_txq_init()
2370 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
2444 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
2502 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
2508 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
2511 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
2575 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); in mvpp2_txq_deinit()
2645 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
2656 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3357 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_poll()
4515 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), in mvpp2_rx_irqs_setup()
4529 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); in mvpp2_rx_irqs_setup()
4533 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); in mvpp2_rx_irqs_setup()
5466 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); in mvpp2_conf_mbus_windows()
5467 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); in mvpp2_conf_mbus_windows()
5470 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); in mvpp2_conf_mbus_windows()
5478 mvpp2_write(priv, MVPP2_WIN_BASE(i), in mvpp2_conf_mbus_windows()
5482 mvpp2_write(priv, MVPP2_WIN_SIZE(i), in mvpp2_conf_mbus_windows()
5488 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); in mvpp2_conf_mbus_windows()
5497 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
5499 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
5503 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, in mvpp2_rx_fifo_init()
5505 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); in mvpp2_rx_fifo_init()
5519 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), in mvpp22_rx_fifo_init()
5521 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), in mvpp22_rx_fifo_init()
5524 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), in mvpp22_rx_fifo_init()
5526 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), in mvpp22_rx_fifo_init()
5530 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp22_rx_fifo_init()
5532 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp22_rx_fifo_init()
5536 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, in mvpp22_rx_fifo_init()
5538 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); in mvpp22_rx_fifo_init()
5557 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); in mvpp22_tx_fifo_init()
5558 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); in mvpp22_tx_fifo_init()
5566 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); in mvpp2_axi_init()
5581 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); in mvpp2_axi_init()
5582 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); in mvpp2_axi_init()
5585 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); in mvpp2_axi_init()
5586 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); in mvpp2_axi_init()
5587 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); in mvpp2_axi_init()
5588 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); in mvpp2_axi_init()
5591 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); in mvpp2_axi_init()
5592 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); in mvpp2_axi_init()
5598 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); in mvpp2_axi_init()
5599 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); in mvpp2_axi_init()
5606 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); in mvpp2_axi_init()
5613 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); in mvpp2_axi_init()
5670 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); in mvpp2_init()