Lines Matching refs:mvreg_write
655 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) in mvreg_write() function
755 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
761 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), in mvneta_rxq_non_occup_desc_add()
787 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
807 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); in mvneta_rxq_desc_num_update()
831 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_max_rx_size_set()
847 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_offset_set()
865 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_pend_desc_add()
904 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); in mvneta_rxq_buf_size_set()
915 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_bm_disable()
926 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_bm_enable()
939 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_long_pool_set()
952 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); in mvneta_rxq_short_pool_set()
971 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); in mvneta_bm_pool_bufsize_set()
997 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); in mvneta_mbus_io_win_set()
998 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); in mvneta_mbus_io_win_set()
1001 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); in mvneta_mbus_io_win_set()
1003 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | in mvneta_mbus_io_win_set()
1006 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); in mvneta_mbus_io_win_set()
1010 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); in mvneta_mbus_io_win_set()
1013 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); in mvneta_mbus_io_win_set()
1137 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); in mvneta_bm_update_mtu()
1154 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); in mvneta_port_up()
1164 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); in mvneta_port_up()
1178 mvreg_write(pp, MVNETA_RXQ_CMD, in mvneta_port_down()
1201 mvreg_write(pp, MVNETA_TXQ_CMD, in mvneta_port_down()
1246 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_enable()
1257 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); in mvneta_port_disable()
1278 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); in mvneta_set_ucast_table()
1295 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); in mvneta_set_special_mcast_table()
1315 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); in mvneta_set_other_mcast_table()
1325 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_percpu_unmask_interrupt()
1338 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_percpu_mask_interrupt()
1339 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); in mvneta_percpu_mask_interrupt()
1340 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); in mvneta_percpu_mask_interrupt()
1350 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); in mvneta_percpu_clear_intr_cause()
1351 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_percpu_clear_intr_cause()
1352 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); in mvneta_percpu_clear_intr_cause()
1376 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); in mvneta_defaults_set()
1379 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); in mvneta_defaults_set()
1411 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); in mvneta_defaults_set()
1415 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_defaults_set()
1416 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_defaults_set()
1419 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); in mvneta_defaults_set()
1421 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); in mvneta_defaults_set()
1422 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); in mvneta_defaults_set()
1425 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_defaults_set()
1426 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_defaults_set()
1435 mvreg_write(pp, MVNETA_ACC_MODE, val); in mvneta_defaults_set()
1438 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); in mvneta_defaults_set()
1442 mvreg_write(pp, MVNETA_PORT_CONFIG, val); in mvneta_defaults_set()
1445 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); in mvneta_defaults_set()
1446 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); in mvneta_defaults_set()
1461 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); in mvneta_defaults_set()
1468 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); in mvneta_defaults_set()
1475 mvreg_write(pp, MVNETA_INTR_ENABLE, in mvneta_defaults_set()
1497 mvreg_write(pp, MVNETA_TX_MTU, val); in mvneta_txq_max_tx_size_set()
1507 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); in mvneta_txq_max_tx_size_set()
1517 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); in mvneta_txq_max_tx_size_set()
1549 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); in mvneta_set_ucast_addr()
1564 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); in mvneta_mac_addr_set()
1565 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); in mvneta_mac_addr_set()
1578 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), in mvneta_rx_pkts_coal_set()
1594 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); in mvneta_rx_time_coal_set()
1608 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); in mvneta_tx_done_pkts_coal_set()
1633 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
1638 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); in mvneta_txq_sent_desc_dec()
2580 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, in mvneta_set_special_mcast_addr()
2613 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); in mvneta_set_other_mcast_addr()
2673 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); in mvneta_rx_unicast_promisc_set()
2674 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); in mvneta_rx_unicast_promisc_set()
2681 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); in mvneta_rx_unicast_promisc_set()
2682 mvreg_write(pp, MVNETA_TYPE_PRIO, val); in mvneta_rx_unicast_promisc_set()
2727 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); in mvneta_isr()
2776 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); in mvneta_poll()
2815 mvreg_write(pp, MVNETA_INTR_NEW_MASK, in mvneta_poll()
2867 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); in mvneta_tx_reset()
2868 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); in mvneta_tx_reset()
2873 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); in mvneta_rx_reset()
2874 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); in mvneta_rx_reset()
2900 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); in mvneta_rxq_hw_init()
2901 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); in mvneta_rxq_hw_init()
3028 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); in mvneta_txq_hw_init()
3029 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); in mvneta_txq_hw_init()
3032 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); in mvneta_txq_hw_init()
3033 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); in mvneta_txq_hw_init()
3082 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); in mvneta_txq_hw_deinit()
3083 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); in mvneta_txq_hw_deinit()
3086 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); in mvneta_txq_hw_deinit()
3087 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); in mvneta_txq_hw_deinit()
3195 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_start_dev()
3451 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_mac_an_restart()
3453 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_mac_an_restart()
3538 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, in mvneta_mac_config()
3561 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); in mvneta_mac_config()
3563 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); in mvneta_mac_config()
3565 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); in mvneta_mac_config()
3567 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); in mvneta_mac_config()
3569 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); in mvneta_mac_config()
3587 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); in mvneta_set_eee()
3603 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_mac_link_down()
3622 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); in mvneta_mac_link_up()
3702 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); in mvneta_percpu_elect()
3764 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_cpu_online()
3805 mvreg_write(pp, MVNETA_INTR_MISC_MASK, in mvneta_cpu_dead()
4192 mvreg_write(pp, MVNETA_PORT_CONFIG, val); in mvneta_config_rss()
4311 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); in mvneta_ethtool_set_eee()
4413 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); in mvneta_conf_mbus_windows()
4414 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); in mvneta_conf_mbus_windows()
4417 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); in mvneta_conf_mbus_windows()
4427 mvreg_write(pp, MVNETA_WIN_BASE(i), in mvneta_conf_mbus_windows()
4432 mvreg_write(pp, MVNETA_WIN_SIZE(i), in mvneta_conf_mbus_windows()
4443 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); in mvneta_conf_mbus_windows()
4448 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); in mvneta_conf_mbus_windows()
4449 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); in mvneta_conf_mbus_windows()
4456 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); in mvneta_port_power_up()
4459 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); in mvneta_port_power_up()
4462 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); in mvneta_port_power_up()