Lines Matching defs:adapter_params
363 struct adapter_params { struct
364 struct sge_params sge;
365 struct tp_params tp;
366 struct vpd_params vpd;
367 struct pf_resources pfres;
368 struct pci_params pci;
369 struct devlog_params devlog;
370 enum pcie_memwin drv_memwin;
372 unsigned int cim_la_size;
374 unsigned int sf_size; /* serial flash size in bytes */
375 unsigned int sf_nsec; /* # of flash sectors */
377 unsigned int fw_vers; /* firmware version */
378 unsigned int bs_vers; /* bootstrap version */
379 unsigned int tp_vers; /* TP microcode version */
380 unsigned int er_vers; /* expansion ROM version */
381 unsigned int scfg_vers; /* Serial Configuration version */
382 unsigned int vpd_vers; /* VPD Version */
383 u8 api_vers[7];
385 unsigned short mtus[NMTUS];
386 unsigned short a_wnd[NCCTRL_WIN];
387 unsigned short b_wnd[NCCTRL_WIN];
389 unsigned char nports; /* # of ethernet ports */
390 unsigned char portvec;
391 enum chip_type chip; /* chip code */
392 struct arch_specific_params arch; /* chip specific params */
393 unsigned char offload;
394 unsigned char crypto; /* HW capability for crypto */
396 unsigned char bypass;
397 unsigned char hash_filter;
399 unsigned int ofldq_wr_cred;
400 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
402 unsigned int nsched_cls; /* number of traffic classes */
403 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
404 unsigned int max_ird_adapter; /* Max read depth per adapter */
405 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
406 u8 fw_caps_support; /* 32-bit Port Capabilities */
407 bool filter2_wr_support; /* FW support for FILTER2_WR */
408 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
413 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
414 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
415 bool write_cmpl_support; /* FW supports WRITE_CMPL */