145 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,  in t3_mc7_bd_read()  argument
151 	unsigned int size64 = mc7->size / 8;	/* # of 64-bit words */  in t3_mc7_bd_read()
152 	struct adapter *adap = mc7->adapter;  in t3_mc7_bd_read()
157 	start *= (8 << mc7->width);  in t3_mc7_bd_read()
162 		for (i = (1 << mc7->width) - 1; i >= 0; --i) {  in t3_mc7_bd_read()
166 			t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);  in t3_mc7_bd_read()
167 			t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);  in t3_mc7_bd_read()
168 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);  in t3_mc7_bd_read()
171 						  mc7->offset + A_MC7_BD_OP);  in t3_mc7_bd_read()
175 			val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);  in t3_mc7_bd_read()
176 			if (mc7->width == 0) {  in t3_mc7_bd_read()
178 						    mc7->offset +  in t3_mc7_bd_read()
182 				if (mc7->width > 1)  in t3_mc7_bd_read()
183 					val >>= shift[mc7->width];  in t3_mc7_bd_read()
184 				val64 |= (u64) val << (step[mc7->width] * i);  in t3_mc7_bd_read()
1791 static void mc7_intr_handler(struct mc7 *mc7)  in mc7_intr_handler()  argument
1793 	struct adapter *adapter = mc7->adapter;  in mc7_intr_handler()
1794 	u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);  in mc7_intr_handler()
1797 		mc7->stats.corr_err++;  in mc7_intr_handler()
1799 			"data 0x%x 0x%x 0x%x\n", mc7->name,  in mc7_intr_handler()
1800 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),  in mc7_intr_handler()
1801 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),  in mc7_intr_handler()
1802 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),  in mc7_intr_handler()
1803 			t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));  in mc7_intr_handler()
1807 		mc7->stats.uncorr_err++;  in mc7_intr_handler()
1809 			 "data 0x%x 0x%x 0x%x\n", mc7->name,  in mc7_intr_handler()
1810 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),  in mc7_intr_handler()
1811 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),  in mc7_intr_handler()
1812 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),  in mc7_intr_handler()
1813 			 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));  in mc7_intr_handler()
1817 		mc7->stats.parity_err++;  in mc7_intr_handler()
1819 			 mc7->name, G_PE(cause));  in mc7_intr_handler()
1827 					   mc7->offset + A_MC7_ERR_ADDR);  in mc7_intr_handler()
1828 		mc7->stats.addr_err++;  in mc7_intr_handler()
1830 			 mc7->name, addr);  in mc7_intr_handler()
1836 	t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);  in mc7_intr_handler()
3194 static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)  in mc7_init()  argument
3209 	struct adapter *adapter = mc7->adapter;  in mc7_init()
3212 	if (!mc7->size)  in mc7_init()
3215 	val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);  in mc7_init()
3220 	t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);  in mc7_init()
3221 	val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);	/* flush */  in mc7_init()
3225 		t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);  in mc7_init()
3226 		t3_read_reg(adapter, mc7->offset + A_MC7_CAL);  in mc7_init()
3228 		if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &  in mc7_init()
3231 			       mc7->name);  in mc7_init()
3236 	t3_write_reg(adapter, mc7->offset + A_MC7_PARM,  in mc7_init()
3242 	t3_write_reg(adapter, mc7->offset + A_MC7_CFG,  in mc7_init()
3244 	t3_read_reg(adapter, mc7->offset + A_MC7_CFG);	/* flush */  in mc7_init()
3247 		t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,  in mc7_init()
3252 	if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||  in mc7_init()
3253 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||  in mc7_init()
3254 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||  in mc7_init()
3255 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))  in mc7_init()
3259 		t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);  in mc7_init()
3260 		t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLRST, 0);  in mc7_init()
3264 	if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||  in mc7_init()
3265 	    wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||  in mc7_init()
3266 	    wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||  in mc7_init()
3267 	    wrreg_wait(adapter, mc7->offset + A_MC7_MODE,  in mc7_init()
3269 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||  in mc7_init()
3270 	    wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))  in mc7_init()
3277 	t3_write_reg(adapter, mc7->offset + A_MC7_REF,  in mc7_init()
3279 	t3_read_reg(adapter, mc7->offset + A_MC7_REF);	/* flush */  in mc7_init()
3281 	t3_write_reg(adapter, mc7->offset + A_MC7_ECC, F_ECCGENEN | F_ECCCHKEN);  in mc7_init()
3282 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);  in mc7_init()
3283 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);  in mc7_init()
3284 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,  in mc7_init()
3285 		     (mc7->size << width) - 1);  in mc7_init()
3286 	t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));  in mc7_init()
3287 	t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);	/* flush */  in mc7_init()
3292 		val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);  in mc7_init()
3295 		CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);  in mc7_init()
3300 	t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);  in mc7_init()
3526 static void mc7_prep(struct adapter *adapter, struct mc7 *mc7,  in mc7_prep()  argument
3531 	mc7->adapter = adapter;  in mc7_prep()
3532 	mc7->name = name;  in mc7_prep()
3533 	mc7->offset = base_addr - MC7_PMRX_BASE_ADDR;  in mc7_prep()
3534 	cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);  in mc7_prep()
3535 	mc7->size = G_DEN(cfg) == M_DEN ? 0 : mc7_calc_size(cfg);  in mc7_prep()
3536 	mc7->width = G_WIDTH(cfg);  in mc7_prep()