Lines Matching refs:oct
218 struct octeon_device *oct = lio->oct_dev; in lio_get_link_ksettings() local
246 dev_dbg(&oct->pci_dev->dev, "ecmd->base.transceiver is XCVR_EXTERNAL\n"); in lio_get_link_ksettings()
249 dev_err(&oct->pci_dev->dev, "Unknown link interface mode: %d\n", in lio_get_link_ksettings()
259 if (oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_get_link_ksettings()
260 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID) { in lio_get_link_ksettings()
261 if (OCTEON_CN23XX_PF(oct)) { in lio_get_link_ksettings()
269 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
281 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
285 oct->speed_setting = 25; in lio_get_link_ksettings()
288 if (oct->speed_setting == 10) { in lio_get_link_ksettings()
299 if (oct->speed_setting == 25) { in lio_get_link_ksettings()
311 if (oct->no_speed_setting) in lio_get_link_ksettings()
319 if (oct->props[lio->ifidx].fec == 1) { in lio_get_link_ksettings()
399 struct octeon_device *oct; in lio_set_link_ksettings() local
401 oct = lio->oct_dev; in lio_set_link_ksettings()
405 if (!(oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_set_link_ksettings()
406 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID)) in lio_set_link_ksettings()
409 if (oct->no_speed_setting) { in lio_set_link_ksettings()
410 dev_err(&oct->pci_dev->dev, "%s: Changing speed is not supported\n", in lio_set_link_ksettings()
422 if ((oct->speed_boot == speed / 1000) && in lio_set_link_ksettings()
423 oct->speed_boot == oct->speed_setting) in lio_set_link_ksettings()
428 dev_dbg(&oct->pci_dev->dev, "Port speed is set to %dG\n", in lio_set_link_ksettings()
429 oct->speed_setting); in lio_set_link_ksettings()
438 struct octeon_device *oct; in lio_get_drvinfo() local
441 oct = lio->oct_dev; in lio_get_drvinfo()
446 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version, in lio_get_drvinfo()
448 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32); in lio_get_drvinfo()
454 struct octeon_device *oct; in lio_get_vf_drvinfo() local
458 oct = lio->oct_dev; in lio_get_vf_drvinfo()
463 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version, in lio_get_vf_drvinfo()
465 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32); in lio_get_vf_drvinfo()
472 struct octeon_device *oct = lio->oct_dev; in lio_send_queue_count_update() local
488 dev_err(&oct->pci_dev->dev, "Failed to send Queue reset command (ret: 0x%x)\n", in lio_send_queue_count_update()
501 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_get_channels() local
505 if (OCTEON_CN6XXX(oct)) { in lio_ethtool_get_channels()
506 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in lio_ethtool_get_channels()
512 } else if (OCTEON_CN23XX_PF(oct)) { in lio_ethtool_get_channels()
513 if (oct->sriov_info.sriov_enabled) { in lio_ethtool_get_channels()
517 CHIP_CONF(oct, cn23xx_pf); in lio_ethtool_get_channels()
521 combined_count = oct->num_iqs; in lio_ethtool_get_channels()
522 } else if (OCTEON_CN23XX_VF(oct)) { in lio_ethtool_get_channels()
526 reg_val = octeon_read_csr64(oct, ctrl); in lio_ethtool_get_channels()
529 combined_count = oct->num_iqs; in lio_ethtool_get_channels()
541 lio_irq_reallocate_irqs(struct octeon_device *oct, uint32_t num_ioqs) in lio_irq_reallocate_irqs() argument
547 if (!oct->msix_on) in lio_irq_reallocate_irqs()
553 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); in lio_irq_reallocate_irqs()
555 if (oct->msix_on) { in lio_irq_reallocate_irqs()
556 if (OCTEON_CN23XX_PF(oct)) in lio_irq_reallocate_irqs()
557 num_msix_irqs = oct->num_msix_irqs - 1; in lio_irq_reallocate_irqs()
558 else if (OCTEON_CN23XX_VF(oct)) in lio_irq_reallocate_irqs()
559 num_msix_irqs = oct->num_msix_irqs; in lio_irq_reallocate_irqs()
561 msix_entries = (struct msix_entry *)oct->msix_entries; in lio_irq_reallocate_irqs()
563 if (oct->ioq_vector[i].vector) { in lio_irq_reallocate_irqs()
568 &oct->ioq_vector[i]); in lio_irq_reallocate_irqs()
569 oct->ioq_vector[i].vector = 0; in lio_irq_reallocate_irqs()
574 if (OCTEON_CN23XX_PF(oct)) in lio_irq_reallocate_irqs()
575 free_irq(msix_entries[i].vector, oct); in lio_irq_reallocate_irqs()
577 pci_disable_msix(oct->pci_dev); in lio_irq_reallocate_irqs()
578 kfree(oct->msix_entries); in lio_irq_reallocate_irqs()
579 oct->msix_entries = NULL; in lio_irq_reallocate_irqs()
582 kfree(oct->irq_name_storage); in lio_irq_reallocate_irqs()
583 oct->irq_name_storage = NULL; in lio_irq_reallocate_irqs()
585 if (octeon_allocate_ioq_vector(oct, num_ioqs)) { in lio_irq_reallocate_irqs()
586 dev_err(&oct->pci_dev->dev, "OCTEON: ioq vector allocation failed\n"); in lio_irq_reallocate_irqs()
590 if (octeon_setup_interrupt(oct, num_ioqs)) { in lio_irq_reallocate_irqs()
591 dev_info(&oct->pci_dev->dev, "Setup interrupt failed\n"); in lio_irq_reallocate_irqs()
596 oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR); in lio_irq_reallocate_irqs()
607 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_set_channels() local
610 if (strcmp(oct->fw_info.liquidio_firmware_version, "1.6.1") < 0) { in lio_ethtool_set_channels()
611 dev_err(&oct->pci_dev->dev, "Minimum firmware version required is 1.6.1\n"); in lio_ethtool_set_channels()
621 if (OCTEON_CN23XX_PF(oct)) { in lio_ethtool_set_channels()
622 if (oct->sriov_info.sriov_enabled) { in lio_ethtool_set_channels()
626 CHIP_CONF(oct, in lio_ethtool_set_channels()
632 } else if (OCTEON_CN23XX_VF(oct)) { in lio_ethtool_set_channels()
636 reg_val = octeon_read_csr64(oct, ctrl); in lio_ethtool_set_channels()
646 if (combined_count == oct->num_iqs) in lio_ethtool_set_channels()
707 struct octeon_device *oct = lio->oct_dev; in octnet_gpio_access() local
723 dev_err(&oct->pci_dev->dev, in octnet_gpio_access()
734 struct octeon_device *oct = lio->oct_dev; in octnet_id_active() local
749 dev_err(&oct->pci_dev->dev, in octnet_id_active()
833 struct octeon_device *oct = lio->oct_dev; in lio_set_phys_id() local
839 cur_ver = OCT_FW_VER(oct->fw_info.ver.maj, in lio_set_phys_id()
840 oct->fw_info.ver.min, in lio_set_phys_id()
841 oct->fw_info.ver.rev); in lio_set_phys_id()
845 if (oct->chip_id == OCTEON_CN66XX) { in lio_set_phys_id()
850 } else if (oct->chip_id == OCTEON_CN68XX) { in lio_set_phys_id()
878 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { in lio_set_phys_id()
891 if (oct->chip_id == OCTEON_CN23XX_PF_VID && in lio_set_phys_id()
895 else if (oct->chip_id == OCTEON_CN66XX) in lio_set_phys_id()
904 if (oct->chip_id == OCTEON_CN23XX_PF_VID && in lio_set_phys_id()
908 else if (oct->chip_id == OCTEON_CN66XX) in lio_set_phys_id()
917 if (oct->chip_id == OCTEON_CN66XX) { in lio_set_phys_id()
920 } else if (oct->chip_id == OCTEON_CN68XX) { in lio_set_phys_id()
933 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { in lio_set_phys_id()
954 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_get_ringparam() local
961 if (OCTEON_CN6XXX(oct)) { in lio_ethtool_get_ringparam()
962 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in lio_ethtool_get_ringparam()
968 } else if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) { in lio_ethtool_get_ringparam()
971 rx_pending = oct->droq[0]->max_count; in lio_ethtool_get_ringparam()
972 tx_pending = oct->instr_queue[0]->max_count; in lio_ethtool_get_ringparam()
987 struct octeon_device *oct = lio->oct_dev; in lio_23xx_reconfigure_queue_count() local
1000 octeon_alloc_soft_command(oct, data_size, in lio_23xx_reconfigure_queue_count()
1003 dev_err(&oct->pci_dev->dev, "%s: Failed to allocate soft command\n", in lio_23xx_reconfigure_queue_count()
1015 ifidx_or_pfnum = oct->pf_num; in lio_23xx_reconfigure_queue_count()
1018 if_cfg.s.num_iqueues = oct->sriov_info.num_pf_rings; in lio_23xx_reconfigure_queue_count()
1019 if_cfg.s.num_oqueues = oct->sriov_info.num_pf_rings; in lio_23xx_reconfigure_queue_count()
1020 if_cfg.s.base_queue = oct->sriov_info.pf_srn; in lio_23xx_reconfigure_queue_count()
1021 if_cfg.s.gmx_port_id = oct->pf_num; in lio_23xx_reconfigure_queue_count()
1024 octeon_prepare_soft_command(oct, sc, OPCODE_NIC, in lio_23xx_reconfigure_queue_count()
1031 retval = octeon_send_soft_command(oct, sc); in lio_23xx_reconfigure_queue_count()
1033 dev_err(&oct->pci_dev->dev, in lio_23xx_reconfigure_queue_count()
1036 octeon_free_soft_command(oct, sc); in lio_23xx_reconfigure_queue_count()
1040 retval = wait_for_sc_completion_timeout(oct, sc, 0); in lio_23xx_reconfigure_queue_count()
1046 dev_err(&oct->pci_dev->dev, in lio_23xx_reconfigure_queue_count()
1074 dev_info(&oct->pci_dev->dev, "Queue count updated to %d\n", in lio_23xx_reconfigure_queue_count()
1085 struct octeon_device *oct = lio->oct_dev; in lio_reset_queues() local
1092 if (wait_for_pending_requests(oct)) in lio_reset_queues()
1093 dev_err(&oct->pci_dev->dev, "There were pending requests\n"); in lio_reset_queues()
1095 if (lio_wait_for_instr_fetch(oct)) in lio_reset_queues()
1096 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n"); in lio_reset_queues()
1098 if (octeon_set_io_queues_off(oct)) { in lio_reset_queues()
1099 dev_err(&oct->pci_dev->dev, "Setting io queues off failed\n"); in lio_reset_queues()
1106 oct->fn_list.disable_io_queues(oct); in lio_reset_queues()
1111 if (num_qs != oct->num_iqs) { in lio_reset_queues()
1114 dev_err(&oct->pci_dev->dev, in lio_reset_queues()
1121 dev_err(&oct->pci_dev->dev, in lio_reset_queues()
1146 if ((OCTEON_CN23XX_PF(oct)) && !oct->sriov_info.sriov_enabled) in lio_reset_queues()
1147 oct->fn_list.free_mbox(oct); in lio_reset_queues()
1150 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { in lio_reset_queues()
1151 if (!(oct->io_qmask.oq & BIT_ULL(i))) in lio_reset_queues()
1153 octeon_delete_droq(oct, i); in lio_reset_queues()
1156 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { in lio_reset_queues()
1157 if (!(oct->io_qmask.iq & BIT_ULL(i))) in lio_reset_queues()
1159 octeon_delete_instr_queue(oct, i); in lio_reset_queues()
1164 if ((OCTEON_CN23XX_PF(oct)) && in lio_reset_queues()
1165 !oct->sriov_info.sriov_enabled) { in lio_reset_queues()
1166 oct->sriov_info.num_pf_rings = num_qs; in lio_reset_queues()
1167 if (cn23xx_sriov_config(oct)) { in lio_reset_queues()
1168 dev_err(&oct->pci_dev->dev, in lio_reset_queues()
1173 num_qs = oct->sriov_info.num_pf_rings; in lio_reset_queues()
1177 if (oct->fn_list.setup_device_regs(oct)) { in lio_reset_queues()
1178 dev_err(&oct->pci_dev->dev, "Failed to configure device registers\n"); in lio_reset_queues()
1186 if (octeon_setup_instr_queues(oct)) in lio_reset_queues()
1189 if (octeon_setup_output_queues(oct)) in lio_reset_queues()
1193 if (OCTEON_CN23XX_PF(oct) && !oct->sriov_info.sriov_enabled) { in lio_reset_queues()
1194 if (oct->fn_list.setup_mbox(oct)) { in lio_reset_queues()
1195 dev_err(&oct->pci_dev->dev, "Mailbox setup failed\n"); in lio_reset_queues()
1203 if (lio_irq_reallocate_irqs(oct, num_qs)) { in lio_reset_queues()
1204 dev_err(&oct->pci_dev->dev, "IRQs could not be allocated\n"); in lio_reset_queues()
1209 if (oct->fn_list.enable_io_queues(oct)) { in lio_reset_queues()
1210 dev_err(&oct->pci_dev->dev, "Failed to enable input/output queues\n"); in lio_reset_queues()
1214 for (i = 0; i < oct->num_oqs; i++) in lio_reset_queues()
1215 writel(oct->droq[i]->max_count, in lio_reset_queues()
1216 oct->droq[i]->pkts_credit_reg); in lio_reset_queues()
1222 if (OCTEON_CN23XX_PF(oct) && !oct->sriov_info.sriov_enabled) { in lio_reset_queues()
1229 if (liquidio_setup_io_queues(oct, 0, num_qs, num_qs)) { in lio_reset_queues()
1230 dev_err(&oct->pci_dev->dev, "I/O queues creation failed\n"); in lio_reset_queues()
1235 if (lio_setup_glists(oct, lio, num_qs)) { in lio_reset_queues()
1236 dev_err(&oct->pci_dev->dev, "Gather list allocation failed\n"); in lio_reset_queues()
1241 dev_err(&oct->pci_dev->dev, "lio_setup_rx_oom_poll_fn failed\n"); in lio_reset_queues()
1248 if (oct->sriov_info.sriov_enabled || OCTEON_CN23XX_VF(oct)) in lio_reset_queues()
1261 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_set_ringparam() local
1264 if (!OCTEON_CN23XX_PF(oct) && !OCTEON_CN23XX_VF(oct)) in lio_ethtool_set_ringparam()
1275 rx_count_old = oct->droq[0]->max_count; in lio_ethtool_set_ringparam()
1276 tx_count_old = oct->instr_queue[0]->max_count; in lio_ethtool_set_ringparam()
1290 CFG_SET_NUM_TX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1293 CFG_SET_NUM_RX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1296 if (lio_reset_queues(netdev, oct->num_iqs)) in lio_ethtool_set_ringparam()
1308 CFG_SET_NUM_TX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1311 CFG_SET_NUM_RX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1353 struct octeon_device *oct = lio->oct_dev; in lio_get_pauseparam() local
1357 pause->tx_pause = oct->tx_pause; in lio_get_pauseparam()
1358 pause->rx_pause = oct->rx_pause; in lio_get_pauseparam()
1368 struct octeon_device *oct = lio->oct_dev; in lio_set_pauseparam() local
1374 if (oct->chip_id != OCTEON_CN23XX_PF_VID) in lio_set_pauseparam()
1413 dev_err(&oct->pci_dev->dev, in lio_set_pauseparam()
1418 oct->rx_pause = pause->rx_pause; in lio_set_pauseparam()
1419 oct->tx_pause = pause->tx_pause; in lio_set_pauseparam()
2115 struct octeon_device *oct = lio->oct_dev; in lio_get_intr_coalesce() local
2122 switch (oct->chip_id) { in lio_get_intr_coalesce()
2126 intr_coal->rx_coalesce_usecs = oct->rx_coalesce_usecs; in lio_get_intr_coalesce()
2128 oct->rx_max_coalesced_frames; in lio_get_intr_coalesce()
2132 oct->tx_max_coalesced_frames; in lio_get_intr_coalesce()
2138 (struct octeon_cn6xxx *)oct->chip; in lio_get_intr_coalesce()
2146 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; in lio_get_intr_coalesce()
2172 if ((OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) && in lio_get_intr_coalesce()
2223 struct octeon_device *oct = lio->oct_dev; in oct_cfg_rx_intrcnt() local
2227 switch (oct->chip_id) { in oct_cfg_rx_intrcnt()
2231 (struct octeon_cn6xxx *)oct->chip; in oct_cfg_rx_intrcnt()
2238 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS, in oct_cfg_rx_intrcnt()
2251 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2252 q_no += oct->sriov_info.pf_srn; in oct_cfg_rx_intrcnt()
2254 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), in oct_cfg_rx_intrcnt()
2256 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no)) & in oct_cfg_rx_intrcnt()
2262 oct->rx_max_coalesced_frames = rx_max_coalesced_frames; in oct_cfg_rx_intrcnt()
2273 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2275 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), in oct_cfg_rx_intrcnt()
2277 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no)) & in oct_cfg_rx_intrcnt()
2283 oct->rx_max_coalesced_frames = rx_max_coalesced_frames; in oct_cfg_rx_intrcnt()
2296 struct octeon_device *oct = lio->oct_dev; in oct_cfg_rx_intrtime() local
2300 switch (oct->chip_id) { in oct_cfg_rx_intrtime()
2304 (struct octeon_cn6xxx *)oct->chip; in oct_cfg_rx_intrtime()
2310 time_threshold = lio_cn6xxx_get_oq_ticks(oct, in oct_cfg_rx_intrtime()
2312 octeon_write_csr(oct, in oct_cfg_rx_intrtime()
2328 cn23xx_pf_get_oq_ticks(oct, (u32)rx_coalesce_usecs); in oct_cfg_rx_intrtime()
2329 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2330 q_no += oct->sriov_info.pf_srn; in oct_cfg_rx_intrtime()
2331 octeon_write_csr64(oct, in oct_cfg_rx_intrtime()
2338 oct->rx_coalesce_usecs = rx_coalesce_usecs; in oct_cfg_rx_intrtime()
2351 cn23xx_vf_get_oq_ticks(oct, (u32)rx_coalesce_usecs); in oct_cfg_rx_intrtime()
2352 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2354 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), in oct_cfg_rx_intrtime()
2360 oct->rx_coalesce_usecs = rx_coalesce_usecs; in oct_cfg_rx_intrtime()
2375 struct octeon_device *oct = lio->oct_dev; in oct_cfg_tx_intrcnt() local
2381 switch (oct->chip_id) { in oct_cfg_tx_intrcnt()
2395 for (q_no = 0; q_no < oct->num_iqs; q_no++) { in oct_cfg_tx_intrcnt()
2396 inst_cnt_reg = (oct->instr_queue[q_no])->inst_cnt_reg; in oct_cfg_tx_intrcnt()
2406 oct->tx_max_coalesced_frames = iq_intr_pkt; in oct_cfg_tx_intrcnt()
2420 struct octeon_device *oct = lio->oct_dev; in lio_set_intr_coalesce() local
2425 switch (oct->chip_id) { in lio_set_intr_coalesce()
2434 oct->instr_queue[q_no]->fill_threshold = in lio_set_intr_coalesce()
2438 dev_err(&oct->pci_dev->dev, in lio_set_intr_coalesce()
2454 intrmod.rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2455 intrmod.rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2456 intrmod.tx_frames = CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2469 oct->rx_coalesce_usecs = in lio_set_intr_coalesce()
2470 CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2471 oct->rx_max_coalesced_frames = in lio_set_intr_coalesce()
2472 CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2480 oct->tx_max_coalesced_frames = in lio_set_intr_coalesce()
2481 CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2525 struct octeon_device *oct = lio->oct_dev; in lio_get_regs_len() local
2527 switch (oct->chip_id) { in lio_get_regs_len()
2537 static int cn23xx_read_csr_reg(char *s, struct octeon_device *oct) in cn23xx_read_csr_reg() argument
2540 u8 pf_num = oct->pf_num; in cn23xx_read_csr_reg()
2549 reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2552 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2553 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2556 reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2559 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2560 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2563 reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2566 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2567 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2572 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2575 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2576 (oct->pf_num) * CN23XX_PF_INT_OFFSET; in cn23xx_read_csr_reg()
2579 oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2582 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2583 (oct->pf_num) * CN23XX_PF_INT_OFFSET; in cn23xx_read_csr_reg()
2586 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2587 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2592 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2597 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2602 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2607 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2612 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2618 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2623 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2631 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2637 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2644 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2652 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2660 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2668 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2677 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2685 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2693 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2700 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2708 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2716 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2725 i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2734 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2743 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2751 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2757 static int cn23xx_vf_read_csr_reg(char *s, struct octeon_device *oct) in cn23xx_vf_read_csr_reg() argument
2767 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2771 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2774 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2778 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2781 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2785 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2788 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2792 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2795 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2799 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2802 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2806 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2809 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2813 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2816 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2819 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2822 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2826 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2829 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2833 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2836 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2840 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2843 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2847 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2850 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2854 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2857 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2861 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2864 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2868 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2874 static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct) in cn6xxx_read_csr_reg() argument
2884 CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2887 CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2890 CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2893 CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2896 CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2899 CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2902 octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG)); in cn6xxx_read_csr_reg()
2906 CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct, in cn6xxx_read_csr_reg()
2910 octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1)); in cn6xxx_read_csr_reg()
2912 octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64)); in cn6xxx_read_csr_reg()
2915 for (i = 0; i < oct->num_oqs; i++) { in cn6xxx_read_csr_reg()
2918 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2921 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2925 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2928 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2936 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2939 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2946 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2949 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2953 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2957 octeon_read_csr(oct, CN6XXX_DMA_CNT(1))); in cn6xxx_read_csr_reg()
2961 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2965 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2972 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); in cn6xxx_read_csr_reg()
2974 CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg); in cn6xxx_read_csr_reg()
2980 static int cn6xxx_read_config_reg(char *s, struct octeon_device *oct) in cn6xxx_read_config_reg() argument
2991 pci_read_config_dword(oct->pci_dev, (i * 4), &val); in cn6xxx_read_config_reg()
2997 pci_read_config_dword(oct->pci_dev, (i * 4), &val); in cn6xxx_read_config_reg()
3011 struct octeon_device *oct = lio->oct_dev; in lio_get_regs() local
3015 switch (oct->chip_id) { in lio_get_regs()
3018 len += cn23xx_read_csr_reg(regbuf + len, oct); in lio_get_regs()
3022 len += cn23xx_vf_read_csr_reg(regbuf + len, oct); in lio_get_regs()
3027 len += cn6xxx_read_csr_reg(regbuf + len, oct); in lio_get_regs()
3028 len += cn6xxx_read_config_reg(regbuf + len, oct); in lio_get_regs()
3031 dev_err(&oct->pci_dev->dev, "%s Unknown chipid: %d\n", in lio_get_regs()
3032 __func__, oct->chip_id); in lio_get_regs()
3057 struct octeon_device *oct = lio->oct_dev; in lio_get_fecparam() local
3062 if (oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_get_fecparam()
3063 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID) { in lio_get_fecparam()
3064 if (oct->no_speed_setting == 1) in lio_get_fecparam()
3069 if (oct->props[lio->ifidx].fec == 1) in lio_get_fecparam()
3082 struct octeon_device *oct = lio->oct_dev; in lio_set_fecparam() local
3084 if (oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_set_fecparam()
3085 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID) { in lio_set_fecparam()
3086 if (oct->no_speed_setting == 1) in lio_set_fecparam()
3157 struct octeon_device *oct = lio->oct_dev; in liquidio_set_ethtool_ops() local
3159 if (OCTEON_CN23XX_VF(oct)) in liquidio_set_ethtool_ops()