Lines Matching refs:oct
39 void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct) in cn23xx_dump_pf_initialized_regs() argument
43 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_dump_pf_initialized_regs()
46 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%llx\n", in cn23xx_dump_pf_initialized_regs()
48 CVM_CAST64(octeon_read_csr64(oct, CN23XX_WIN_WR_MASK_REG))); in cn23xx_dump_pf_initialized_regs()
49 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
51 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1))); in cn23xx_dump_pf_initialized_regs()
52 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
54 lio_pci_readq(oct, CN23XX_RST_SOFT_RST)); in cn23xx_dump_pf_initialized_regs()
57 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
59 lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL)); in cn23xx_dump_pf_initialized_regs()
62 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
65 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i))); in cn23xx_dump_pf_initialized_regs()
66 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
69 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i))); in cn23xx_dump_pf_initialized_regs()
72 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", "CN23XX_DPI_CTL", in cn23xx_dump_pf_initialized_regs()
73 CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL)); in cn23xx_dump_pf_initialized_regs()
76 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val); in cn23xx_dump_pf_initialized_regs()
77 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
81 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
82 "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port, in cn23xx_dump_pf_initialized_regs()
83 CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port), in cn23xx_dump_pf_initialized_regs()
84 lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))); in cn23xx_dump_pf_initialized_regs()
87 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
88 "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port, in cn23xx_dump_pf_initialized_regs()
89 CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)), in cn23xx_dump_pf_initialized_regs()
91 oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)))); in cn23xx_dump_pf_initialized_regs()
93 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
95 (u64)octeon_read_csr64(oct, CN23XX_SLI_PKT_IOQ_RING_RST)); in cn23xx_dump_pf_initialized_regs()
99 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
101 CVM_CAST64(CN23XX_SLI_PKT_MAC_RINFO64(i, oct->pf_num)), in cn23xx_dump_pf_initialized_regs()
103 (oct, CN23XX_SLI_PKT_MAC_RINFO64 in cn23xx_dump_pf_initialized_regs()
104 (i, oct->pf_num)))); in cn23xx_dump_pf_initialized_regs()
109 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
113 (oct, CN23XX_SLI_IQ_PKT_CONTROL64(i)))); in cn23xx_dump_pf_initialized_regs()
117 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
119 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_OQ_WMARK))); in cn23xx_dump_pf_initialized_regs()
122 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
126 oct, CN23XX_SLI_OQ_PKT_CONTROL(i)))); in cn23xx_dump_pf_initialized_regs()
127 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
131 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(i)))); in cn23xx_dump_pf_initialized_regs()
135 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
140 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
147 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
151 oct, CN23XX_SLI_IQ_BASE_ADDR64(i)))); in cn23xx_dump_pf_initialized_regs()
152 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
156 (oct, CN23XX_SLI_IQ_SIZE(i)))); in cn23xx_dump_pf_initialized_regs()
157 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
161 oct, CN23XX_SLI_IQ_DOORBELL(i)))); in cn23xx_dump_pf_initialized_regs()
162 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
166 oct, CN23XX_SLI_IQ_INSTR_COUNT64(i)))); in cn23xx_dump_pf_initialized_regs()
171 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
175 oct, CN23XX_SLI_OQ_BASE_ADDR64(i)))); in cn23xx_dump_pf_initialized_regs()
176 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
180 (oct, CN23XX_SLI_OQ_SIZE(i)))); in cn23xx_dump_pf_initialized_regs()
181 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
185 oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(i)))); in cn23xx_dump_pf_initialized_regs()
186 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
190 oct, CN23XX_SLI_OQ_PKTS_SENT(i)))); in cn23xx_dump_pf_initialized_regs()
191 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
195 oct, CN23XX_SLI_OQ_PKTS_CREDIT(i)))); in cn23xx_dump_pf_initialized_regs()
198 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
201 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_TIME_INT))); in cn23xx_dump_pf_initialized_regs()
202 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", in cn23xx_dump_pf_initialized_regs()
205 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT))); in cn23xx_dump_pf_initialized_regs()
208 static int cn23xx_pf_soft_reset(struct octeon_device *oct) in cn23xx_pf_soft_reset() argument
210 octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF); in cn23xx_pf_soft_reset()
212 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: BIST enabled for CN23XX soft reset\n", in cn23xx_pf_soft_reset()
213 oct->octeon_id); in cn23xx_pf_soft_reset()
215 octeon_write_csr64(oct, CN23XX_SLI_SCRATCH1, 0x1234ULL); in cn23xx_pf_soft_reset()
218 lio_pci_readq(oct, CN23XX_RST_SOFT_RST); in cn23xx_pf_soft_reset()
219 lio_pci_writeq(oct, 1, CN23XX_RST_SOFT_RST); in cn23xx_pf_soft_reset()
224 if (octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)) { in cn23xx_pf_soft_reset()
225 dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Soft reset failed\n", in cn23xx_pf_soft_reset()
226 oct->octeon_id); in cn23xx_pf_soft_reset()
230 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Reset completed\n", in cn23xx_pf_soft_reset()
231 oct->octeon_id); in cn23xx_pf_soft_reset()
234 octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF); in cn23xx_pf_soft_reset()
239 static void cn23xx_enable_error_reporting(struct octeon_device *oct) in cn23xx_enable_error_reporting() argument
244 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val); in cn23xx_enable_error_reporting()
248 pci_read_config_dword(oct->pci_dev, in cn23xx_enable_error_reporting()
251 pci_read_config_dword(oct->pci_dev, in cn23xx_enable_error_reporting()
254 dev_err(&oct->pci_dev->dev, "PCI-E Fatal error detected;\n" in cn23xx_enable_error_reporting()
264 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Enabling PCI-E error reporting..\n", in cn23xx_enable_error_reporting()
265 oct->octeon_id); in cn23xx_enable_error_reporting()
266 pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval); in cn23xx_enable_error_reporting()
269 static u32 cn23xx_coprocessor_clock(struct octeon_device *oct) in cn23xx_coprocessor_clock() argument
276 return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50); in cn23xx_coprocessor_clock()
279 u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us) in cn23xx_pf_get_oq_ticks() argument
282 u32 oqticks_per_us = cn23xx_coprocessor_clock(oct); in cn23xx_pf_get_oq_ticks()
284 oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us; in cn23xx_pf_get_oq_ticks()
301 static void cn23xx_setup_global_mac_regs(struct octeon_device *oct) in cn23xx_setup_global_mac_regs() argument
303 u16 mac_no = oct->pcie_port; in cn23xx_setup_global_mac_regs()
304 u16 pf_num = oct->pf_num; in cn23xx_setup_global_mac_regs()
310 dev_dbg(&oct->pci_dev->dev, "%s:Using pcie port %d\n", in cn23xx_setup_global_mac_regs()
315 octeon_read_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)); in cn23xx_setup_global_mac_regs()
317 if (oct->rev_id == OCTEON_CN23XX_REV_1_1) { in cn23xx_setup_global_mac_regs()
327 (oct->sriov_info.trs << CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS); in cn23xx_setup_global_mac_regs()
329 temp = oct->sriov_info.rings_per_vf & 0xff; in cn23xx_setup_global_mac_regs()
333 temp = oct->sriov_info.max_vfs & 0xff; in cn23xx_setup_global_mac_regs()
337 octeon_write_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num), in cn23xx_setup_global_mac_regs()
340 dev_dbg(&oct->pci_dev->dev, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n", in cn23xx_setup_global_mac_regs()
342 (oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num))); in cn23xx_setup_global_mac_regs()
345 static int cn23xx_reset_io_queues(struct octeon_device *oct) in cn23xx_reset_io_queues() argument
352 srn = oct->sriov_info.pf_srn; in cn23xx_reset_io_queues()
353 ern = srn + oct->sriov_info.num_pf_rings; in cn23xx_reset_io_queues()
361 d64 = octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in cn23xx_reset_io_queues()
363 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), d64); in cn23xx_reset_io_queues()
368 u64 reg_val = octeon_read_csr64(oct, in cn23xx_reset_io_queues()
374 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no))); in cn23xx_reset_io_queues()
377 dev_err(&oct->pci_dev->dev, in cn23xx_reset_io_queues()
384 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in cn23xx_reset_io_queues()
388 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no))); in cn23xx_reset_io_queues()
390 dev_err(&oct->pci_dev->dev, in cn23xx_reset_io_queues()
400 static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct) in cn23xx_pf_setup_global_input_regs() argument
402 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_pf_setup_global_input_regs()
409 pf_num = oct->pf_num; in cn23xx_pf_setup_global_input_regs()
411 srn = oct->sriov_info.pf_srn; in cn23xx_pf_setup_global_input_regs()
412 ern = srn + oct->sriov_info.num_pf_rings; in cn23xx_pf_setup_global_input_regs()
414 if (cn23xx_reset_io_queues(oct)) in cn23xx_pf_setup_global_input_regs()
423 reg_val = oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS; in cn23xx_pf_setup_global_input_regs()
426 if (q_no < oct->sriov_info.pf_srn) { in cn23xx_pf_setup_global_input_regs()
427 vf_num = q_no / oct->sriov_info.rings_per_vf; in cn23xx_pf_setup_global_input_regs()
436 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in cn23xx_pf_setup_global_input_regs()
446 iq = oct->instr_queue[q_no]; in cn23xx_pf_setup_global_input_regs()
450 inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr + in cn23xx_pf_setup_global_input_regs()
454 octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in cn23xx_pf_setup_global_input_regs()
458 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in cn23xx_pf_setup_global_input_regs()
475 static void cn23xx_pf_setup_global_output_regs(struct octeon_device *oct) in cn23xx_pf_setup_global_output_regs() argument
481 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_pf_setup_global_output_regs()
483 srn = oct->sriov_info.pf_srn; in cn23xx_pf_setup_global_output_regs()
484 ern = srn + oct->sriov_info.num_pf_rings; in cn23xx_pf_setup_global_output_regs()
487 octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 32); in cn23xx_pf_setup_global_output_regs()
490 octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 0); in cn23xx_pf_setup_global_output_regs()
494 reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_pf_setup_global_output_regs()
527 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val); in cn23xx_pf_setup_global_output_regs()
535 oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf)); in cn23xx_pf_setup_global_output_regs()
537 octeon_write_csr64(oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), in cn23xx_pf_setup_global_output_regs()
543 writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK); in cn23xx_pf_setup_global_output_regs()
549 if ((oct->rev_id == OCTEON_CN23XX_REV_1_0) || in cn23xx_pf_setup_global_output_regs()
550 (oct->rev_id == OCTEON_CN23XX_REV_1_1)) in cn23xx_pf_setup_global_output_regs()
551 writeq(readq((u8 *)oct->mmio[0].hw_addr + in cn23xx_pf_setup_global_output_regs()
553 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_GBL_CONTROL); in cn23xx_pf_setup_global_output_regs()
556 if (oct->pf_num) in cn23xx_pf_setup_global_output_regs()
558 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN2_W1S); in cn23xx_pf_setup_global_output_regs()
561 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN_W1S); in cn23xx_pf_setup_global_output_regs()
564 static int cn23xx_setup_pf_device_regs(struct octeon_device *oct) in cn23xx_setup_pf_device_regs() argument
566 cn23xx_enable_error_reporting(oct); in cn23xx_setup_pf_device_regs()
569 cn23xx_setup_global_mac_regs(oct); in cn23xx_setup_pf_device_regs()
571 if (cn23xx_pf_setup_global_input_regs(oct)) in cn23xx_setup_pf_device_regs()
574 cn23xx_pf_setup_global_output_regs(oct); in cn23xx_setup_pf_device_regs()
579 octeon_write_csr64(oct, CN23XX_SLI_WINDOW_CTL, in cn23xx_setup_pf_device_regs()
583 octeon_write_csr64(oct, CN23XX_SLI_PKT_IN_JABBER, CN23XX_INPUT_JABBER); in cn23xx_setup_pf_device_regs()
587 static void cn23xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no) in cn23xx_setup_iq_regs() argument
589 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; in cn23xx_setup_iq_regs()
592 iq_no += oct->sriov_info.pf_srn; in cn23xx_setup_iq_regs()
595 octeon_write_csr64(oct, CN23XX_SLI_IQ_BASE_ADDR64(iq_no), in cn23xx_setup_iq_regs()
597 octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count); in cn23xx_setup_iq_regs()
603 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_DOORBELL(iq_no); in cn23xx_setup_iq_regs()
605 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_INSTR_COUNT64(iq_no); in cn23xx_setup_iq_regs()
606 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n", in cn23xx_setup_iq_regs()
614 if (oct->msix_on) { in cn23xx_setup_iq_regs()
628 static void cn23xx_setup_oq_regs(struct octeon_device *oct, u32 oq_no) in cn23xx_setup_oq_regs() argument
631 struct octeon_droq *droq = oct->droq[oq_no]; in cn23xx_setup_oq_regs()
632 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_setup_oq_regs()
636 oq_no += oct->sriov_info.pf_srn; in cn23xx_setup_oq_regs()
638 octeon_write_csr64(oct, CN23XX_SLI_OQ_BASE_ADDR64(oq_no), in cn23xx_setup_oq_regs()
640 octeon_write_csr(oct, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count); in cn23xx_setup_oq_regs()
642 octeon_write_csr(oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no), in cn23xx_setup_oq_regs()
647 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_SENT(oq_no); in cn23xx_setup_oq_regs()
649 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_CREDIT(oq_no); in cn23xx_setup_oq_regs()
651 if (!oct->msix_on) { in cn23xx_setup_oq_regs()
655 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
657 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no), in cn23xx_setup_oq_regs()
663 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in cn23xx_setup_oq_regs()
665 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no), in cn23xx_setup_oq_regs()
669 oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf)); in cn23xx_setup_oq_regs()
673 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no), in cn23xx_setup_oq_regs()
682 struct octeon_device *oct = mbox->oct_dev; in cn23xx_pf_mbox_thread() local
686 if (oct->rev_id < OCTEON_CN23XX_REV_1_1) { in cn23xx_pf_mbox_thread()
691 for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) { in cn23xx_pf_mbox_thread()
692 q_no = i * oct->sriov_info.rings_per_vf; in cn23xx_pf_mbox_thread()
694 val64 = readq(oct->mbox[q_no]->mbox_write_reg); in cn23xx_pf_mbox_thread()
697 if (octeon_mbox_read(oct->mbox[q_no])) in cn23xx_pf_mbox_thread()
699 oct->mbox[q_no]); in cn23xx_pf_mbox_thread()
709 static int cn23xx_setup_pf_mbox(struct octeon_device *oct) in cn23xx_setup_pf_mbox() argument
712 u16 mac_no = oct->pcie_port; in cn23xx_setup_pf_mbox()
713 u16 pf_num = oct->pf_num; in cn23xx_setup_pf_mbox()
716 if (!oct->sriov_info.max_vfs) in cn23xx_setup_pf_mbox()
719 for (i = 0; i < oct->sriov_info.max_vfs; i++) { in cn23xx_setup_pf_mbox()
720 q_no = i * oct->sriov_info.rings_per_vf; in cn23xx_setup_pf_mbox()
730 mbox->oct_dev = oct; in cn23xx_setup_pf_mbox()
737 mbox->mbox_int_reg = (u8 *)oct->mmio[0].hw_addr + in cn23xx_setup_pf_mbox()
741 mbox->mbox_write_reg = (u8 *)oct->mmio[0].hw_addr + in cn23xx_setup_pf_mbox()
745 mbox->mbox_read_reg = (u8 *)oct->mmio[0].hw_addr + in cn23xx_setup_pf_mbox()
753 oct->mbox[q_no] = mbox; in cn23xx_setup_pf_mbox()
758 if (oct->rev_id < OCTEON_CN23XX_REV_1_1) in cn23xx_setup_pf_mbox()
759 schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work, in cn23xx_setup_pf_mbox()
767 vfree(oct->mbox[i]); in cn23xx_setup_pf_mbox()
773 static int cn23xx_free_pf_mbox(struct octeon_device *oct) in cn23xx_free_pf_mbox() argument
777 if (!oct->sriov_info.max_vfs) in cn23xx_free_pf_mbox()
780 for (i = 0; i < oct->sriov_info.max_vfs; i++) { in cn23xx_free_pf_mbox()
781 q_no = i * oct->sriov_info.rings_per_vf; in cn23xx_free_pf_mbox()
783 &oct->mbox[q_no]->mbox_poll_wk.work); in cn23xx_free_pf_mbox()
784 vfree(oct->mbox[q_no]); in cn23xx_free_pf_mbox()
790 static int cn23xx_enable_io_queues(struct octeon_device *oct) in cn23xx_enable_io_queues() argument
796 srn = oct->sriov_info.pf_srn; in cn23xx_enable_io_queues()
797 ern = srn + oct->num_iqs; in cn23xx_enable_io_queues()
801 if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) { in cn23xx_enable_io_queues()
803 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in cn23xx_enable_io_queues()
806 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val); in cn23xx_enable_io_queues()
810 if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) { in cn23xx_enable_io_queues()
815 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in cn23xx_enable_io_queues()
823 oct, in cn23xx_enable_io_queues()
827 dev_err(&oct->pci_dev->dev, in cn23xx_enable_io_queues()
834 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in cn23xx_enable_io_queues()
838 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in cn23xx_enable_io_queues()
840 dev_err(&oct->pci_dev->dev, in cn23xx_enable_io_queues()
847 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in cn23xx_enable_io_queues()
850 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val); in cn23xx_enable_io_queues()
856 if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) { in cn23xx_enable_io_queues()
858 oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no)); in cn23xx_enable_io_queues()
860 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), in cn23xx_enable_io_queues()
867 static void cn23xx_disable_io_queues(struct octeon_device *oct) in cn23xx_disable_io_queues() argument
874 srn = oct->sriov_info.pf_srn; in cn23xx_disable_io_queues()
875 ern = srn + oct->num_iqs; in cn23xx_disable_io_queues()
883 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no))); in cn23xx_disable_io_queues()
887 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in cn23xx_disable_io_queues()
894 oct, CN23XX_SLI_PKT_IOQ_RING_RST)); in cn23xx_disable_io_queues()
897 oct, CN23XX_SLI_PKT_IOQ_RING_RST)); in cn23xx_disable_io_queues()
902 octeon_write_csr(oct, CN23XX_SLI_IQ_DOORBELL(q_no), 0xFFFFFFFF); in cn23xx_disable_io_queues()
903 while (octeon_read_csr64(oct, CN23XX_SLI_IQ_DOORBELL(q_no)) && in cn23xx_disable_io_queues()
918 oct, CN23XX_SLI_PKT_IOQ_RING_RST)); in cn23xx_disable_io_queues()
921 oct, CN23XX_SLI_PKT_IOQ_RING_RST)); in cn23xx_disable_io_queues()
926 octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_CREDIT(q_no), in cn23xx_disable_io_queues()
928 while (octeon_read_csr64(oct, in cn23xx_disable_io_queues()
936 oct, CN23XX_SLI_OQ_PKTS_SENT(q_no))); in cn23xx_disable_io_queues()
937 octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_SENT(q_no), in cn23xx_disable_io_queues()
945 struct octeon_device *oct = ioq_vector->oct_dev; in cn23xx_pf_msix_interrupt_handler() local
948 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index]; in cn23xx_pf_msix_interrupt_handler()
950 dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct); in cn23xx_pf_msix_interrupt_handler()
953 …dev_err(&oct->pci_dev->dev, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL… in cn23xx_pf_msix_interrupt_handler()
954 oct->pf_num, ioq_vector->ioq_num); in cn23xx_pf_msix_interrupt_handler()
984 static void cn23xx_handle_pf_mbox_intr(struct octeon_device *oct) in cn23xx_handle_pf_mbox_intr() argument
990 mbox_int_val = readq(oct->mbox[0]->mbox_int_reg); in cn23xx_handle_pf_mbox_intr()
992 for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) { in cn23xx_handle_pf_mbox_intr()
993 q_no = i * oct->sriov_info.rings_per_vf; in cn23xx_handle_pf_mbox_intr()
997 oct->mbox[0]->mbox_int_reg); in cn23xx_handle_pf_mbox_intr()
998 if (octeon_mbox_read(oct->mbox[q_no])) { in cn23xx_handle_pf_mbox_intr()
999 work = &oct->mbox[q_no]->mbox_poll_wk.work; in cn23xx_handle_pf_mbox_intr()
1009 struct octeon_device *oct = (struct octeon_device *)dev; in cn23xx_interrupt_handler() local
1010 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_interrupt_handler()
1013 dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct); in cn23xx_interrupt_handler()
1016 oct->int_status = 0; in cn23xx_interrupt_handler()
1019 dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Error Intr: 0x%016llx\n", in cn23xx_interrupt_handler()
1020 oct->octeon_id, CVM_CAST64(intr64)); in cn23xx_interrupt_handler()
1024 cn23xx_handle_pf_mbox_intr(oct); in cn23xx_interrupt_handler()
1026 if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) { in cn23xx_interrupt_handler()
1028 oct->int_status |= OCT_DEV_INTR_PKT_DATA; in cn23xx_interrupt_handler()
1032 oct->int_status |= OCT_DEV_INTR_DMA0_FORCE; in cn23xx_interrupt_handler()
1034 oct->int_status |= OCT_DEV_INTR_DMA1_FORCE; in cn23xx_interrupt_handler()
1042 static void cn23xx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr, in cn23xx_bar1_idx_setup() argument
1050 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_setup()
1052 lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL), in cn23xx_bar1_idx_setup()
1053 CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_setup()
1055 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_setup()
1063 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK), in cn23xx_bar1_idx_setup()
1064 CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_setup()
1067 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx))); in cn23xx_bar1_idx_setup()
1070 static void cn23xx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask) in cn23xx_bar1_idx_write() argument
1072 lio_pci_writeq(oct, mask, in cn23xx_bar1_idx_write()
1073 CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_write()
1076 static u32 cn23xx_bar1_idx_read(struct octeon_device *oct, u32 idx) in cn23xx_bar1_idx_read() argument
1079 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in cn23xx_bar1_idx_read()
1103 static void cn23xx_enable_pf_interrupt(struct octeon_device *oct, u8 intr_flag) in cn23xx_enable_pf_interrupt() argument
1105 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_enable_pf_interrupt()
1117 (oct->sriov_info.max_vfs > 0)) { in cn23xx_enable_pf_interrupt()
1118 if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) { in cn23xx_enable_pf_interrupt()
1126 static void cn23xx_disable_pf_interrupt(struct octeon_device *oct, u8 intr_flag) in cn23xx_disable_pf_interrupt() argument
1128 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_disable_pf_interrupt()
1139 (oct->sriov_info.max_vfs > 0)) { in cn23xx_disable_pf_interrupt()
1140 if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) { in cn23xx_disable_pf_interrupt()
1148 static void cn23xx_get_pcie_qlmport(struct octeon_device *oct) in cn23xx_get_pcie_qlmport() argument
1150 oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff; in cn23xx_get_pcie_qlmport()
1152 dev_dbg(&oct->pci_dev->dev, "OCTEON: CN23xx uses PCIE Port %d\n", in cn23xx_get_pcie_qlmport()
1153 oct->pcie_port); in cn23xx_get_pcie_qlmport()
1156 static int cn23xx_get_pf_num(struct octeon_device *oct) in cn23xx_get_pf_num() argument
1165 if (pci_read_config_dword(oct->pci_dev, CN23XX_PCIE_SRIOV_FDL, in cn23xx_get_pf_num()
1167 oct->pf_num = ((fdl_bit >> CN23XX_PCIE_SRIOV_FDL_BIT_POS) & in cn23xx_get_pf_num()
1177 pkt0_in_ctl = octeon_read_csr64(oct, in cn23xx_get_pf_num()
1181 mac = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff; in cn23xx_get_pf_num()
1184 d64 = octeon_read_csr64(oct, in cn23xx_get_pf_num()
1188 dev_err(&oct->pci_dev->dev, in cn23xx_get_pf_num()
1191 oct->pf_num = pfnum; in cn23xx_get_pf_num()
1194 dev_err(&oct->pci_dev->dev, in cn23xx_get_pf_num()
1202 static void cn23xx_setup_reg_address(struct octeon_device *oct) in cn23xx_setup_reg_address() argument
1204 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr; in cn23xx_setup_reg_address()
1205 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_setup_reg_address()
1207 oct->reg_list.pci_win_wr_addr_hi = in cn23xx_setup_reg_address()
1209 oct->reg_list.pci_win_wr_addr_lo = in cn23xx_setup_reg_address()
1211 oct->reg_list.pci_win_wr_addr = in cn23xx_setup_reg_address()
1214 oct->reg_list.pci_win_rd_addr_hi = in cn23xx_setup_reg_address()
1216 oct->reg_list.pci_win_rd_addr_lo = in cn23xx_setup_reg_address()
1218 oct->reg_list.pci_win_rd_addr = in cn23xx_setup_reg_address()
1221 oct->reg_list.pci_win_wr_data_hi = in cn23xx_setup_reg_address()
1223 oct->reg_list.pci_win_wr_data_lo = in cn23xx_setup_reg_address()
1225 oct->reg_list.pci_win_wr_data = in cn23xx_setup_reg_address()
1228 oct->reg_list.pci_win_rd_data_hi = in cn23xx_setup_reg_address()
1230 oct->reg_list.pci_win_rd_data_lo = in cn23xx_setup_reg_address()
1232 oct->reg_list.pci_win_rd_data = in cn23xx_setup_reg_address()
1235 cn23xx_get_pcie_qlmport(oct); in cn23xx_setup_reg_address()
1238 if (!oct->msix_on) in cn23xx_setup_reg_address()
1240 if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) in cn23xx_setup_reg_address()
1245 CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); in cn23xx_setup_reg_address()
1248 CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); in cn23xx_setup_reg_address()
1251 int cn23xx_sriov_config(struct octeon_device *oct) in cn23xx_sriov_config() argument
1253 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; in cn23xx_sriov_config()
1259 (struct octeon_config *)oct_get_config_info(oct, LIO_23XX); in cn23xx_sriov_config()
1260 switch (oct->rev_id) { in cn23xx_sriov_config()
1275 if (oct->sriov_info.num_pf_rings) in cn23xx_sriov_config()
1276 num_pf_rings = oct->sriov_info.num_pf_rings; in cn23xx_sriov_config()
1294 oct->sriov_info.trs = total_rings; in cn23xx_sriov_config()
1295 oct->sriov_info.max_vfs = max_vfs; in cn23xx_sriov_config()
1296 oct->sriov_info.rings_per_vf = rings_per_vf; in cn23xx_sriov_config()
1297 oct->sriov_info.pf_srn = pf_srn; in cn23xx_sriov_config()
1298 oct->sriov_info.num_pf_rings = num_pf_rings; in cn23xx_sriov_config()
1299 dev_notice(&oct->pci_dev->dev, "trs:%d max_vfs:%d rings_per_vf:%d pf_srn:%d num_pf_rings:%d\n", in cn23xx_sriov_config()
1300 oct->sriov_info.trs, oct->sriov_info.max_vfs, in cn23xx_sriov_config()
1301 oct->sriov_info.rings_per_vf, oct->sriov_info.pf_srn, in cn23xx_sriov_config()
1302 oct->sriov_info.num_pf_rings); in cn23xx_sriov_config()
1304 oct->sriov_info.sriov_enabled = 0; in cn23xx_sriov_config()
1309 int setup_cn23xx_octeon_pf_device(struct octeon_device *oct) in setup_cn23xx_octeon_pf_device() argument
1314 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_0, &data32); in setup_cn23xx_octeon_pf_device()
1316 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_1, &data32); in setup_cn23xx_octeon_pf_device()
1318 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_2, &data32); in setup_cn23xx_octeon_pf_device()
1320 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_3, &data32); in setup_cn23xx_octeon_pf_device()
1325 dev_err(&oct->pci_dev->dev, "device BAR0 unassigned\n"); in setup_cn23xx_octeon_pf_device()
1327 dev_err(&oct->pci_dev->dev, "device BAR1 unassigned\n"); in setup_cn23xx_octeon_pf_device()
1331 if (octeon_map_pci_barx(oct, 0, 0)) in setup_cn23xx_octeon_pf_device()
1334 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) { in setup_cn23xx_octeon_pf_device()
1335 dev_err(&oct->pci_dev->dev, "%s CN23XX BAR1 map failed\n", in setup_cn23xx_octeon_pf_device()
1337 octeon_unmap_pci_barx(oct, 0); in setup_cn23xx_octeon_pf_device()
1341 if (cn23xx_get_pf_num(oct) != 0) in setup_cn23xx_octeon_pf_device()
1344 if (cn23xx_sriov_config(oct)) { in setup_cn23xx_octeon_pf_device()
1345 octeon_unmap_pci_barx(oct, 0); in setup_cn23xx_octeon_pf_device()
1346 octeon_unmap_pci_barx(oct, 1); in setup_cn23xx_octeon_pf_device()
1350 octeon_write_csr64(oct, CN23XX_SLI_MAC_CREDIT_CNT, 0x3F802080802080ULL); in setup_cn23xx_octeon_pf_device()
1352 oct->fn_list.setup_iq_regs = cn23xx_setup_iq_regs; in setup_cn23xx_octeon_pf_device()
1353 oct->fn_list.setup_oq_regs = cn23xx_setup_oq_regs; in setup_cn23xx_octeon_pf_device()
1354 oct->fn_list.setup_mbox = cn23xx_setup_pf_mbox; in setup_cn23xx_octeon_pf_device()
1355 oct->fn_list.free_mbox = cn23xx_free_pf_mbox; in setup_cn23xx_octeon_pf_device()
1357 oct->fn_list.process_interrupt_regs = cn23xx_interrupt_handler; in setup_cn23xx_octeon_pf_device()
1358 oct->fn_list.msix_interrupt_handler = cn23xx_pf_msix_interrupt_handler; in setup_cn23xx_octeon_pf_device()
1360 oct->fn_list.soft_reset = cn23xx_pf_soft_reset; in setup_cn23xx_octeon_pf_device()
1361 oct->fn_list.setup_device_regs = cn23xx_setup_pf_device_regs; in setup_cn23xx_octeon_pf_device()
1362 oct->fn_list.update_iq_read_idx = cn23xx_update_read_index; in setup_cn23xx_octeon_pf_device()
1364 oct->fn_list.bar1_idx_setup = cn23xx_bar1_idx_setup; in setup_cn23xx_octeon_pf_device()
1365 oct->fn_list.bar1_idx_write = cn23xx_bar1_idx_write; in setup_cn23xx_octeon_pf_device()
1366 oct->fn_list.bar1_idx_read = cn23xx_bar1_idx_read; in setup_cn23xx_octeon_pf_device()
1368 oct->fn_list.enable_interrupt = cn23xx_enable_pf_interrupt; in setup_cn23xx_octeon_pf_device()
1369 oct->fn_list.disable_interrupt = cn23xx_disable_pf_interrupt; in setup_cn23xx_octeon_pf_device()
1371 oct->fn_list.enable_io_queues = cn23xx_enable_io_queues; in setup_cn23xx_octeon_pf_device()
1372 oct->fn_list.disable_io_queues = cn23xx_disable_io_queues; in setup_cn23xx_octeon_pf_device()
1374 cn23xx_setup_reg_address(oct); in setup_cn23xx_octeon_pf_device()
1376 oct->coproc_clock_rate = 1000000ULL * cn23xx_coprocessor_clock(oct); in setup_cn23xx_octeon_pf_device()
1381 int validate_cn23xx_pf_config_info(struct octeon_device *oct, in validate_cn23xx_pf_config_info() argument
1385 dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n", in validate_cn23xx_pf_config_info()
1392 dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n", in validate_cn23xx_pf_config_info()
1400 dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n", in validate_cn23xx_pf_config_info()
1406 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n", in validate_cn23xx_pf_config_info()
1412 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n", in validate_cn23xx_pf_config_info()
1420 int cn23xx_fw_loaded(struct octeon_device *oct) in cn23xx_fw_loaded() argument
1432 if (atomic_read(oct->adapter_refcount) > 1) in cn23xx_fw_loaded()
1435 val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2); in cn23xx_fw_loaded()
1439 void cn23xx_tell_vf_its_macaddr_changed(struct octeon_device *oct, int vfidx, in cn23xx_tell_vf_its_macaddr_changed() argument
1442 if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vfidx)) { in cn23xx_tell_vf_its_macaddr_changed()
1455 mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf; in cn23xx_tell_vf_its_macaddr_changed()
1456 octeon_mbox_write(oct, &mbox_cmd); in cn23xx_tell_vf_its_macaddr_changed()
1461 cn23xx_get_vf_stats_callback(struct octeon_device *oct, in cn23xx_get_vf_stats_callback() argument
1470 int cn23xx_get_vf_stats(struct octeon_device *oct, int vfidx, in cn23xx_get_vf_stats() argument
1478 if (!(oct->sriov_info.vf_drv_loaded_mask & (1ULL << vfidx))) in cn23xx_get_vf_stats()
1489 mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf; in cn23xx_get_vf_stats()
1497 octeon_mbox_write(oct, &mbox_cmd); in cn23xx_get_vf_stats()
1505 octeon_mbox_cancel(oct, 0); in cn23xx_get_vf_stats()
1506 dev_err(&oct->pci_dev->dev, "Unable to get stats from VF-%d, timedout\n", in cn23xx_get_vf_stats()