Lines Matching refs:tp
91 #define tg3_flag(tp, flag) \ argument
92 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define tg3_flag_set(tp, flag) \ argument
94 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define tg3_flag_clear(tp, flag) \ argument
96 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
131 #define TG3_MAX_MTU(tp) \ argument
132 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
138 #define TG3_RX_STD_RING_SIZE(tp) \ argument
139 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
142 #define TG3_RX_JMB_RING_SIZE(tp) \ argument
143 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
157 #define TG3_RX_STD_RING_BYTES(tp) \ argument
158 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
159 #define TG3_RX_JMB_RING_BYTES(tp) \ argument
160 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
161 #define TG3_RX_RCB_RING_BYTES(tp) \ argument
162 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
177 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ argument
178 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
180 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ argument
181 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
196 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD argument
198 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) argument
202 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) argument
204 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) argument
214 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3) argument
215 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1) argument
474 static void tg3_write32(struct tg3 *tp, u32 off, u32 val) in tg3_write32() argument
476 writel(val, tp->regs + off); in tg3_write32()
479 static u32 tg3_read32(struct tg3 *tp, u32 off) in tg3_read32() argument
481 return readl(tp->regs + off); in tg3_read32()
484 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) in tg3_ape_write32() argument
486 writel(val, tp->aperegs + off); in tg3_ape_write32()
489 static u32 tg3_ape_read32(struct tg3 *tp, u32 off) in tg3_ape_read32() argument
491 return readl(tp->aperegs + off); in tg3_ape_read32()
494 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_reg32() argument
498 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
499 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
501 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
504 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_flush_reg32() argument
506 writel(val, tp->regs + off); in tg3_write_flush_reg32()
507 readl(tp->regs + off); in tg3_write_flush_reg32()
510 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) in tg3_read_indirect_reg32() argument
515 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
516 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
517 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
518 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
522 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_mbox() argument
527 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
532 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
537 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
538 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
539 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
540 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
547 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
548 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
552 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) in tg3_read_indirect_mbox() argument
557 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
558 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
559 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
560 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
569 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) in _tw32_flush() argument
571 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
573 tp->write32(tp, off, val); in _tw32_flush()
576 tg3_write32(tp, off, val); in _tw32_flush()
579 tp->read32(tp, off); in _tw32_flush()
588 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) in tw32_mailbox_flush() argument
590 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
591 if (tg3_flag(tp, FLUSH_POSTED_WRITES) || in tw32_mailbox_flush()
592 (!tg3_flag(tp, MBOX_WRITE_REORDER) && in tw32_mailbox_flush()
593 !tg3_flag(tp, ICH_WORKAROUND))) in tw32_mailbox_flush()
594 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
597 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write32_tx_mbox() argument
599 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
601 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
603 if (tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_write32_tx_mbox()
604 tg3_flag(tp, FLUSH_POSTED_WRITES)) in tg3_write32_tx_mbox()
608 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) in tg3_read32_mbox_5906() argument
610 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
613 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) in tg3_write32_mbox_5906() argument
615 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
618 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
619 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
620 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
621 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
622 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
624 #define tw32(reg, val) tp->write32(tp, reg, val)
625 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
626 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
627 #define tr32(reg) tp->read32(tp, reg)
629 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) in tg3_write_mem() argument
633 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_write_mem()
637 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
638 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
643 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
651 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
654 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) in tg3_read_mem() argument
658 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_read_mem()
664 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
665 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
667 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
670 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
678 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
681 static void tg3_ape_lock_init(struct tg3 *tp) in tg3_ape_lock_init() argument
686 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock_init()
701 if (!tp->pci_fn) in tg3_ape_lock_init()
704 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
706 tg3_ape_write32(tp, regbase + 4 * i, bit); in tg3_ape_lock_init()
711 static int tg3_ape_lock(struct tg3 *tp, int locknum) in tg3_ape_lock() argument
717 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
722 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock()
727 if (!tp->pci_fn) in tg3_ape_lock()
730 bit = 1 << tp->pci_fn; in tg3_ape_lock()
742 if (tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_ape_lock()
752 tg3_ape_write32(tp, req + off, bit); in tg3_ape_lock()
756 status = tg3_ape_read32(tp, gnt + off); in tg3_ape_lock()
759 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
767 tg3_ape_write32(tp, gnt + off, bit); in tg3_ape_lock()
774 static void tg3_ape_unlock(struct tg3 *tp, int locknum) in tg3_ape_unlock() argument
778 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
783 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
788 if (!tp->pci_fn) in tg3_ape_unlock()
791 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
803 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
808 tg3_ape_write32(tp, gnt + 4 * locknum, bit); in tg3_ape_unlock()
811 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) in tg3_ape_event_lock() argument
816 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_event_lock()
819 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_event_lock()
823 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_event_lock()
833 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) in tg3_ape_wait_for_event() argument
838 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_wait_for_event()
849 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, in tg3_ape_scratchpad_read() argument
855 if (!tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_scratchpad_read()
858 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_scratchpad_read()
862 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
866 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + in tg3_ape_scratchpad_read()
869 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); in tg3_ape_scratchpad_read()
878 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
883 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_scratchpad_read()
890 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); in tg3_ape_scratchpad_read()
892 tg3_ape_write32(tp, bufoff, base_off); in tg3_ape_scratchpad_read()
893 tg3_ape_write32(tp, bufoff + sizeof(u32), length); in tg3_ape_scratchpad_read()
895 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_scratchpad_read()
896 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_scratchpad_read()
900 if (tg3_ape_wait_for_event(tp, 30000)) in tg3_ape_scratchpad_read()
904 u32 val = tg3_ape_read32(tp, msgoff + i); in tg3_ape_scratchpad_read()
914 static int tg3_ape_send_event(struct tg3 *tp, u32 event) in tg3_ape_send_event() argument
919 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_send_event()
923 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_send_event()
928 err = tg3_ape_event_lock(tp, 20000); in tg3_ape_send_event()
932 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, in tg3_ape_send_event()
935 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_send_event()
936 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_send_event()
941 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) in tg3_ape_driver_state_change() argument
946 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
951 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
952 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, in tg3_ape_driver_state_change()
954 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, in tg3_ape_driver_state_change()
956 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); in tg3_ape_driver_state_change()
957 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); in tg3_ape_driver_state_change()
958 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, in tg3_ape_driver_state_change()
960 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, in tg3_ape_driver_state_change()
962 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, in tg3_ape_driver_state_change()
968 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
969 tg3_flag(tp, WOL_ENABLE)) { in tg3_ape_driver_state_change()
970 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, in tg3_ape_driver_state_change()
976 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); in tg3_ape_driver_state_change()
986 tg3_ape_send_event(tp, event); in tg3_ape_driver_state_change()
989 static void tg3_send_ape_heartbeat(struct tg3 *tp, in tg3_send_ape_heartbeat() argument
993 if (!tg3_flag(tp, ENABLE_APE) || in tg3_send_ape_heartbeat()
994 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
997 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
998 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1001 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
1006 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1007 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1008 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1011 static void tg3_enable_ints(struct tg3 *tp) in tg3_enable_ints() argument
1015 tp->irq_sync = 0; in tg3_enable_ints()
1019 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1021 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1022 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1023 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1026 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
1029 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1033 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
1034 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1035 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1037 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1039 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1044 struct tg3 *tp = tnapi->tp; in tg3_has_work() local
1049 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
1073 struct tg3 *tp = tnapi->tp; in tg3_int_reenable() local
1081 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
1082 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1086 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
1091 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
1100 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1102 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
1121 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_readphy() argument
1128 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1130 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1134 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1165 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1166 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1170 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1175 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) in tg3_readphy() argument
1177 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1180 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_writephy() argument
1187 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1191 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1193 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1197 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1224 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1225 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1229 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1234 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() argument
1236 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1239 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) in tg3_phy_cl45_write() argument
1243 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1247 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1251 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1256 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1262 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) in tg3_phy_cl45_read() argument
1266 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1270 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1274 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1279 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_read()
1285 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) in tg3_phydsp_read() argument
1289 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1291 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1296 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) in tg3_phydsp_write() argument
1300 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1302 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1307 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) in tg3_phy_auxctl_read() argument
1311 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1315 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); in tg3_phy_auxctl_read()
1320 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() argument
1325 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1328 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) in tg3_phy_toggle_auxctl_smdsp() argument
1333 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); in tg3_phy_toggle_auxctl_smdsp()
1343 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
1349 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) in tg3_phy_shdw_write() argument
1351 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1355 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
1364 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1370 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1388 struct tg3 *tp = bp->priv; in tg3_mdio_read() local
1391 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1393 if (__tg3_readphy(tp, mii_id, reg, &val)) in tg3_mdio_read()
1396 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1403 struct tg3 *tp = bp->priv; in tg3_mdio_write() local
1406 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1408 if (__tg3_writephy(tp, mii_id, reg, val)) in tg3_mdio_write()
1411 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1416 static void tg3_mdio_config_5785(struct tg3 *tp) in tg3_mdio_config_5785() argument
1421 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1452 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1465 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1466 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1468 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1483 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1484 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1489 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1497 static void tg3_mdio_start(struct tg3 *tp) in tg3_mdio_start() argument
1499 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1500 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1503 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1504 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_start()
1505 tg3_mdio_config_5785(tp); in tg3_mdio_start()
1508 static int tg3_mdio_init(struct tg3 *tp) in tg3_mdio_init() argument
1514 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1517 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1519 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1525 tp->phy_addr += 7; in tg3_mdio_init()
1526 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) { in tg3_mdio_init()
1529 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1532 tp->phy_addr = addr; in tg3_mdio_init()
1534 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1536 tg3_mdio_start(tp); in tg3_mdio_init()
1538 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1541 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1542 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1545 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1546 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", in tg3_mdio_init()
1547 (tp->pdev->bus->number << 8) | tp->pdev->devfn); in tg3_mdio_init()
1548 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1549 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1550 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1551 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1552 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1559 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1560 tg3_bmcr_reset(tp); in tg3_mdio_init()
1562 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1564 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1565 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1569 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1572 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1573 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1574 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1589 if (tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_init()
1591 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_init()
1593 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_init()
1603 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1607 tg3_flag_set(tp, MDIOBUS_INITED); in tg3_mdio_init()
1609 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_init()
1610 tg3_mdio_config_5785(tp); in tg3_mdio_init()
1615 static void tg3_mdio_fini(struct tg3 *tp) in tg3_mdio_fini() argument
1617 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1618 tg3_flag_clear(tp, MDIOBUS_INITED); in tg3_mdio_fini()
1619 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1620 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1625 static inline void tg3_generate_fw_event(struct tg3 *tp) in tg3_generate_fw_event() argument
1633 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1639 static void tg3_wait_for_event_ack(struct tg3 *tp) in tg3_wait_for_event_ack() argument
1646 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1661 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1669 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) in tg3_phy_gather_ump_data() argument
1674 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_phy_gather_ump_data()
1676 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_phy_gather_ump_data()
1681 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_phy_gather_ump_data()
1683 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_phy_gather_ump_data()
1688 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1689 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_phy_gather_ump_data()
1691 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_phy_gather_ump_data()
1696 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_phy_gather_ump_data()
1704 static void tg3_ump_link_report(struct tg3 *tp) in tg3_ump_link_report() argument
1708 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1711 tg3_phy_gather_ump_data(tp, data); in tg3_ump_link_report()
1713 tg3_wait_for_event_ack(tp); in tg3_ump_link_report()
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); in tg3_ump_link_report()
1716 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); in tg3_ump_link_report()
1717 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1718 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1719 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1720 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1722 tg3_generate_fw_event(tp); in tg3_ump_link_report()
1726 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1728 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1730 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1732 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); in tg3_stop_fw()
1734 tg3_generate_fw_event(tp); in tg3_stop_fw()
1737 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1742 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) in tg3_write_sig_pre_reset() argument
1744 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, in tg3_write_sig_pre_reset()
1747 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1750 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1755 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1760 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1771 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) in tg3_write_sig_post_reset() argument
1773 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1776 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1781 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1792 static void tg3_write_sig_legacy(struct tg3 *tp, int kind) in tg3_write_sig_legacy() argument
1794 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1807 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1817 static int tg3_poll_fw(struct tg3 *tp) in tg3_poll_fw() argument
1822 if (tg3_flag(tp, NO_FWARE_REPORTED)) in tg3_poll_fw()
1825 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_poll_fw()
1830 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_poll_fw()
1835 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1845 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); in tg3_poll_fw()
1848 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1849 if (!tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1850 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1851 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1865 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1866 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1868 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1871 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1881 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
1883 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1884 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1885 tg3_ump_link_report(tp); in tg3_link_report()
1886 } else if (netif_msg_link(tp)) { in tg3_link_report()
1887 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1888 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1890 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1892 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1895 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1896 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1898 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1901 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1902 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1903 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1905 tg3_ump_link_report(tp); in tg3_link_report()
1908 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1971 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) in tg3_setup_flow_control() argument
1975 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1976 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1978 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1979 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1981 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1983 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1984 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1989 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1991 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1994 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1996 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1998 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1999 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
2002 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2004 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2006 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
2007 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2014 struct tg3 *tp = netdev_priv(dev); in tg3_adjust_link() local
2015 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2017 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2019 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2022 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2031 tg3_asic_rev(tp) != ASIC_REV_5785) in tg3_adjust_link()
2040 tp->link_config.flowctrl); in tg3_adjust_link()
2048 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_adjust_link()
2052 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2053 tp->mac_mode = mac_mode; in tg3_adjust_link()
2054 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2058 if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_adjust_link()
2078 if (phydev->link != tp->old_link || in tg3_adjust_link()
2079 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2080 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2081 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2084 tp->old_link = phydev->link; in tg3_adjust_link()
2085 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2086 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2088 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2091 tg3_link_report(tp); in tg3_adjust_link()
2094 static int tg3_phy_init(struct tg3 *tp) in tg3_phy_init() argument
2098 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2102 tg3_bmcr_reset(tp); in tg3_phy_init()
2104 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2107 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2110 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2118 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2129 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2133 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2140 static void tg3_phy_start(struct tg3 *tp) in tg3_phy_start() argument
2144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2147 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2149 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2150 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2151 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2152 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2153 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2155 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2163 static void tg3_phy_stop(struct tg3 *tp) in tg3_phy_stop() argument
2165 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2168 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2171 static void tg3_phy_fini(struct tg3 *tp) in tg3_phy_fini() argument
2173 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2174 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2175 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2179 static int tg3_phy_set_extloopbk(struct tg3 *tp) in tg3_phy_set_extloopbk() argument
2184 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2187 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2189 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2196 err = tg3_phy_auxctl_read(tp, in tg3_phy_set_extloopbk()
2202 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2209 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_fet_toggle_apd() argument
2213 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
2216 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2218 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
2223 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2225 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2229 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_toggle_apd() argument
2233 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
2234 (tg3_flag(tp, 5717_PLUS) && in tg3_phy_toggle_apd()
2235 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2238 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2239 tg3_phy_fet_toggle_apd(tp, enable); in tg3_phy_toggle_apd()
2247 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); in tg3_phy_toggle_apd()
2257 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); in tg3_phy_toggle_apd()
2260 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) in tg3_phy_toggle_automdix() argument
2264 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2265 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2268 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2271 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2274 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2276 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2281 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2283 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2288 ret = tg3_phy_auxctl_read(tp, in tg3_phy_toggle_automdix()
2295 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2301 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
2306 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2309 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2311 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2315 static void tg3_phy_apply_otp(struct tg3 *tp) in tg3_phy_apply_otp() argument
2319 if (!tp->phy_otp) in tg3_phy_apply_otp()
2322 otp = tp->phy_otp; in tg3_phy_apply_otp()
2324 if (tg3_phy_toggle_auxctl_smdsp(tp, true)) in tg3_phy_apply_otp()
2329 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); in tg3_phy_apply_otp()
2333 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); in tg3_phy_apply_otp()
2337 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); in tg3_phy_apply_otp()
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); in tg3_phy_apply_otp()
2343 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); in tg3_phy_apply_otp()
2347 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); in tg3_phy_apply_otp()
2349 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_apply_otp()
2352 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee) in tg3_eee_pull_config() argument
2355 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2357 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) in tg3_eee_pull_config()
2374 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) in tg3_eee_pull_config()
2379 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) in tg3_eee_pull_config()
2392 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) in tg3_phy_eee_adjust() argument
2396 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2399 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2401 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2403 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2404 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2405 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2408 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2415 tg3_eee_pull_config(tp, NULL); in tg3_phy_eee_adjust()
2416 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2417 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2420 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2422 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_adjust()
2423 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2424 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_adjust()
2432 static void tg3_phy_eee_enable(struct tg3 *tp) in tg3_phy_eee_enable() argument
2436 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2437 (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_phy_eee_enable()
2438 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_eee_enable()
2439 tg3_flag(tp, 57765_CLASS)) && in tg3_phy_eee_enable()
2440 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_enable()
2443 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_eee_enable()
2444 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_enable()
2451 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
2458 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2469 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
2482 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2484 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2487 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2490 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2491 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2496 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2498 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2499 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2504 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2505 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2513 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2514 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2515 tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2523 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2525 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2535 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
2542 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2544 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2546 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2547 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2548 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2555 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
2564 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
2571 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2575 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2578 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2582 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2585 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2588 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_reset_5703_4_5()
2593 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2595 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
2600 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
2604 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2606 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2607 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2609 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset_5703_4_5()
2611 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2613 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
2618 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2623 static void tg3_carrier_off(struct tg3 *tp) in tg3_carrier_off() argument
2625 netif_carrier_off(tp->dev); in tg3_carrier_off()
2626 tp->link_up = false; in tg3_carrier_off()
2629 static void tg3_warn_mgmt_link_flap(struct tg3 *tp) in tg3_warn_mgmt_link_flap() argument
2631 if (tg3_flag(tp, ENABLE_ASF)) in tg3_warn_mgmt_link_flap()
2632 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2639 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
2644 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2649 err = tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2650 err |= tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2654 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2655 netif_carrier_off(tp->dev); in tg3_phy_reset()
2656 tg3_link_report(tp); in tg3_phy_reset()
2659 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_phy_reset()
2660 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_phy_reset()
2661 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_phy_reset()
2662 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
2669 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_phy_reset()
2670 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_phy_reset()
2677 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
2683 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); in tg3_phy_reset()
2688 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_phy_reset()
2689 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_phy_reset()
2699 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2700 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2703 tg3_phy_apply_otp(tp); in tg3_phy_reset()
2705 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2706 tg3_phy_toggle_apd(tp, true); in tg3_phy_reset()
2708 tg3_phy_toggle_apd(tp, false); in tg3_phy_reset()
2711 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2712 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2713 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2714 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2715 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2718 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2719 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2720 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2723 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2725 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2726 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2727 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2728 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2730 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2731 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2732 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2733 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2734 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2735 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2740 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2746 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2748 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2749 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2751 err = tg3_phy_auxctl_read(tp, in tg3_phy_reset()
2754 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
2761 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2762 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2763 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2767 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2769 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2772 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) in tg3_phy_reset()
2773 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2775 tg3_phy_toggle_automdix(tp, true); in tg3_phy_reset()
2776 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
2796 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) in tg3_set_function_status() argument
2800 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2801 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2802 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); in tg3_set_function_status()
2806 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2810 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2811 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2812 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); in tg3_set_function_status()
2819 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) in tg3_pwrsrc_switch_to_vmain() argument
2821 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2824 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2825 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_pwrsrc_switch_to_vmain()
2826 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_pwrsrc_switch_to_vmain()
2827 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2830 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); in tg3_pwrsrc_switch_to_vmain()
2832 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2835 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_pwrsrc_switch_to_vmain()
2837 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2844 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) in tg3_pwrsrc_die_with_vmain() argument
2848 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2849 tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_die_with_vmain()
2850 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_pwrsrc_die_with_vmain()
2853 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2868 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) in tg3_pwrsrc_switch_to_vaux() argument
2870 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2873 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2874 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_pwrsrc_switch_to_vaux()
2875 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2882 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2883 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2890 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2906 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2908 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2914 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2927 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2933 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2939 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2945 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) in tg3_frob_aux_power_5717() argument
2950 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2953 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2956 msg = tg3_set_function_status(tp, msg); in tg3_frob_aux_power_5717()
2962 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power_5717()
2964 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power_5717()
2967 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_frob_aux_power_5717()
2970 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) in tg3_frob_aux_power() argument
2975 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2978 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_frob_aux_power()
2979 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_frob_aux_power()
2980 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_frob_aux_power()
2981 tg3_frob_aux_power_5717(tp, include_wol ? in tg3_frob_aux_power()
2982 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
2986 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2989 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3004 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
3005 tg3_flag(tp, ENABLE_ASF)) in tg3_frob_aux_power()
3009 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power()
3011 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power()
3014 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) in tg3_5700_link_polarity() argument
3016 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3018 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3027 static bool tg3_phy_power_bug(struct tg3 *tp) in tg3_phy_power_bug() argument
3029 switch (tg3_asic_rev(tp)) { in tg3_phy_power_bug()
3034 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3038 if (!tp->pci_fn) in tg3_phy_power_bug()
3043 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3044 !tp->pci_fn) in tg3_phy_power_bug()
3052 static bool tg3_phy_led_bug(struct tg3 *tp) in tg3_phy_led_bug() argument
3054 switch (tg3_asic_rev(tp)) { in tg3_phy_led_bug()
3057 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3058 !tp->pci_fn) in tg3_phy_led_bug()
3066 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) in tg3_power_down_phy() argument
3070 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3073 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3074 if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_power_down_phy()
3086 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_phy()
3087 tg3_bmcr_reset(tp); in tg3_power_down_phy()
3092 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3094 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
3097 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3098 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3101 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3103 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
3105 tg3_writephy(tp, in tg3_power_down_phy()
3109 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3113 if (!tg3_phy_led_bug(tp)) in tg3_power_down_phy()
3114 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3120 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
3126 if (tg3_phy_power_bug(tp)) in tg3_power_down_phy()
3129 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_power_down_phy()
3130 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_power_down_phy()
3137 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
3141 static int tg3_nvram_lock(struct tg3 *tp) in tg3_nvram_lock() argument
3143 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
3146 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3158 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3164 static void tg3_nvram_unlock(struct tg3 *tp) in tg3_nvram_unlock() argument
3166 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
3167 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3168 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3169 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3175 static void tg3_enable_nvram_access(struct tg3 *tp) in tg3_enable_nvram_access() argument
3177 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
3185 static void tg3_disable_nvram_access(struct tg3 *tp) in tg3_disable_nvram_access() argument
3187 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
3194 static int tg3_nvram_read_using_eeprom(struct tg3 *tp, in tg3_nvram_read_using_eeprom() argument
3236 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) in tg3_nvram_exec_cmd() argument
3255 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) in tg3_nvram_phys_addr() argument
3257 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
3258 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_phys_addr()
3259 tg3_flag(tp, FLASH) && in tg3_nvram_phys_addr()
3260 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_phys_addr()
3261 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3263 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3265 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3270 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) in tg3_nvram_logical_addr() argument
3272 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
3273 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_logical_addr()
3274 tg3_flag(tp, FLASH) && in tg3_nvram_logical_addr()
3275 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_logical_addr()
3276 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3279 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3291 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_nvram_read() argument
3295 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
3296 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
3298 offset = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_read()
3303 ret = tg3_nvram_lock(tp); in tg3_nvram_read()
3307 tg3_enable_nvram_access(tp); in tg3_nvram_read()
3310 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | in tg3_nvram_read()
3316 tg3_disable_nvram_access(tp); in tg3_nvram_read()
3318 tg3_nvram_unlock(tp); in tg3_nvram_read()
3324 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) in tg3_nvram_read_be32() argument
3327 int res = tg3_nvram_read(tp, offset, &v); in tg3_nvram_read_be32()
3333 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, in tg3_nvram_write_block_using_eeprom() argument
3383 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_unbuffered() argument
3387 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3403 ret = tg3_nvram_read_be32(tp, phy_addr + j, in tg3_nvram_write_block_unbuffered()
3422 tg3_enable_nvram_access(tp); in tg3_nvram_write_block_unbuffered()
3430 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3439 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3445 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3465 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3474 tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3482 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_buffered() argument
3494 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3496 phy_addr = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_write_block_buffered()
3502 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3509 !tg3_flag(tp, FLASH) || in tg3_nvram_write_block_buffered()
3510 !tg3_flag(tp, 57765_PLUS)) in tg3_nvram_write_block_buffered()
3513 if (tg3_asic_rev(tp) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
3514 !tg3_flag(tp, 5755_PLUS) && in tg3_nvram_write_block_buffered()
3515 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3520 ret = tg3_nvram_exec_cmd(tp, cmd); in tg3_nvram_write_block_buffered()
3524 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
3529 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_buffered()
3537 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) in tg3_nvram_write_block() argument
3541 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3542 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3547 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
3548 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); in tg3_nvram_write_block()
3552 ret = tg3_nvram_lock(tp); in tg3_nvram_write_block()
3556 tg3_enable_nvram_access(tp); in tg3_nvram_write_block()
3557 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
3563 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
3564 ret = tg3_nvram_write_block_buffered(tp, offset, len, in tg3_nvram_write_block()
3567 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, in tg3_nvram_write_block()
3574 tg3_disable_nvram_access(tp); in tg3_nvram_write_block()
3575 tg3_nvram_unlock(tp); in tg3_nvram_write_block()
3578 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3579 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3592 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3602 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3610 static int tg3_rxcpu_pause(struct tg3 *tp) in tg3_rxcpu_pause() argument
3612 int rc = tg3_pause_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_pause()
3622 static int tg3_txcpu_pause(struct tg3 *tp) in tg3_txcpu_pause() argument
3624 return tg3_pause_cpu(tp, TX_CPU_BASE); in tg3_txcpu_pause()
3628 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3635 static void tg3_rxcpu_resume(struct tg3 *tp) in tg3_rxcpu_resume() argument
3637 tg3_resume_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_resume()
3641 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3645 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3647 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_halt_cpu()
3654 rc = tg3_rxcpu_pause(tp); in tg3_halt_cpu()
3660 if (tg3_flag(tp, IS_SSB_CORE)) in tg3_halt_cpu()
3663 rc = tg3_txcpu_pause(tp); in tg3_halt_cpu()
3667 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3673 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3678 static int tg3_fw_data_len(struct tg3 *tp, in tg3_fw_data_len() argument
3697 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3700 fw_len = tp->fw->size; in tg3_fw_data_len()
3706 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, in tg3_load_firmware_cpu() argument
3712 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3714 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3715 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3721 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) in tg3_load_firmware_cpu()
3726 if (tg3_asic_rev(tp) != ASIC_REV_57766) { in tg3_load_firmware_cpu()
3730 int lock_err = tg3_nvram_lock(tp); in tg3_load_firmware_cpu()
3731 err = tg3_halt_cpu(tp, cpu_base); in tg3_load_firmware_cpu()
3733 tg3_nvram_unlock(tp); in tg3_load_firmware_cpu()
3738 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3752 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3753 write_op(tp, cpu_scratch_base + in tg3_load_firmware_cpu()
3772 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) in tg3_pause_cpu_and_set_pc() argument
3793 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) in tg3_load_5701_a0_firmware_fix() argument
3798 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3806 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3812 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3819 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3822 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3829 tg3_rxcpu_resume(tp); in tg3_load_5701_a0_firmware_fix()
3834 static int tg3_validate_rxcpu_state(struct tg3 *tp) in tg3_validate_rxcpu_state() argument
3851 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3855 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); in tg3_validate_rxcpu_state()
3857 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3866 static void tg3_load_57766_firmware(struct tg3 *tp) in tg3_load_57766_firmware() argument
3870 if (!tg3_flag(tp, NO_NVRAM)) in tg3_load_57766_firmware()
3873 if (tg3_validate_rxcpu_state(tp)) in tg3_load_57766_firmware()
3876 if (!tp->fw) in tg3_load_57766_firmware()
3893 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3897 if (tg3_rxcpu_pause(tp)) in tg3_load_57766_firmware()
3901 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3903 tg3_rxcpu_resume(tp); in tg3_load_57766_firmware()
3907 static int tg3_load_tso_firmware(struct tg3 *tp) in tg3_load_tso_firmware() argument
3913 if (!tg3_flag(tp, FW_TSO)) in tg3_load_tso_firmware()
3916 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3924 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3926 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3935 err = tg3_load_firmware_cpu(tp, cpu_base, in tg3_load_tso_firmware()
3942 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, in tg3_load_tso_firmware()
3945 netdev_err(tp->dev, in tg3_load_tso_firmware()
3952 tg3_resume_cpu(tp, cpu_base); in tg3_load_tso_firmware()
3957 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index) in __tg3_set_one_mac_addr() argument
3976 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) in __tg3_set_mac_addr() argument
3984 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3987 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3988 tg3_asic_rev(tp) == ASIC_REV_5704) { in __tg3_set_mac_addr()
3990 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3993 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3994 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3995 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3996 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3997 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3998 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
4003 static void tg3_enable_register_access(struct tg3 *tp) in tg3_enable_register_access() argument
4009 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4010 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4013 static int tg3_power_up(struct tg3 *tp) in tg3_power_up() argument
4017 tg3_enable_register_access(tp); in tg3_power_up()
4019 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4022 tg3_pwrsrc_switch_to_vmain(tp); in tg3_power_up()
4024 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4032 static int tg3_power_down_prepare(struct tg3 *tp) in tg3_power_down_prepare() argument
4037 tg3_enable_register_access(tp); in tg3_power_down_prepare()
4040 if (tg3_flag(tp, CLKREQ_BUG)) in tg3_power_down_prepare()
4041 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4048 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4049 tg3_flag(tp, WOL_ENABLE); in tg3_power_down_prepare()
4051 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
4053 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4054 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4059 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4061 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4063 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4064 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4065 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4067 &tp->link_config.advertising, in tg3_power_down_prepare()
4078 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
4079 if (tg3_flag(tp, WOL_SPEED_100MB)) { in tg3_power_down_prepare()
4107 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4108 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4110 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4111 tg3_setup_phy(tp, false); in tg3_power_down_prepare()
4114 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4119 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4124 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); in tg3_power_down_prepare()
4130 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
4131 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | in tg3_power_down_prepare()
4139 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4141 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4142 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4150 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4152 else if (tp->phy_flags & in tg3_power_down_prepare()
4154 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4161 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4162 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_power_down_prepare()
4163 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? in tg3_power_down_prepare()
4165 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
4174 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
4175 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4178 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
4179 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) in tg3_power_down_prepare()
4182 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
4194 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
4195 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4196 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_power_down_prepare()
4199 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4205 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
4206 tg3_flag(tp, CPMU_PRESENT) || in tg3_power_down_prepare()
4207 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4209 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
4212 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4213 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4218 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4226 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4229 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4232 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4235 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4236 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4245 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4249 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
4250 tg3_power_down_phy(tp, do_low_power); in tg3_power_down_prepare()
4252 tg3_frob_aux_power(tp, true); in tg3_power_down_prepare()
4255 if ((!tg3_flag(tp, IS_SSB_CORE)) && in tg3_power_down_prepare()
4256 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
4257 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { in tg3_power_down_prepare()
4262 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4265 err = tg3_nvram_lock(tp); in tg3_power_down_prepare()
4266 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_power_down_prepare()
4268 tg3_nvram_unlock(tp); in tg3_power_down_prepare()
4272 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4274 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4279 static void tg3_power_down(struct tg3 *tp) in tg3_power_down() argument
4281 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4282 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4285 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) in tg3_aux_stat_to_speed_duplex() argument
4319 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4332 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) in tg3_phy_autoneg_cfg() argument
4341 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4345 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4348 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
4349 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) in tg3_phy_autoneg_cfg()
4352 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4357 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4363 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_autoneg_cfg()
4375 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4377 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4379 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4384 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); in tg3_phy_autoneg_cfg()
4388 switch (tg3_asic_rev(tp)) { in tg3_phy_autoneg_cfg()
4398 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_autoneg_cfg()
4402 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
4403 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | in tg3_phy_autoneg_cfg()
4407 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_autoneg_cfg()
4416 static void tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
4418 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4419 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4422 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4423 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4426 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
4429 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4430 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4438 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4439 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4443 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4446 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4448 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4449 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4457 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4463 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4464 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4466 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_phy_copper_begin()
4471 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4475 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4489 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4492 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
4494 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4499 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
4500 tg3_readphy(tp, MII_BMSR, &tmp)) in tg3_phy_copper_begin()
4507 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4513 static int tg3_phy_pull_config(struct tg3 *tp) in tg3_phy_pull_config() argument
4518 err = tg3_readphy(tp, MII_BMCR, &val); in tg3_phy_pull_config()
4523 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4524 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4525 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4531 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4537 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4540 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4543 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4544 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4553 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4555 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4557 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4563 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4564 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4565 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4570 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4575 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4577 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4579 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4582 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4585 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4586 err = tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_pull_config()
4592 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4597 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4603 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4610 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
4616 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4618 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4619 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4620 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4621 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4622 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4629 static bool tg3_phy_eee_config_ok(struct tg3 *tp) in tg3_phy_eee_config_ok() argument
4633 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4636 tg3_eee_pull_config(tp, &eee); in tg3_phy_eee_config_ok()
4638 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4639 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4640 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4641 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4652 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) in tg3_phy_copper_an_config_ok() argument
4656 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4660 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4661 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4665 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
4671 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4676 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
4680 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_copper_an_config_ok()
4681 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_an_config_ok()
4696 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) in tg3_phy_copper_fetch_rmtadv() argument
4700 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4703 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
4709 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
4713 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4718 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) in tg3_test_and_report_link_chg() argument
4720 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4722 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4724 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4725 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4726 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4729 tg3_link_report(tp); in tg3_test_and_report_link_chg()
4736 static void tg3_clear_mac_status(struct tg3 *tp) in tg3_clear_mac_status() argument
4748 static void tg3_setup_eee(struct tg3 *tp) in tg3_setup_eee() argument
4754 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_setup_eee()
4763 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4767 if (tg3_asic_rev(tp) != ASIC_REV_5717) in tg3_setup_eee()
4770 if (tg3_flag(tp, ENABLE_APE)) in tg3_setup_eee()
4773 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4777 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4784 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) in tg3_setup_copper_phy() argument
4793 tg3_clear_mac_status(tp); in tg3_setup_copper_phy()
4795 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4797 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4801 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4806 if ((tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_setup_copper_phy()
4807 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_setup_copper_phy()
4808 tg3_asic_rev(tp) == ASIC_REV_5705) && in tg3_setup_copper_phy()
4809 tp->link_up) { in tg3_setup_copper_phy()
4810 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4811 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4816 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4818 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4819 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4820 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
4821 !tg3_flag(tp, INIT_COMPLETE)) in tg3_setup_copper_phy()
4825 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4829 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4832 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4839 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4842 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4843 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
4845 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4850 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
4851 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
4853 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4854 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4855 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4856 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4860 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4861 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4863 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4864 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4865 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4866 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4868 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_setup_copper_phy()
4869 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_setup_copper_phy()
4870 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4871 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4874 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4880 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4881 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4883 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4884 err = tg3_phy_auxctl_read(tp, in tg3_setup_copper_phy()
4888 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()
4897 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4898 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4907 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
4910 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
4915 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
4921 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
4922 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
4932 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4933 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4935 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4936 bool eee_config_ok = tg3_phy_eee_config_ok(tp); in tg3_setup_copper_phy()
4940 tg3_phy_copper_an_config_ok(tp, &lcl_adv) && in tg3_setup_copper_phy()
4941 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) in tg3_setup_copper_phy()
4949 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4951 tg3_setup_eee(tp); in tg3_setup_copper_phy()
4952 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4956 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4957 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4963 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4966 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4974 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4975 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4977 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_setup_copper_phy()
4982 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4983 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
4985 if (tg3_flag(tp, ROBOSWITCH)) { in tg3_setup_copper_phy()
4990 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4991 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4994 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4995 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4996 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
5000 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
5002 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5003 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5004 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5006 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5007 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
5008 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5010 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5015 if (tg3_flag(tp, RGMII_MODE)) { in tg3_setup_copper_phy()
5019 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5021 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5024 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5032 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5033 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5034 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5036 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_setup_copper_phy()
5038 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5039 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5041 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5047 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5048 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
5049 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5050 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5054 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5057 tg3_phy_eee_adjust(tp, current_link_up); in tg3_setup_copper_phy()
5059 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
5067 if (tg3_asic_rev(tp) == ASIC_REV_5700 && in tg3_setup_copper_phy()
5069 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5070 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
5076 tg3_write_mem(tp, in tg3_setup_copper_phy()
5082 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
5083 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5084 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5085 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5088 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5092 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_copper_phy()
5161 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
5241 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5242 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5264 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5270 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5271 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5285 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5286 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5371 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5372 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5413 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) in fiber_autoneg() argument
5423 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5427 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5436 status = tg3_fiber_aneg_smachine(tp, &aninfo); in fiber_autoneg()
5443 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5444 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5458 static void tg3_init_bcm8002(struct tg3 *tp) in tg3_init_bcm8002() argument
5464 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
5469 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5472 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5480 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5483 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5485 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5486 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5489 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5491 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5493 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5495 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5505 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5508 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_hw_autoneg() argument
5522 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
5523 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { in tg3_setup_fiber_hw_autoneg()
5535 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5550 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5559 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5566 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5567 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5571 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5582 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5583 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5603 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5606 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_hw_autoneg()
5608 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5609 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5611 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5612 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5634 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5636 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5638 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5645 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5646 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5653 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_by_hand() argument
5660 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5664 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
5677 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5680 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_by_hand()
5702 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5707 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5710 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5718 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_phy() argument
5727 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5728 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5729 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5731 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
5732 tp->link_up && in tg3_setup_fiber_phy()
5733 tg3_flag(tp, INIT_COMPLETE)) { in tg3_setup_fiber_phy()
5749 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5750 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5751 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5754 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5755 tg3_init_bcm8002(tp); in tg3_setup_fiber_phy()
5762 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5765 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
5766 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); in tg3_setup_fiber_phy()
5768 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); in tg3_setup_fiber_phy()
5770 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5772 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5787 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5788 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5789 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5792 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5797 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5798 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5799 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5803 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5804 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5805 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5810 if (!tg3_test_and_report_link_chg(tp, current_link_up)) { in tg3_setup_fiber_phy()
5811 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5813 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5814 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5815 tg3_link_report(tp); in tg3_setup_fiber_phy()
5821 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_mii_phy() argument
5830 if ((tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_setup_fiber_mii_phy()
5831 tg3_asic_rev(tp) == ASIC_REV_5720) && in tg3_setup_fiber_mii_phy()
5832 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && in tg3_setup_fiber_mii_phy()
5836 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5838 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5841 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5846 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5849 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5852 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5861 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5864 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5869 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5870 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5873 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5876 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5878 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5880 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5881 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5882 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5889 err |= tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_fiber_mii_phy()
5891 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5892 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5894 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5897 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5903 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5904 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5907 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5909 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5912 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5913 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5923 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5933 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5936 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5940 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5941 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5945 tg3_carrier_off(tp); in tg3_setup_fiber_mii_phy()
5947 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
5949 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5950 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5951 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5957 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5975 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_fiber_mii_phy()
5976 err |= tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_fiber_mii_phy()
5985 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5987 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
5997 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_mii_phy()
5999 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
6000 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
6001 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
6003 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
6008 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
6009 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6011 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_fiber_mii_phy()
6015 static void tg3_serdes_parallel_detect(struct tg3 *tp) in tg3_serdes_parallel_detect() argument
6017 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6019 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6023 if (!tp->link_up && in tg3_serdes_parallel_detect()
6024 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6027 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6032 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6033 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6036 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6038 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6039 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6049 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6050 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6053 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6054 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6055 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6059 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6061 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6066 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6067 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
6069 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6075 static int tg3_setup_phy(struct tg3 *tp, bool force_reset) in tg3_setup_phy() argument
6080 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6081 err = tg3_setup_fiber_phy(tp, force_reset); in tg3_setup_phy()
6082 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6083 err = tg3_setup_fiber_mii_phy(tp, force_reset); in tg3_setup_phy()
6085 err = tg3_setup_copper_phy(tp, force_reset); in tg3_setup_phy()
6087 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_setup_phy()
6105 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_setup_phy()
6106 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_setup_phy()
6111 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6112 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6119 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
6120 if (tp->link_up) { in tg3_setup_phy()
6122 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6128 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
6130 if (!tp->link_up) in tg3_setup_phy()
6132 tp->pwrmgmt_thresh; in tg3_setup_phy()
6142 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts) in tg3_refclk_read() argument
6155 static void tg3_refclk_write(struct tg3 *tp, u64 newval) in tg3_refclk_write() argument
6165 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6166 static inline void tg3_full_unlock(struct tg3 *tp);
6169 struct tg3 *tp = netdev_priv(dev); in tg3_get_ts_info() local
6175 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_get_ts_info()
6181 if (tp->ptp_clock) in tg3_get_ts_info()
6182 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6197 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjfreq() local
6217 tg3_full_lock(tp, 0); in tg3_ptp_adjfreq()
6226 tg3_full_unlock(tp); in tg3_ptp_adjfreq()
6233 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjtime() local
6235 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6236 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6237 tg3_full_unlock(tp); in tg3_ptp_adjtime()
6246 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_gettimex() local
6248 tg3_full_lock(tp, 0); in tg3_ptp_gettimex()
6249 ns = tg3_refclk_read(tp, sts); in tg3_ptp_gettimex()
6250 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6251 tg3_full_unlock(tp); in tg3_ptp_gettimex()
6262 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_settime() local
6266 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6267 tg3_refclk_write(tp, ns); in tg3_ptp_settime()
6268 tp->ptp_adjust = 0; in tg3_ptp_settime()
6269 tg3_full_unlock(tp); in tg3_ptp_settime()
6277 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_enable() local
6290 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6301 netdev_warn(tp->dev, in tg3_ptp_enable()
6308 netdev_warn(tp->dev, in tg3_ptp_enable()
6327 tg3_full_unlock(tp); in tg3_ptp_enable()
6353 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, in tg3_hwclock_to_timestamp() argument
6358 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6362 static void tg3_ptp_init(struct tg3 *tp) in tg3_ptp_init() argument
6364 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_init()
6368 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); in tg3_ptp_init()
6369 tp->ptp_adjust = 0; in tg3_ptp_init()
6370 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6374 static void tg3_ptp_resume(struct tg3 *tp) in tg3_ptp_resume() argument
6376 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_resume()
6379 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6380 tp->ptp_adjust = 0; in tg3_ptp_resume()
6383 static void tg3_ptp_fini(struct tg3 *tp) in tg3_ptp_fini() argument
6385 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6388 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6389 tp->ptp_clock = NULL; in tg3_ptp_fini()
6390 tp->ptp_adjust = 0; in tg3_ptp_fini()
6393 static inline int tg3_irq_sync(struct tg3 *tp) in tg3_irq_sync() argument
6395 return tp->irq_sync; in tg3_irq_sync()
6398 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) in tg3_rd32_loop() argument
6407 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) in tg3_dump_legacy_regs() argument
6409 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6410 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6411 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6412 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6413 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6414 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6418 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6419 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6420 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6421 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6422 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6423 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6425 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6426 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6427 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6429 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
6430 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6432 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6433 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6434 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6435 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6436 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6437 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6438 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6439 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6441 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
6442 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6443 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6444 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6447 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6448 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6449 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6450 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6451 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6453 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
6454 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6457 static void tg3_dump_state(struct tg3 *tp) in tg3_dump_state() argument
6466 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
6471 tg3_dump_legacy_regs(tp, regs); in tg3_dump_state()
6478 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6485 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6486 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6489 netdev_err(tp->dev, in tg3_dump_state()
6500 netdev_err(tp->dev, in tg3_dump_state()
6519 static void tg3_tx_recover(struct tg3 *tp) in tg3_tx_recover() argument
6521 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_tx_recover()
6522 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6524 netdev_warn(tp->dev, in tg3_tx_recover()
6530 tg3_flag_set(tp, TX_RECOVERY_PENDING); in tg3_tx_recover()
6547 struct tg3 *tp = tnapi->tp; in tg3_tx() local
6551 int index = tnapi - tp->napi; in tg3_tx()
6554 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
6557 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6565 tg3_tx_recover(tp); in tg3_tx()
6574 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_tx()
6579 pci_unmap_single(tp->pdev, in tg3_tx()
6599 pci_unmap_page(tp->pdev, in tg3_tx()
6619 tg3_tx_recover(tp); in tg3_tx()
6653 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) in tg3_rx_data_free() argument
6655 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + in tg3_rx_data_free()
6661 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), in tg3_rx_data_free()
6679 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, in tg3_alloc_rx_data() argument
6691 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6694 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6698 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6714 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + in tg3_alloc_rx_data()
6726 mapping = pci_map_single(tp->pdev, in tg3_alloc_rx_data()
6727 data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6730 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { in tg3_alloc_rx_data()
6753 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx() local
6756 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6761 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6769 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6820 struct tg3 *tp = tnapi->tp; in tg3_rx() local
6851 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6857 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6872 tp->rx_dropped++; in tg3_rx()
6876 prefetch(data + TG3_RX_OFFSET(tp)); in tg3_rx()
6888 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
6892 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, in tg3_rx()
6897 pci_unmap_single(tp->pdev, dma_addr, skb_size, in tg3_rx()
6912 skb_reserve(skb, TG3_RX_OFFSET(tp)); in tg3_rx()
6917 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6923 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6925 data + TG3_RX_OFFSET(tp), in tg3_rx()
6927 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6932 tg3_hwclock_to_timestamp(tp, tstamp, in tg3_rx()
6935 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6943 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6945 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6953 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6965 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6967 tp->rx_std_ring_mask; in tg3_rx()
6975 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6989 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
6995 tp->rx_std_ring_mask; in tg3_rx()
7001 tp->rx_jmb_ring_mask; in tg3_rx()
7011 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7012 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7014 if (tnapi != &tp->napi[1]) { in tg3_rx()
7015 tp->rx_refill = true; in tg3_rx()
7016 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7023 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
7026 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
7027 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7032 spin_lock(&tp->lock); in tg3_poll_link()
7033 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
7041 tg3_setup_phy(tp, false); in tg3_poll_link()
7042 spin_unlock(&tp->lock); in tg3_poll_link()
7047 static int tg3_rx_prodring_xfer(struct tg3 *tp, in tg3_rx_prodring_xfer() argument
7068 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7072 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7107 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7109 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7126 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7130 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7165 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7167 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7175 struct tg3 *tp = tnapi->tp; in tg3_poll_work() local
7180 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
7194 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7195 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7200 tp->rx_refill = false; in tg3_poll_work()
7201 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7202 err |= tg3_rx_prodring_xfer(tp, dpr, in tg3_poll_work()
7203 &tp->napi[i].prodring); in tg3_poll_work()
7216 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7222 static inline void tg3_reset_task_schedule(struct tg3 *tp) in tg3_reset_task_schedule() argument
7224 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7225 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7228 static inline void tg3_reset_task_cancel(struct tg3 *tp) in tg3_reset_task_cancel() argument
7230 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7231 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task_cancel()
7232 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task_cancel()
7238 struct tg3 *tp = tnapi->tp; in tg3_poll_msix() local
7245 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
7266 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7276 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7277 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7285 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll_msix()
7291 tg3_reset_task_schedule(tp); in tg3_poll_msix()
7295 static void tg3_process_error(struct tg3 *tp) in tg3_process_error() argument
7300 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
7306 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7311 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7316 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7323 tg3_dump_state(tp); in tg3_process_error()
7325 tg3_flag_set(tp, ERROR_PROCESSED); in tg3_process_error()
7326 tg3_reset_task_schedule(tp); in tg3_process_error()
7332 struct tg3 *tp = tnapi->tp; in tg3_poll() local
7338 tg3_process_error(tp); in tg3_poll()
7340 tg3_poll_link(tp); in tg3_poll()
7344 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
7350 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
7368 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll()
7374 tg3_reset_task_schedule(tp); in tg3_poll()
7378 static void tg3_napi_disable(struct tg3 *tp) in tg3_napi_disable() argument
7382 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7383 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7386 static void tg3_napi_enable(struct tg3 *tp) in tg3_napi_enable() argument
7390 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7391 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7394 static void tg3_napi_init(struct tg3 *tp) in tg3_napi_init() argument
7398 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); in tg3_napi_init()
7399 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7400 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); in tg3_napi_init()
7403 static void tg3_napi_fini(struct tg3 *tp) in tg3_napi_fini() argument
7407 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7408 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7411 static inline void tg3_netif_stop(struct tg3 *tp) in tg3_netif_stop() argument
7413 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7414 tg3_napi_disable(tp); in tg3_netif_stop()
7415 netif_carrier_off(tp->dev); in tg3_netif_stop()
7416 netif_tx_disable(tp->dev); in tg3_netif_stop()
7420 static inline void tg3_netif_start(struct tg3 *tp) in tg3_netif_start() argument
7422 tg3_ptp_resume(tp); in tg3_netif_start()
7428 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7430 if (tp->link_up) in tg3_netif_start()
7431 netif_carrier_on(tp->dev); in tg3_netif_start()
7433 tg3_napi_enable(tp); in tg3_netif_start()
7434 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7435 tg3_enable_ints(tp); in tg3_netif_start()
7438 static void tg3_irq_quiesce(struct tg3 *tp) in tg3_irq_quiesce() argument
7439 __releases(tp->lock) in tg3_irq_quiesce()
7440 __acquires(tp->lock) in tg3_irq_quiesce()
7444 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7446 tp->irq_sync = 1; in tg3_irq_quiesce()
7449 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7451 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7452 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7454 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7462 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) in tg3_full_lock() argument
7464 spin_lock_bh(&tp->lock); in tg3_full_lock()
7466 tg3_irq_quiesce(tp); in tg3_full_lock()
7469 static inline void tg3_full_unlock(struct tg3 *tp) in tg3_full_unlock() argument
7471 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7480 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot() local
7486 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
7499 struct tg3 *tp = tnapi->tp; in tg3_msi() local
7512 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
7521 struct tg3 *tp = tnapi->tp; in tg3_interrupt() local
7531 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
7550 if (tg3_irq_sync(tp)) in tg3_interrupt()
7570 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged() local
7580 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
7608 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
7623 struct tg3 *tp = tnapi->tp; in tg3_test_isr() local
7628 tg3_disable_ints(tp); in tg3_test_isr()
7638 struct tg3 *tp = netdev_priv(dev); in tg3_poll_controller() local
7640 if (tg3_irq_sync(tp)) in tg3_poll_controller()
7643 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7644 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7650 struct tg3 *tp = netdev_priv(dev); in tg3_tx_timeout() local
7652 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
7654 tg3_dump_state(tp); in tg3_tx_timeout()
7657 tg3_reset_task_schedule(tp); in tg3_tx_timeout()
7671 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_4g_tso_overflow_test() argument
7674 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) { in tg3_4g_tso_overflow_test()
7683 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_40bit_overflow_test() argument
7687 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
7709 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set() local
7712 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
7718 if (tg3_4g_tso_overflow_test(tp, map, len, mss)) in tg3_tx_frag_set()
7721 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
7724 if (tp->dma_limit) { in tg3_tx_frag_set()
7727 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7728 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7729 len -= tp->dma_limit; in tg3_tx_frag_set()
7733 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7734 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7777 pci_unmap_single(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7794 pci_unmap_page(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7812 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround() local
7817 if (tg3_asic_rev(tp) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
7831 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, in tigon3_dma_hwbug_workaround()
7834 if (pci_dma_mapping_error(tp->pdev, new_addr)) { in tigon3_dma_hwbug_workaround()
7874 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, in tg3_tso_bug() argument
7896 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7905 tg3_start_xmit(nskb, tp->dev); in tg3_tso_bug()
7917 struct tg3 *tp = netdev_priv(dev); in tg3_start_xmit() local
7931 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7932 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
7974 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7980 tg3_flag(tp, TSO_BUG)) { in tg3_start_xmit()
7982 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7997 if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
7998 tg3_flag(tp, HW_TSO_2) || in tg3_start_xmit()
7999 tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
8007 if (tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
8012 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_start_xmit()
8014 else if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
8015 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_start_xmit()
8043 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_start_xmit()
8053 tg3_flag(tp, TX_TSTAMP_EN)) { in tg3_start_xmit()
8060 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); in tg3_start_xmit()
8061 if (pci_dma_mapping_error(tp->pdev, mapping)) in tg3_start_xmit()
8070 if (tg3_flag(tp, 5701_DMA_BUG)) in tg3_start_xmit()
8080 if (!tg3_flag(tp, HW_TSO_1) && in tg3_start_xmit()
8081 !tg3_flag(tp, HW_TSO_2) && in tg3_start_xmit()
8082 !tg3_flag(tp, HW_TSO_3)) in tg3_start_xmit()
8093 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8099 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8125 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
8171 tp->tx_dropped++; in tg3_start_xmit()
8175 static void tg3_mac_loopback(struct tg3 *tp, bool enable) in tg3_mac_loopback() argument
8178 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8181 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8183 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
8184 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8186 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8187 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8189 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8191 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8193 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
8194 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8195 tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_mac_loopback()
8196 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8199 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8203 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) in tg3_phy_lpbk_set() argument
8207 tg3_phy_toggle_apd(tp, false); in tg3_phy_lpbk_set()
8208 tg3_phy_toggle_automdix(tp, false); in tg3_phy_lpbk_set()
8210 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
8222 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8232 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8233 tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_lpbk_set()
8236 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8240 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8245 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8248 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8249 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_phy_lpbk_set()
8253 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8254 tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_phy_lpbk_set()
8255 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8260 tg3_readphy(tp, MII_TG3_FET_PTEST, &val); in tg3_phy_lpbk_set()
8264 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8265 tg3_flag(tp, 5780_CLASS)) { in tg3_phy_lpbk_set()
8268 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8271 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8278 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
8279 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8286 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
8298 struct tg3 *tp = netdev_priv(dev); in tg3_set_loopback() local
8301 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8304 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8305 tg3_mac_loopback(tp, true); in tg3_set_loopback()
8306 netif_carrier_on(tp->dev); in tg3_set_loopback()
8307 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8310 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8313 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8314 tg3_mac_loopback(tp, false); in tg3_set_loopback()
8316 tg3_setup_phy(tp, true); in tg3_set_loopback()
8317 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8325 struct tg3 *tp = netdev_priv(dev); in tg3_fix_features() local
8327 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8343 static void tg3_rx_prodring_free(struct tg3 *tp, in tg3_rx_prodring_free() argument
8348 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8350 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8351 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8352 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8354 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
8357 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8358 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8366 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8367 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8368 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8370 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
8371 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8372 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8384 static int tg3_rx_prodring_alloc(struct tg3 *tp, in tg3_rx_prodring_alloc() argument
8394 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8396 TG3_RX_STD_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8399 TG3_RX_JMB_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8404 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8407 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
8408 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8410 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8416 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8427 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8430 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, in tg3_rx_prodring_alloc()
8432 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8435 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8438 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8443 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
8446 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8448 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
8451 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8462 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8465 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, in tg3_rx_prodring_alloc()
8467 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8470 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8473 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8482 tg3_rx_prodring_free(tp, tpr); in tg3_rx_prodring_alloc()
8486 static void tg3_rx_prodring_fini(struct tg3 *tp, in tg3_rx_prodring_fini() argument
8494 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8499 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8505 static int tg3_rx_prodring_init(struct tg3 *tp, in tg3_rx_prodring_init() argument
8508 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8513 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8514 TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_init()
8520 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
8521 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8526 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8527 TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_init()
8537 tg3_rx_prodring_fini(tp, tpr); in tg3_rx_prodring_init()
8548 static void tg3_free_rings(struct tg3 *tp) in tg3_free_rings() argument
8552 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8553 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8555 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8571 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8582 static int tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
8587 tg3_free_rings(tp); in tg3_init_rings()
8589 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8590 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8605 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8608 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8609 tg3_free_rings(tp); in tg3_init_rings()
8617 static void tg3_mem_tx_release(struct tg3 *tp) in tg3_mem_tx_release() argument
8621 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8622 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8625 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8635 static int tg3_mem_tx_acquire(struct tg3 *tp) in tg3_mem_tx_acquire() argument
8638 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8643 if (tg3_flag(tp, ENABLE_TSS)) in tg3_mem_tx_acquire()
8646 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8653 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8664 tg3_mem_tx_release(tp); in tg3_mem_tx_acquire()
8668 static void tg3_mem_rx_release(struct tg3 *tp) in tg3_mem_rx_release() argument
8672 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8673 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8675 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8680 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8681 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_release()
8688 static int tg3_mem_rx_acquire(struct tg3 *tp) in tg3_mem_rx_acquire() argument
8692 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8697 if (tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8701 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8703 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8710 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8713 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8714 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_acquire()
8724 tg3_mem_rx_release(tp); in tg3_mem_rx_acquire()
8732 static void tg3_free_consistent(struct tg3 *tp) in tg3_free_consistent() argument
8736 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8737 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8740 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8747 tg3_mem_rx_release(tp); in tg3_free_consistent()
8748 tg3_mem_tx_release(tp); in tg3_free_consistent()
8754 if (tp->hw_stats) { in tg3_free_consistent()
8755 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8756 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8757 tp->hw_stats = NULL; in tg3_free_consistent()
8765 static int tg3_alloc_consistent(struct tg3 *tp) in tg3_alloc_consistent() argument
8769 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8771 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8772 if (!tp->hw_stats) in tg3_alloc_consistent()
8775 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8776 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8779 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8788 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_alloc_consistent()
8817 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) in tg3_alloc_consistent()
8823 tg3_free_consistent(tp); in tg3_alloc_consistent()
8832 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8837 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
8859 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8860 dev_err(&tp->pdev->dev, in tg3_stop_block()
8874 dev_err(&tp->pdev->dev, in tg3_stop_block()
8884 static int tg3_abort_hw(struct tg3 *tp, bool silent) in tg3_abort_hw() argument
8888 tg3_disable_ints(tp); in tg3_abort_hw()
8890 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8891 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8892 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8897 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8898 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8901 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8902 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); in tg3_abort_hw()
8903 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); in tg3_abort_hw()
8904 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8905 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); in tg3_abort_hw()
8906 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); in tg3_abort_hw()
8908 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); in tg3_abort_hw()
8909 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8910 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); in tg3_abort_hw()
8911 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8912 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); in tg3_abort_hw()
8913 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8914 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); in tg3_abort_hw()
8916 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8917 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8920 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8921 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8929 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8935 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); in tg3_abort_hw()
8936 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8937 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); in tg3_abort_hw()
8942 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); in tg3_abort_hw()
8943 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); in tg3_abort_hw()
8946 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8947 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8956 static void tg3_save_pci_state(struct tg3 *tp) in tg3_save_pci_state() argument
8958 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8962 static void tg3_restore_pci_state(struct tg3 *tp) in tg3_restore_pci_state() argument
8967 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8968 tp->misc_host_ctrl); in tg3_restore_pci_state()
8972 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
8973 tg3_flag(tp, PCIX_MODE)) in tg3_restore_pci_state()
8976 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
8980 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8982 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8984 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
8985 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8986 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8987 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8988 tp->pci_lat_timer); in tg3_restore_pci_state()
8992 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
8995 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8998 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
9002 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
9007 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
9010 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9011 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9013 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9014 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9022 static void tg3_override_clk(struct tg3 *tp) in tg3_override_clk() argument
9026 switch (tg3_asic_rev(tp)) { in tg3_override_clk()
9043 static void tg3_restore_clk(struct tg3 *tp) in tg3_restore_clk() argument
9047 switch (tg3_asic_rev(tp)) { in tg3_restore_clk()
9066 static int tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
9067 __releases(tp->lock) in tg3_chip_reset()
9068 __acquires(tp->lock) in tg3_chip_reset()
9074 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9077 tg3_nvram_lock(tp); in tg3_chip_reset()
9079 tg3_ape_lock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9084 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9090 tg3_save_pci_state(tp); in tg3_chip_reset()
9092 if (tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_chip_reset()
9093 tg3_flag(tp, 5755_PLUS)) in tg3_chip_reset()
9102 write_op = tp->write32; in tg3_chip_reset()
9104 tp->write32 = tg3_write32; in tg3_chip_reset()
9112 tg3_flag_set(tp, CHIP_RESETTING); in tg3_chip_reset()
9113 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9114 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9124 tg3_full_unlock(tp); in tg3_chip_reset()
9126 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9127 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9129 tg3_full_lock(tp, 0); in tg3_chip_reset()
9131 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_chip_reset()
9139 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
9141 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9142 !tg3_flag(tp, 57765_PLUS) && in tg3_chip_reset()
9147 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9153 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_chip_reset()
9164 tg3_override_clk(tp); in tg3_chip_reset()
9167 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9173 tp->write32 = write_op; in tg3_chip_reset()
9196 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9200 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9203 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9211 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9212 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9222 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9224 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9227 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9234 tg3_restore_pci_state(tp); in tg3_chip_reset()
9236 tg3_flag_clear(tp, CHIP_RESETTING); in tg3_chip_reset()
9237 tg3_flag_clear(tp, ERROR_PROCESSED); in tg3_chip_reset()
9240 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
9244 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
9245 tg3_stop_fw(tp); in tg3_chip_reset()
9249 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_chip_reset()
9255 tg3_stop_fw(tp); in tg3_chip_reset()
9256 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_chip_reset()
9259 err = tg3_poll_fw(tp); in tg3_chip_reset()
9263 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9265 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
9271 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9272 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_chip_reset()
9273 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9274 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) in tg3_chip_reset()
9275 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9276 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9279 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9280 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9281 val = tp->mac_mode; in tg3_chip_reset()
9282 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9283 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9284 val = tp->mac_mode; in tg3_chip_reset()
9291 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9293 tg3_mdio_start(tp); in tg3_chip_reset()
9295 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
9296 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_chip_reset()
9297 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9298 !tg3_flag(tp, 57765_PLUS)) { in tg3_chip_reset()
9304 tg3_restore_clk(tp); in tg3_chip_reset()
9309 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_chip_reset()
9316 tg3_flag_clear(tp, ENABLE_ASF); in tg3_chip_reset()
9317 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9320 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9321 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_chip_reset()
9325 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_chip_reset()
9327 tg3_flag_set(tp, ENABLE_ASF); in tg3_chip_reset()
9328 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9329 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
9330 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9332 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); in tg3_chip_reset()
9334 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9336 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9348 static int tg3_halt(struct tg3 *tp, int kind, bool silent) in tg3_halt() argument
9352 tg3_stop_fw(tp); in tg3_halt()
9354 tg3_write_sig_pre_reset(tp, kind); in tg3_halt()
9356 tg3_abort_hw(tp, silent); in tg3_halt()
9357 err = tg3_chip_reset(tp); in tg3_halt()
9359 __tg3_set_mac_addr(tp, false); in tg3_halt()
9361 tg3_write_sig_legacy(tp, kind); in tg3_halt()
9362 tg3_write_sig_post_reset(tp, kind); in tg3_halt()
9364 if (tp->hw_stats) { in tg3_halt()
9366 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9367 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9370 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9378 struct tg3 *tp = netdev_priv(dev); in tg3_set_mac_addr() local
9391 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
9404 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9405 __tg3_set_mac_addr(tp, skip_mac_1); in tg3_set_mac_addr()
9407 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9413 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, in tg3_set_bdinfo() argument
9417 tg3_write_mem(tp, in tg3_set_bdinfo()
9420 tg3_write_mem(tp, in tg3_set_bdinfo()
9423 tg3_write_mem(tp, in tg3_set_bdinfo()
9427 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
9428 tg3_write_mem(tp, in tg3_set_bdinfo()
9434 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_tx_init() argument
9438 if (!tg3_flag(tp, ENABLE_TSS)) { in tg3_coal_tx_init()
9447 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9459 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9466 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_rx_init() argument
9469 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9471 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_coal_rx_init()
9493 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9500 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) in __tg3_set_coalesce() argument
9502 tg3_coal_tx_init(tp, ec); in __tg3_set_coalesce()
9503 tg3_coal_rx_init(tp, ec); in __tg3_set_coalesce()
9505 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
9511 if (!tp->link_up) in __tg3_set_coalesce()
9519 static void tg3_tx_rcbs_disable(struct tg3 *tp) in tg3_tx_rcbs_disable() argument
9524 if (!tg3_flag(tp, 5705_PLUS)) in tg3_tx_rcbs_disable()
9526 else if (tg3_flag(tp, 5717_PLUS)) in tg3_tx_rcbs_disable()
9528 else if (tg3_flag(tp, 57765_CLASS) || in tg3_tx_rcbs_disable()
9529 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_tx_rcbs_disable()
9536 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_tx_rcbs_disable()
9541 static void tg3_tx_rcbs_init(struct tg3 *tp) in tg3_tx_rcbs_init() argument
9546 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx_rcbs_init()
9549 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9550 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9555 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9562 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) in tg3_rx_ret_rcbs_disable() argument
9567 if (tg3_flag(tp, 5717_PLUS)) in tg3_rx_ret_rcbs_disable()
9569 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rx_ret_rcbs_disable()
9571 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_rx_ret_rcbs_disable()
9572 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_rx_ret_rcbs_disable()
9573 tg3_flag(tp, 57765_CLASS)) in tg3_rx_ret_rcbs_disable()
9580 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_rx_ret_rcbs_disable()
9585 static void tg3_rx_ret_rcbs_init(struct tg3 *tp) in tg3_rx_ret_rcbs_init() argument
9590 if (tg3_flag(tp, ENABLE_RSS)) in tg3_rx_ret_rcbs_init()
9593 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9594 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9599 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9600 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9606 static void tg3_rings_reset(struct tg3 *tp) in tg3_rings_reset() argument
9610 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9612 tg3_tx_rcbs_disable(tp); in tg3_rings_reset()
9614 tg3_rx_ret_rcbs_disable(tp); in tg3_rings_reset()
9617 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9618 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9619 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9620 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9623 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
9624 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9625 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9626 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9627 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9628 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9629 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9630 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9631 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9632 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9633 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9635 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9636 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9638 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9639 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9640 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9641 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9645 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
9662 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9672 tg3_tx_rcbs_init(tp); in tg3_rings_reset()
9673 tg3_rx_ret_rcbs_init(tp); in tg3_rings_reset()
9676 static void tg3_setup_rxbd_thresholds(struct tg3 *tp) in tg3_setup_rxbd_thresholds() argument
9680 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
9681 tg3_flag(tp, 5780_CLASS) || in tg3_setup_rxbd_thresholds()
9682 tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_setup_rxbd_thresholds()
9683 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_setup_rxbd_thresholds()
9684 tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9686 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
9687 tg3_asic_rev(tp) == ASIC_REV_5787) in tg3_setup_rxbd_thresholds()
9692 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9693 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9698 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9701 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
9706 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9711 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9739 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) in tg3_set_multi() argument
9750 struct tg3 *tp = netdev_priv(dev); in __tg3_set_rx_mode() local
9753 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9760 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
9769 tg3_set_multi(tp, 1); in __tg3_set_rx_mode()
9772 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9795 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) { in __tg3_set_rx_mode()
9803 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9804 i + TG3_UCAST_ADDR_IDX(tp)); in __tg3_set_rx_mode()
9809 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9810 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9816 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) in tg3_rss_init_dflt_indir_tbl() argument
9821 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9824 static void tg3_rss_check_indir_tbl(struct tg3 *tp) in tg3_rss_check_indir_tbl() argument
9828 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
9831 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9832 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9838 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9843 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9846 static void tg3_rss_write_indir_tbl(struct tg3 *tp) in tg3_rss_write_indir_tbl() argument
9852 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9856 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9863 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) in tg3_lso_rd_dma_workaround_bit() argument
9865 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_lso_rd_dma_workaround_bit()
9872 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) in tg3_reset_hw() argument
9876 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9878 tg3_disable_ints(tp); in tg3_reset_hw()
9880 tg3_stop_fw(tp); in tg3_reset_hw()
9882 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
9884 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
9885 tg3_abort_hw(tp, 1); in tg3_reset_hw()
9887 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9888 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9889 tg3_phy_pull_config(tp); in tg3_reset_hw()
9890 tg3_eee_pull_config(tp, NULL); in tg3_reset_hw()
9891 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9895 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9896 tg3_setup_eee(tp); in tg3_reset_hw()
9899 tg3_phy_reset(tp); in tg3_reset_hw()
9901 err = tg3_chip_reset(tp); in tg3_reset_hw()
9905 tg3_write_sig_legacy(tp, RESET_KIND_INIT); in tg3_reset_hw()
9907 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_reset_hw()
9928 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_reset_hw()
9943 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
9957 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
9958 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
9973 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { in tg3_reset_hw()
10007 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
10008 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10009 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10010 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10013 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
10014 tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10020 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
10031 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { in tg3_reset_hw()
10043 err = tg3_init_rings(tp); in tg3_reset_hw()
10047 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10050 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_reset_hw()
10052 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
10053 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_reset_hw()
10054 tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_reset_hw()
10056 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10057 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && in tg3_reset_hw()
10058 tg3_asic_rev(tp) != ASIC_REV_5761) { in tg3_reset_hw()
10062 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10065 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10069 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10077 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10080 if (tp->rxptpctl) in tg3_reset_hw()
10082 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10084 if (tg3_flag(tp, PTP_CAPABLE)) in tg3_reset_hw()
10087 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10093 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10094 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10106 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10108 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { in tg3_reset_hw()
10110 if (tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_reset_hw()
10116 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10119 fw_len = tp->fw_len; in tg3_reset_hw()
10127 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10129 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10131 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10133 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10136 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10138 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10140 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10143 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10145 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10148 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_reset_hw()
10150 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_reset_hw()
10151 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_reset_hw()
10152 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10153 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) in tg3_reset_hw()
10162 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10166 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) in tg3_reset_hw()
10169 tg3_setup_rxbd_thresholds(tp); in tg3_reset_hw()
10192 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
10197 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10204 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10205 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { in tg3_reset_hw()
10207 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
10212 val = TG3_RX_JMB_RING_SIZE(tp) << in tg3_reset_hw()
10216 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
10217 tg3_flag(tp, 57765_CLASS) || in tg3_reset_hw()
10218 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10226 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10227 val = TG3_RX_STD_RING_SIZE(tp); in tg3_reset_hw()
10237 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10241 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10244 tg3_rings_reset(tp); in tg3_reset_hw()
10247 __tg3_set_mac_addr(tp, false); in tg3_reset_hw()
10251 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10260 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10261 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10281 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_reset_hw()
10284 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10285 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10286 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10291 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10292 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10293 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10294 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_reset_hw()
10297 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10302 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10305 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10306 tp->dma_limit = 0; in tg3_reset_hw()
10307 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10309 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10313 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10314 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10315 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10318 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
10319 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10320 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10323 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10324 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10327 if (tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_reset_hw()
10328 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10329 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10330 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_reset_hw()
10331 tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10334 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10340 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10341 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10352 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10353 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10354 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10357 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10369 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10374 tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10395 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10397 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10403 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10405 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10414 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10419 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10423 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10426 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10427 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10433 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10436 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10437 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10438 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
10439 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10440 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_reset_hw()
10441 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10442 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10451 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
10458 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_reset_hw()
10462 if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_reset_hw()
10465 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10466 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10469 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
10470 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10473 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10476 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
10479 if (tp->irq_cnt > 1) in tg3_reset_hw()
10481 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
10486 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10497 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10498 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10499 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10500 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || in tg3_reset_hw()
10501 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { in tg3_reset_hw()
10504 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10510 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10513 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_reset_hw()
10519 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10522 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10524 if (tg3_asic_rev(tp) == ASIC_REV_5703) { in tg3_reset_hw()
10527 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_reset_hw()
10531 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10538 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10539 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_reset_hw()
10541 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10546 val |= tg3_lso_rd_dma_workaround_bit(tp); in tg3_reset_hw()
10548 tg3_flag_set(tp, 5719_5720_RDMA_BUG); in tg3_reset_hw()
10553 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10556 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_reset_hw()
10565 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
10569 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10570 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10571 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10574 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
10579 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
10580 err = tg3_load_5701_a0_firmware_fix(tp); in tg3_reset_hw()
10585 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10589 tg3_load_57766_firmware(tp); in tg3_reset_hw()
10592 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10593 err = tg3_load_tso_firmware(tp); in tg3_reset_hw()
10598 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10600 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
10601 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_reset_hw()
10602 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10604 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10605 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10607 tp->tx_mode &= ~val; in tg3_reset_hw()
10608 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10611 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10614 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
10617 tg3_rss_write_indir_tbl(tp); in tg3_reset_hw()
10625 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10626 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10627 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10629 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10630 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10632 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
10633 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10640 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10643 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10646 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10650 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10653 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10654 if ((tg3_asic_rev(tp) == ASIC_REV_5704) && in tg3_reset_hw()
10655 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10663 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) in tg3_reset_hw()
10670 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
10676 if (tg3_asic_rev(tp) == ASIC_REV_5704 && in tg3_reset_hw()
10677 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10679 tg3_flag_set(tp, HW_AUTONEG); in tg3_reset_hw()
10682 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10683 tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_reset_hw()
10688 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10689 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10690 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10693 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
10694 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10695 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10697 err = tg3_setup_phy(tp, false); in tg3_reset_hw()
10701 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10702 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10706 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
10707 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
10709 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); in tg3_reset_hw()
10714 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10722 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
10726 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
10776 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10778 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, in tg3_reset_hw()
10781 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
10789 static int tg3_init_hw(struct tg3 *tp, bool reset_phy) in tg3_init_hw() argument
10795 tg3_enable_register_access(tp); in tg3_init_hw()
10796 tg3_poll_fw(tp); in tg3_init_hw()
10798 tg3_switch_clocks(tp); in tg3_init_hw()
10802 return tg3_reset_hw(tp, reset_phy); in tg3_init_hw()
10806 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) in tg3_sd_scan_scratchpad() argument
10813 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); in tg3_sd_scan_scratchpad()
10827 struct tg3 *tp = dev_get_drvdata(dev); in tg3_show_temp() local
10830 spin_lock_bh(&tp->lock); in tg3_show_temp()
10831 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10833 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10853 static void tg3_hwmon_close(struct tg3 *tp) in tg3_hwmon_close() argument
10855 if (tp->hwmon_dev) { in tg3_hwmon_close()
10856 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10857 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10861 static void tg3_hwmon_open(struct tg3 *tp) in tg3_hwmon_open() argument
10865 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10868 tg3_sd_scan_scratchpad(tp, ocirs); in tg3_hwmon_open()
10881 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10882 tp, tg3_groups); in tg3_hwmon_open()
10883 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10884 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10889 static inline void tg3_hwmon_close(struct tg3 *tp) { } in tg3_hwmon_close() argument
10890 static inline void tg3_hwmon_open(struct tg3 *tp) { } in tg3_hwmon_open() argument
10901 static void tg3_periodic_fetch_stats(struct tg3 *tp) in tg3_periodic_fetch_stats() argument
10903 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10905 if (!tp->link_up) in tg3_periodic_fetch_stats()
10921 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && in tg3_periodic_fetch_stats()
10927 val &= ~tg3_lso_rd_dma_workaround_bit(tp); in tg3_periodic_fetch_stats()
10929 tg3_flag_clear(tp, 5719_5720_RDMA_BUG); in tg3_periodic_fetch_stats()
10948 if (tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
10949 tg3_asic_rev(tp) != ASIC_REV_5762 && in tg3_periodic_fetch_stats()
10950 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && in tg3_periodic_fetch_stats()
10951 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { in tg3_periodic_fetch_stats()
10967 static void tg3_chk_missed_msi(struct tg3 *tp) in tg3_chk_missed_msi() argument
10971 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10972 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10992 struct tg3 *tp = from_timer(tp, t, timer); in tg3_timer() local
10994 spin_lock(&tp->lock); in tg3_timer()
10996 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10997 spin_unlock(&tp->lock); in tg3_timer()
11001 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_timer()
11002 tg3_flag(tp, 57765_CLASS)) in tg3_timer()
11003 tg3_chk_missed_msi(tp); in tg3_timer()
11005 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_timer()
11010 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
11015 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11017 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11019 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11024 spin_unlock(&tp->lock); in tg3_timer()
11025 tg3_reset_task_schedule(tp); in tg3_timer()
11031 if (!--tp->timer_counter) { in tg3_timer()
11032 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
11033 tg3_periodic_fetch_stats(tp); in tg3_timer()
11035 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11036 tg3_phy_eee_enable(tp); in tg3_timer()
11038 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
11045 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11052 tg3_setup_phy(tp, false); in tg3_timer()
11053 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
11057 if (tp->link_up && in tg3_timer()
11061 if (!tp->link_up && in tg3_timer()
11067 if (!tp->serdes_counter) { in tg3_timer()
11069 (tp->mac_mode & in tg3_timer()
11072 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11075 tg3_setup_phy(tp, false); in tg3_timer()
11077 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11078 tg3_flag(tp, 5780_CLASS)) { in tg3_timer()
11079 tg3_serdes_parallel_detect(tp); in tg3_timer()
11080 } else if (tg3_flag(tp, POLL_CPMU_LINK)) { in tg3_timer()
11085 if (link_up != tp->link_up) in tg3_timer()
11086 tg3_setup_phy(tp, false); in tg3_timer()
11089 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11109 if (!--tp->asf_counter) { in tg3_timer()
11110 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
11111 tg3_wait_for_event_ack(tp); in tg3_timer()
11113 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, in tg3_timer()
11115 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); in tg3_timer()
11116 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, in tg3_timer()
11119 tg3_generate_fw_event(tp); in tg3_timer()
11121 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11125 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL); in tg3_timer()
11127 spin_unlock(&tp->lock); in tg3_timer()
11130 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11131 add_timer(&tp->timer); in tg3_timer()
11134 static void tg3_timer_init(struct tg3 *tp) in tg3_timer_init() argument
11136 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_timer_init()
11137 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_timer_init()
11138 !tg3_flag(tp, 57765_CLASS)) in tg3_timer_init()
11139 tp->timer_offset = HZ; in tg3_timer_init()
11141 tp->timer_offset = HZ / 10; in tg3_timer_init()
11143 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11145 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11146 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11149 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11152 static void tg3_timer_start(struct tg3 *tp) in tg3_timer_start() argument
11154 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11155 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11157 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11158 add_timer(&tp->timer); in tg3_timer_start()
11161 static void tg3_timer_stop(struct tg3 *tp) in tg3_timer_stop() argument
11163 del_timer_sync(&tp->timer); in tg3_timer_stop()
11169 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) in tg3_restart_hw() argument
11170 __releases(tp->lock) in tg3_restart_hw()
11171 __acquires(tp->lock) in tg3_restart_hw()
11175 err = tg3_init_hw(tp, reset_phy); in tg3_restart_hw()
11177 netdev_err(tp->dev, in tg3_restart_hw()
11179 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_restart_hw()
11180 tg3_full_unlock(tp); in tg3_restart_hw()
11181 tg3_timer_stop(tp); in tg3_restart_hw()
11182 tp->irq_sync = 0; in tg3_restart_hw()
11183 tg3_napi_enable(tp); in tg3_restart_hw()
11184 dev_close(tp->dev); in tg3_restart_hw()
11185 tg3_full_lock(tp, 0); in tg3_restart_hw()
11192 struct tg3 *tp = container_of(work, struct tg3, reset_task); in tg3_reset_task() local
11196 tg3_full_lock(tp, 0); in tg3_reset_task()
11198 if (!netif_running(tp->dev)) { in tg3_reset_task()
11199 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11200 tg3_full_unlock(tp); in tg3_reset_task()
11205 tg3_full_unlock(tp); in tg3_reset_task()
11207 tg3_phy_stop(tp); in tg3_reset_task()
11209 tg3_netif_stop(tp); in tg3_reset_task()
11211 tg3_full_lock(tp, 1); in tg3_reset_task()
11213 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
11214 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11215 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11216 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_reset_task()
11217 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task()
11220 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11221 err = tg3_init_hw(tp, true); in tg3_reset_task()
11225 tg3_netif_start(tp); in tg3_reset_task()
11228 tg3_full_unlock(tp); in tg3_reset_task()
11231 tg3_phy_start(tp); in tg3_reset_task()
11233 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11237 static int tg3_request_irq(struct tg3 *tp, int irq_num) in tg3_request_irq() argument
11242 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11244 if (tp->irq_cnt == 1) in tg3_request_irq()
11245 name = tp->dev->name; in tg3_request_irq()
11250 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11253 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11256 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11259 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11263 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
11265 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
11270 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
11278 static int tg3_test_interrupt(struct tg3 *tp) in tg3_test_interrupt() argument
11280 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11281 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11288 tg3_disable_ints(tp); in tg3_test_interrupt()
11296 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
11307 tg3_enable_ints(tp); in tg3_test_interrupt()
11309 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11324 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
11331 tg3_disable_ints(tp); in tg3_test_interrupt()
11335 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11342 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
11355 static int tg3_test_msi(struct tg3 *tp) in tg3_test_msi() argument
11360 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
11366 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11367 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11370 err = tg3_test_interrupt(tp); in tg3_test_msi()
11372 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11382 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11386 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11388 pci_disable_msi(tp->pdev); in tg3_test_msi()
11390 tg3_flag_clear(tp, USING_MSI); in tg3_test_msi()
11391 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11393 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11400 tg3_full_lock(tp, 1); in tg3_test_msi()
11402 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_test_msi()
11403 err = tg3_init_hw(tp, true); in tg3_test_msi()
11405 tg3_full_unlock(tp); in tg3_test_msi()
11408 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11413 static int tg3_request_firmware(struct tg3 *tp) in tg3_request_firmware() argument
11417 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11418 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11419 tp->fw_needed); in tg3_request_firmware()
11423 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11430 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11431 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11432 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11433 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11434 release_firmware(tp->fw); in tg3_request_firmware()
11435 tp->fw = NULL; in tg3_request_firmware()
11440 tp->fw_needed = NULL; in tg3_request_firmware()
11444 static u32 tg3_irq_count(struct tg3 *tp) in tg3_irq_count() argument
11446 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11454 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11460 static bool tg3_enable_msix(struct tg3 *tp) in tg3_enable_msix() argument
11465 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11466 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11467 if (!tp->rxq_cnt) in tg3_enable_msix()
11468 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11469 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11470 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11476 if (!tp->txq_req) in tg3_enable_msix()
11477 tp->txq_cnt = 1; in tg3_enable_msix()
11479 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11481 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11486 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11489 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11490 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11491 tp->irq_cnt, rc); in tg3_enable_msix()
11492 tp->irq_cnt = rc; in tg3_enable_msix()
11493 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11494 if (tp->txq_cnt) in tg3_enable_msix()
11495 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11498 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11499 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11501 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11502 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11506 if (tp->irq_cnt == 1) in tg3_enable_msix()
11509 tg3_flag_set(tp, ENABLE_RSS); in tg3_enable_msix()
11511 if (tp->txq_cnt > 1) in tg3_enable_msix()
11512 tg3_flag_set(tp, ENABLE_TSS); in tg3_enable_msix()
11514 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11519 static void tg3_ints_init(struct tg3 *tp) in tg3_ints_init() argument
11521 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
11522 !tg3_flag(tp, TAGGED_STATUS)) { in tg3_ints_init()
11526 netdev_warn(tp->dev, in tg3_ints_init()
11531 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
11532 tg3_flag_set(tp, USING_MSIX); in tg3_ints_init()
11533 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11534 tg3_flag_set(tp, USING_MSI); in tg3_ints_init()
11536 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11538 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11540 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
11545 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11546 tp->irq_cnt = 1; in tg3_ints_init()
11547 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11550 if (tp->irq_cnt == 1) { in tg3_ints_init()
11551 tp->txq_cnt = 1; in tg3_ints_init()
11552 tp->rxq_cnt = 1; in tg3_ints_init()
11553 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11554 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11558 static void tg3_ints_fini(struct tg3 *tp) in tg3_ints_fini() argument
11560 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
11561 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11562 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
11563 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11564 tg3_flag_clear(tp, USING_MSI); in tg3_ints_fini()
11565 tg3_flag_clear(tp, USING_MSIX); in tg3_ints_fini()
11566 tg3_flag_clear(tp, ENABLE_RSS); in tg3_ints_fini()
11567 tg3_flag_clear(tp, ENABLE_TSS); in tg3_ints_fini()
11570 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, in tg3_start() argument
11573 struct net_device *dev = tp->dev; in tg3_start()
11580 tg3_ints_init(tp); in tg3_start()
11582 tg3_rss_check_indir_tbl(tp); in tg3_start()
11587 err = tg3_alloc_consistent(tp); in tg3_start()
11591 tg3_napi_init(tp); in tg3_start()
11593 tg3_napi_enable(tp); in tg3_start()
11595 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11596 err = tg3_request_irq(tp, i); in tg3_start()
11599 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11607 tg3_full_lock(tp, 0); in tg3_start()
11610 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_start()
11612 err = tg3_init_hw(tp, reset_phy); in tg3_start()
11614 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11615 tg3_free_rings(tp); in tg3_start()
11618 tg3_full_unlock(tp); in tg3_start()
11623 if (test_irq && tg3_flag(tp, USING_MSI)) { in tg3_start()
11624 err = tg3_test_msi(tp); in tg3_start()
11627 tg3_full_lock(tp, 0); in tg3_start()
11628 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11629 tg3_free_rings(tp); in tg3_start()
11630 tg3_full_unlock(tp); in tg3_start()
11635 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_start()
11643 tg3_phy_start(tp); in tg3_start()
11645 tg3_hwmon_open(tp); in tg3_start()
11647 tg3_full_lock(tp, 0); in tg3_start()
11649 tg3_timer_start(tp); in tg3_start()
11650 tg3_flag_set(tp, INIT_COMPLETE); in tg3_start()
11651 tg3_enable_ints(tp); in tg3_start()
11653 tg3_ptp_resume(tp); in tg3_start()
11655 tg3_full_unlock(tp); in tg3_start()
11669 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11670 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11675 tg3_napi_disable(tp); in tg3_start()
11676 tg3_napi_fini(tp); in tg3_start()
11677 tg3_free_consistent(tp); in tg3_start()
11680 tg3_ints_fini(tp); in tg3_start()
11685 static void tg3_stop(struct tg3 *tp) in tg3_stop() argument
11689 tg3_reset_task_cancel(tp); in tg3_stop()
11690 tg3_netif_stop(tp); in tg3_stop()
11692 tg3_timer_stop(tp); in tg3_stop()
11694 tg3_hwmon_close(tp); in tg3_stop()
11696 tg3_phy_stop(tp); in tg3_stop()
11698 tg3_full_lock(tp, 1); in tg3_stop()
11700 tg3_disable_ints(tp); in tg3_stop()
11702 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_stop()
11703 tg3_free_rings(tp); in tg3_stop()
11704 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_stop()
11706 tg3_full_unlock(tp); in tg3_stop()
11708 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11709 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11713 tg3_ints_fini(tp); in tg3_stop()
11715 tg3_napi_fini(tp); in tg3_stop()
11717 tg3_free_consistent(tp); in tg3_stop()
11722 struct tg3 *tp = netdev_priv(dev); in tg3_open() local
11725 if (tp->pcierr_recovery) { in tg3_open()
11731 if (tp->fw_needed) { in tg3_open()
11732 err = tg3_request_firmware(tp); in tg3_open()
11733 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_open()
11735 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11736 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11737 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11738 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11739 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11741 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_open()
11745 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11746 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_open()
11747 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
11748 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11749 tg3_flag_set(tp, TSO_CAPABLE); in tg3_open()
11753 tg3_carrier_off(tp); in tg3_open()
11755 err = tg3_power_up(tp); in tg3_open()
11759 tg3_full_lock(tp, 0); in tg3_open()
11761 tg3_disable_ints(tp); in tg3_open()
11762 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_open()
11764 tg3_full_unlock(tp); in tg3_open()
11766 err = tg3_start(tp, in tg3_open()
11767 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11770 tg3_frob_aux_power(tp, false); in tg3_open()
11771 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11779 struct tg3 *tp = netdev_priv(dev); in tg3_close() local
11781 if (tp->pcierr_recovery) { in tg3_close()
11787 tg3_stop(tp); in tg3_close()
11789 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11790 tg3_power_down_prepare(tp); in tg3_close()
11792 tg3_carrier_off(tp); in tg3_close()
11802 static u64 tg3_calc_crc_errors(struct tg3 *tp) in tg3_calc_crc_errors() argument
11804 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11806 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11807 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_calc_crc_errors()
11808 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_calc_crc_errors()
11811 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
11812 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
11814 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); in tg3_calc_crc_errors()
11818 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11820 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11830 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) in tg3_get_estats() argument
11832 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11833 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11914 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) in tg3_get_nstats() argument
11916 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11917 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11959 tg3_calc_crc_errors(tp); in tg3_get_nstats()
11964 stats->rx_dropped = tp->rx_dropped; in tg3_get_nstats()
11965 stats->tx_dropped = tp->tx_dropped; in tg3_get_nstats()
11976 struct tg3 *tp = netdev_priv(dev); in tg3_get_regs() local
11982 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
11985 tg3_full_lock(tp, 0); in tg3_get_regs()
11987 tg3_dump_legacy_regs(tp, (u32 *)_p); in tg3_get_regs()
11989 tg3_full_unlock(tp); in tg3_get_regs()
11994 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom_len() local
11996 return tp->nvram_size; in tg3_get_eeprom_len()
12001 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom() local
12007 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
12017 if (tg3_flag(tp, CPMU_PRESENT)) { in tg3_get_eeprom()
12027 tg3_override_clk(tp); in tg3_get_eeprom()
12037 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12049 ret = tg3_nvram_read_be32(tp, offset + i, &val); in tg3_get_eeprom()
12073 ret = tg3_nvram_read_be32(tp, b_offset, &val); in tg3_get_eeprom()
12083 tg3_restore_clk(tp); in tg3_get_eeprom()
12092 struct tg3 *tp = netdev_priv(dev); in tg3_set_eeprom() local
12098 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
12107 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12121 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12138 ret = tg3_nvram_write_block(tp, offset, len, buf); in tg3_set_eeprom()
12149 struct tg3 *tp = netdev_priv(dev); in tg3_get_link_ksettings() local
12152 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_link_ksettings()
12154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12156 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12164 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12168 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12182 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12183 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_link_ksettings()
12184 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12185 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12191 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12198 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12199 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12200 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12203 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12205 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12206 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12216 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12217 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12224 struct tg3 *tp = netdev_priv(dev); in tg3_set_link_ksettings() local
12228 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_link_ksettings()
12230 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12232 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12253 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12257 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12278 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12291 tg3_full_lock(tp, 0); in tg3_set_link_ksettings()
12293 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12295 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12297 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12298 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12300 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12301 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12302 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12305 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12307 tg3_warn_mgmt_link_flap(tp); in tg3_set_link_ksettings()
12310 tg3_setup_phy(tp, true); in tg3_set_link_ksettings()
12312 tg3_full_unlock(tp); in tg3_set_link_ksettings()
12319 struct tg3 *tp = netdev_priv(dev); in tg3_get_drvinfo() local
12323 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12324 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12329 struct tg3 *tp = netdev_priv(dev); in tg3_get_wol() local
12331 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12336 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12343 struct tg3 *tp = netdev_priv(dev); in tg3_set_wol() local
12344 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12349 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12355 tg3_flag_set(tp, WOL_ENABLE); in tg3_set_wol()
12357 tg3_flag_clear(tp, WOL_ENABLE); in tg3_set_wol()
12364 struct tg3 *tp = netdev_priv(dev); in tg3_get_msglevel() local
12365 return tp->msg_enable; in tg3_get_msglevel()
12370 struct tg3 *tp = netdev_priv(dev); in tg3_set_msglevel() local
12371 tp->msg_enable = value; in tg3_set_msglevel()
12376 struct tg3 *tp = netdev_priv(dev); in tg3_nway_reset() local
12382 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12385 tg3_warn_mgmt_link_flap(tp); in tg3_nway_reset()
12387 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
12388 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12390 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12394 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12396 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_nway_reset()
12397 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
12399 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12400 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
12404 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12412 struct tg3 *tp = netdev_priv(dev); in tg3_get_ringparam() local
12414 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12415 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12416 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12422 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12423 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12424 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12428 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12433 struct tg3 *tp = netdev_priv(dev); in tg3_set_ringparam() local
12437 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12438 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12441 (tg3_flag(tp, TSO_BUG) && in tg3_set_ringparam()
12446 tg3_phy_stop(tp); in tg3_set_ringparam()
12447 tg3_netif_stop(tp); in tg3_set_ringparam()
12451 tg3_full_lock(tp, irq_sync); in tg3_set_ringparam()
12453 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12455 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
12456 tp->rx_pending > 63) in tg3_set_ringparam()
12457 tp->rx_pending = 63; in tg3_set_ringparam()
12459 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_set_ringparam()
12460 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12462 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12463 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12466 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_ringparam()
12468 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_ringparam()
12469 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_ringparam()
12470 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_ringparam()
12473 err = tg3_restart_hw(tp, reset_phy); in tg3_set_ringparam()
12475 tg3_netif_start(tp); in tg3_set_ringparam()
12478 tg3_full_unlock(tp); in tg3_set_ringparam()
12481 tg3_phy_start(tp); in tg3_set_ringparam()
12488 struct tg3 *tp = netdev_priv(dev); in tg3_get_pauseparam() local
12490 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12492 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12497 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12505 struct tg3 *tp = netdev_priv(dev); in tg3_set_pauseparam() local
12509 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12510 tg3_warn_mgmt_link_flap(tp); in tg3_set_pauseparam()
12512 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
12515 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12520 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12523 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12526 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12529 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12533 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12535 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12537 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12550 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12556 tg3_netif_stop(tp); in tg3_set_pauseparam()
12560 tg3_full_lock(tp, irq_sync); in tg3_set_pauseparam()
12563 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12565 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12567 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12569 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12571 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12573 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12576 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_pauseparam()
12578 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_pauseparam()
12579 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_pauseparam()
12580 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_pauseparam()
12583 err = tg3_restart_hw(tp, reset_phy); in tg3_set_pauseparam()
12585 tg3_netif_start(tp); in tg3_set_pauseparam()
12588 tg3_full_unlock(tp); in tg3_set_pauseparam()
12591 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12611 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxnfc() local
12613 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
12618 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12619 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12636 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh_indir_size() local
12638 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
12646 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh() local
12655 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12663 struct tg3 *tp = netdev_priv(dev); in tg3_set_rxfh() local
12677 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12679 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh()
12685 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12686 tg3_rss_write_indir_tbl(tp); in tg3_set_rxfh()
12687 tg3_full_unlock(tp); in tg3_set_rxfh()
12695 struct tg3 *tp = netdev_priv(dev); in tg3_get_channels() local
12698 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12699 channel->max_tx = tp->txq_max; in tg3_get_channels()
12702 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12703 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12705 if (tp->rxq_req) in tg3_get_channels()
12706 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12708 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12710 if (tp->txq_req) in tg3_get_channels()
12711 channel->tx_count = tp->txq_req; in tg3_get_channels()
12713 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12720 struct tg3 *tp = netdev_priv(dev); in tg3_set_channels() local
12722 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_set_channels()
12725 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12726 channel->tx_count > tp->txq_max) in tg3_set_channels()
12729 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12730 tp->txq_req = channel->tx_count; in tg3_set_channels()
12735 tg3_stop(tp); in tg3_set_channels()
12737 tg3_carrier_off(tp); in tg3_set_channels()
12739 tg3_start(tp, true, false, false); in tg3_set_channels()
12762 struct tg3 *tp = netdev_priv(dev); in tg3_set_phys_id() local
12784 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12794 struct tg3 *tp = netdev_priv(dev); in tg3_get_ethtool_stats() local
12796 if (tp->hw_stats) in tg3_get_ethtool_stats()
12797 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); in tg3_get_ethtool_stats()
12802 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) in tg3_vpd_readblock() argument
12809 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12816 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
12826 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
12829 offset = tg3_nvram_logical_addr(tp, offset); in tg3_vpd_readblock()
12848 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
12858 cnt = pci_read_vpd(tp->pdev, pos, in tg3_vpd_readblock()
12888 static int tg3_test_nvram(struct tg3 *tp) in tg3_test_nvram() argument
12894 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
12897 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
12940 err = tg3_nvram_read_be32(tp, i, &buf[j]); in tg3_test_nvram()
13031 buf = tg3_vpd_readblock(tp, &len); in tg3_test_nvram()
13070 static int tg3_test_link(struct tg3 *tp) in tg3_test_link() argument
13074 if (!netif_running(tp->dev)) in tg3_test_link()
13077 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13083 if (tp->link_up) in tg3_test_link()
13094 static int tg3_test_registers(struct tg3 *tp) in tg3_test_registers() argument
13244 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
13246 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
13257 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
13307 if (netif_msg_hw(tp)) in tg3_test_registers()
13308 netdev_err(tp->dev, in tg3_test_registers()
13314 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) in tg3_do_mem_test() argument
13324 tg3_write_mem(tp, offset + j, test_pattern[i]); in tg3_do_mem_test()
13325 tg3_read_mem(tp, offset + j, &val); in tg3_do_mem_test()
13333 static int tg3_test_memory(struct tg3 *tp) in tg3_test_memory() argument
13380 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
13382 else if (tg3_flag(tp, 57765_CLASS) || in tg3_test_memory()
13383 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_test_memory()
13385 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
13387 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_test_memory()
13389 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
13395 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); in tg3_test_memory()
13426 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) in tg3_run_loopback() argument
13437 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13439 tnapi = &tp->napi[0]; in tg3_run_loopback()
13440 rnapi = &tp->napi[0]; in tg3_run_loopback()
13441 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13442 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
13443 rnapi = &tp->napi[1]; in tg3_run_loopback()
13444 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
13445 tnapi = &tp->napi[1]; in tg3_run_loopback()
13452 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13457 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13481 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13482 tg3_flag(tp, HW_TSO_2) || in tg3_run_loopback()
13483 tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13491 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13496 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
13498 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13499 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_run_loopback()
13510 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_run_loopback()
13518 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); in tg3_run_loopback()
13519 if (pci_dma_mapping_error(tp->pdev, map)) { in tg3_run_loopback()
13528 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13555 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13617 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, in tg3_run_loopback()
13620 rx_data += TG3_RX_OFFSET(tp); in tg3_run_loopback()
13642 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) in tg3_test_loopback() argument
13648 if (tp->dma_limit) in tg3_test_loopback()
13649 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13651 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13652 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13654 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13662 err = tg3_reset_hw(tp, true); in tg3_test_loopback()
13671 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
13685 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_test_loopback()
13686 !tg3_flag(tp, CPMU_PRESENT)) { in tg3_test_loopback()
13687 tg3_mac_loopback(tp, true); in tg3_test_loopback()
13689 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13692 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13693 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13696 tg3_mac_loopback(tp, false); in tg3_test_loopback()
13699 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13700 !tg3_flag(tp, USE_PHYLIB)) { in tg3_test_loopback()
13703 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13712 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13714 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13715 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13717 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13718 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13722 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13730 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13733 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13734 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13737 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13738 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13744 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13745 tg3_phy_toggle_apd(tp, true); in tg3_test_loopback()
13752 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13760 struct tg3 *tp = netdev_priv(dev); in tg3_self_test() local
13763 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13764 if (tg3_power_up(tp)) { in tg3_self_test()
13769 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_self_test()
13774 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13778 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
13786 tg3_phy_stop(tp); in tg3_self_test()
13787 tg3_netif_stop(tp); in tg3_self_test()
13791 tg3_full_lock(tp, irq_sync); in tg3_self_test()
13792 tg3_halt(tp, RESET_KIND_SUSPEND, 1); in tg3_self_test()
13793 err = tg3_nvram_lock(tp); in tg3_self_test()
13794 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_self_test()
13795 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
13796 tg3_halt_cpu(tp, TX_CPU_BASE); in tg3_self_test()
13798 tg3_nvram_unlock(tp); in tg3_self_test()
13800 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13801 tg3_phy_reset(tp); in tg3_self_test()
13803 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13808 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13816 if (tg3_test_loopback(tp, data, doextlpbk)) in tg3_self_test()
13819 tg3_full_unlock(tp); in tg3_self_test()
13821 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13826 tg3_full_lock(tp, 0); in tg3_self_test()
13828 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_self_test()
13830 tg3_flag_set(tp, INIT_COMPLETE); in tg3_self_test()
13831 err2 = tg3_restart_hw(tp, true); in tg3_self_test()
13833 tg3_netif_start(tp); in tg3_self_test()
13836 tg3_full_unlock(tp); in tg3_self_test()
13839 tg3_phy_start(tp); in tg3_self_test()
13841 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13842 tg3_power_down_prepare(tp); in tg3_self_test()
13848 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_set() local
13851 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_set()
13866 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13869 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13873 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13877 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13881 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13885 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13889 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13893 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13897 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13901 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13905 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13909 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13913 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13920 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13922 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13925 tg3_flag_set(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13927 tg3_flag_clear(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13935 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_get() local
13938 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_get()
13942 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
13945 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13997 struct tg3 *tp = netdev_priv(dev); in tg3_ioctl() local
14000 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
14002 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14004 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14010 data->phy_id = tp->phy_addr; in tg3_ioctl()
14016 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14022 spin_lock_bh(&tp->lock); in tg3_ioctl()
14023 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14025 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14033 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14039 spin_lock_bh(&tp->lock); in tg3_ioctl()
14040 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14042 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14061 struct tg3 *tp = netdev_priv(dev); in tg3_get_coalesce() local
14063 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14069 struct tg3 *tp = netdev_priv(dev); in tg3_set_coalesce() local
14073 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
14095 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14096 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14097 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14098 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14099 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14100 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14101 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14102 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14103 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14106 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14107 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14108 tg3_full_unlock(tp); in tg3_set_coalesce()
14115 struct tg3 *tp = netdev_priv(dev); in tg3_set_eee() local
14117 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14118 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14122 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14123 netdev_warn(tp->dev, in tg3_set_eee()
14129 netdev_warn(tp->dev, in tg3_set_eee()
14135 tp->eee = *edata; in tg3_set_eee()
14137 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14138 tg3_warn_mgmt_link_flap(tp); in tg3_set_eee()
14140 if (netif_running(tp->dev)) { in tg3_set_eee()
14141 tg3_full_lock(tp, 0); in tg3_set_eee()
14142 tg3_setup_eee(tp); in tg3_set_eee()
14143 tg3_phy_reset(tp); in tg3_set_eee()
14144 tg3_full_unlock(tp); in tg3_set_eee()
14152 struct tg3 *tp = netdev_priv(dev); in tg3_get_eee() local
14154 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14155 netdev_warn(tp->dev, in tg3_get_eee()
14160 *edata = tp->eee; in tg3_get_eee()
14204 struct tg3 *tp = netdev_priv(dev); in tg3_get_stats64() local
14206 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14207 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14208 *stats = tp->net_stats_prev; in tg3_get_stats64()
14209 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14213 tg3_get_nstats(tp, stats); in tg3_get_stats64()
14214 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14219 struct tg3 *tp = netdev_priv(dev); in tg3_set_rx_mode() local
14224 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14226 tg3_full_unlock(tp); in tg3_set_rx_mode()
14229 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, in tg3_set_mtu() argument
14235 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14237 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_set_mtu()
14239 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14242 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14243 tg3_flag_set(tp, TSO_CAPABLE); in tg3_set_mtu()
14246 tg3_flag_clear(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14252 struct tg3 *tp = netdev_priv(dev); in tg3_change_mtu() local
14260 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14264 tg3_phy_stop(tp); in tg3_change_mtu()
14266 tg3_netif_stop(tp); in tg3_change_mtu()
14268 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14270 tg3_full_lock(tp, 1); in tg3_change_mtu()
14272 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_change_mtu()
14277 if (tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_change_mtu()
14278 tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_change_mtu()
14279 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_change_mtu()
14280 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_change_mtu()
14283 err = tg3_restart_hw(tp, reset_phy); in tg3_change_mtu()
14286 tg3_netif_start(tp); in tg3_change_mtu()
14288 tg3_full_unlock(tp); in tg3_change_mtu()
14291 tg3_phy_start(tp); in tg3_change_mtu()
14314 static void tg3_get_eeprom_size(struct tg3 *tp) in tg3_get_eeprom_size() argument
14318 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14320 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14335 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14336 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14345 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14348 static void tg3_get_nvram_size(struct tg3 *tp) in tg3_get_nvram_size() argument
14352 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14357 tg3_get_eeprom_size(tp); in tg3_get_nvram_size()
14361 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14374 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14378 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14381 static void tg3_get_nvram_info(struct tg3 *tp) in tg3_get_nvram_info() argument
14387 tg3_flag_set(tp, FLASH); in tg3_get_nvram_info()
14393 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_nvram_info()
14394 tg3_flag(tp, 5780_CLASS)) { in tg3_get_nvram_info()
14397 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14398 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14399 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14402 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14403 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14406 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14407 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14408 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14411 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14412 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14413 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14416 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14417 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14421 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14422 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14426 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14427 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14428 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14432 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) in tg3_nvram_get_pagesize() argument
14436 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14439 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14442 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14445 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14448 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14451 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14454 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14459 static void tg3_get_5752_nvram_info(struct tg3 *tp) in tg3_get_5752_nvram_info() argument
14467 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5752_nvram_info()
14472 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14473 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14476 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14477 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14478 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14483 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14484 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14485 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14489 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
14490 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5752_nvram_info()
14493 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14500 static void tg3_get_5755_nvram_info(struct tg3 *tp) in tg3_get_5755_nvram_info() argument
14508 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5755_nvram_info()
14518 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14519 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14520 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14521 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14524 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14527 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14530 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14536 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14537 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14538 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14539 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14541 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14545 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14549 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14556 static void tg3_get_5787_nvram_info(struct tg3 *tp) in tg3_get_5787_nvram_info() argument
14567 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14568 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14569 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14578 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14579 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14580 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14581 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14586 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14587 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14588 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14589 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14594 static void tg3_get_5761_nvram_info(struct tg3 *tp) in tg3_get_5761_nvram_info() argument
14602 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5761_nvram_info()
14616 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14617 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14618 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14619 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5761_nvram_info()
14620 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14630 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14631 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14632 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14633 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14638 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14645 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14651 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14657 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14663 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14669 static void tg3_get_5906_nvram_info(struct tg3 *tp) in tg3_get_5906_nvram_info() argument
14671 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14672 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5906_nvram_info()
14673 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14676 static void tg3_get_57780_nvram_info(struct tg3 *tp) in tg3_get_57780_nvram_info() argument
14685 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14686 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14687 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14699 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14700 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14701 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14707 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14711 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14715 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14722 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14723 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14724 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14728 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14731 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14734 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14739 tg3_flag_set(tp, NO_NVRAM); in tg3_get_57780_nvram_info()
14743 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_57780_nvram_info()
14744 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14745 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_57780_nvram_info()
14749 static void tg3_get_5717_nvram_info(struct tg3 *tp) in tg3_get_5717_nvram_info() argument
14758 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14759 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14760 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14772 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14773 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14774 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14782 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14785 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14799 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14800 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14801 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14810 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14813 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14818 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5717_nvram_info()
14822 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5717_nvram_info()
14823 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14824 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5717_nvram_info()
14827 static void tg3_get_5720_nvram_info(struct tg3 *tp) in tg3_get_5720_nvram_info() argument
14834 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14836 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14846 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14847 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14848 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14849 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14850 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14852 tp->nvram_size = in tg3_get_5720_nvram_info()
14876 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14877 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14882 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14884 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14898 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14899 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14900 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14906 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14911 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14915 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14918 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14919 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14941 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14942 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14943 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14950 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14956 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14962 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14965 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14966 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14971 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14975 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5720_nvram_info()
14976 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
14977 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14979 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14982 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
14987 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14992 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
14994 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_nvram_init()
14996 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
14997 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
14998 tg3_flag_set(tp, NO_NVRAM); in tg3_nvram_init()
15014 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_nvram_init()
15015 tg3_asic_rev(tp) != ASIC_REV_5701) { in tg3_nvram_init()
15016 tg3_flag_set(tp, NVRAM); in tg3_nvram_init()
15018 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
15019 netdev_warn(tp->dev, in tg3_nvram_init()
15024 tg3_enable_nvram_access(tp); in tg3_nvram_init()
15026 tp->nvram_size = 0; in tg3_nvram_init()
15028 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_nvram_init()
15029 tg3_get_5752_nvram_info(tp); in tg3_nvram_init()
15030 else if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_nvram_init()
15031 tg3_get_5755_nvram_info(tp); in tg3_nvram_init()
15032 else if (tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_nvram_init()
15033 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_nvram_init()
15034 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_nvram_init()
15035 tg3_get_5787_nvram_info(tp); in tg3_nvram_init()
15036 else if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_nvram_init()
15037 tg3_get_5761_nvram_info(tp); in tg3_nvram_init()
15038 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_nvram_init()
15039 tg3_get_5906_nvram_info(tp); in tg3_nvram_init()
15040 else if (tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_nvram_init()
15041 tg3_flag(tp, 57765_CLASS)) in tg3_nvram_init()
15042 tg3_get_57780_nvram_info(tp); in tg3_nvram_init()
15043 else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_nvram_init()
15044 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_nvram_init()
15045 tg3_get_5717_nvram_info(tp); in tg3_nvram_init()
15046 else if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_nvram_init()
15047 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_nvram_init()
15048 tg3_get_5720_nvram_info(tp); in tg3_nvram_init()
15050 tg3_get_nvram_info(tp); in tg3_nvram_init()
15052 if (tp->nvram_size == 0) in tg3_nvram_init()
15053 tg3_get_nvram_size(tp); in tg3_nvram_init()
15055 tg3_disable_nvram_access(tp); in tg3_nvram_init()
15056 tg3_nvram_unlock(tp); in tg3_nvram_init()
15059 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15060 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15062 tg3_get_eeprom_size(tp); in tg3_nvram_init()
15135 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) in tg3_lookup_by_subsys() argument
15141 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15143 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15149 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) in tg3_get_eeprom_hw_cfg() argument
15153 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15154 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15157 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15158 tg3_flag_set(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15160 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
15162 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15163 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15167 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15170 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15171 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15176 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_get_eeprom_hw_cfg()
15183 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_get_eeprom_hw_cfg()
15184 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15186 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); in tg3_get_eeprom_hw_cfg()
15188 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
15189 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_eeprom_hw_cfg()
15190 tg3_asic_rev(tp) != ASIC_REV_5703 && in tg3_get_eeprom_hw_cfg()
15192 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15194 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
15195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); in tg3_get_eeprom_hw_cfg()
15197 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_eeprom_hw_cfg()
15198 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_eeprom_hw_cfg()
15199 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_eeprom_hw_cfg()
15200 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15206 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); in tg3_get_eeprom_hw_cfg()
15217 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15219 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
15220 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15222 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15225 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15234 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15238 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15242 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15247 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15248 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_get_eeprom_hw_cfg()
15249 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15254 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15255 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
15256 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) in tg3_get_eeprom_hw_cfg()
15257 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15260 if (tg3_flag(tp, 5717_PLUS) || in tg3_get_eeprom_hw_cfg()
15261 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_eeprom_hw_cfg()
15262 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15268 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15272 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15273 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
15274 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15280 if ((tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15281 tg3_asic_rev(tp) == ASIC_REV_5701) && in tg3_get_eeprom_hw_cfg()
15282 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15283 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15285 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
15286 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15289 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15290 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15292 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15293 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15294 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15296 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15297 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15301 tg3_flag_set(tp, ENABLE_ASF); in tg3_get_eeprom_hw_cfg()
15302 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15303 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_get_eeprom_hw_cfg()
15307 tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15308 tg3_flag_set(tp, ENABLE_APE); in tg3_get_eeprom_hw_cfg()
15310 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15312 tg3_flag_clear(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15314 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
15316 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15317 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15321 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15326 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15328 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
15329 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_eeprom_hw_cfg()
15330 tg3_chip_rev(tp) != CHIPREV_5784_AX)) && in tg3_get_eeprom_hw_cfg()
15332 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15334 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_get_eeprom_hw_cfg()
15337 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); in tg3_get_eeprom_hw_cfg()
15338 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_eeprom_hw_cfg()
15339 !tg3_flag(tp, 57765_PLUS) && in tg3_get_eeprom_hw_cfg()
15341 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15343 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15345 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15349 tg3_flag_set(tp, RGMII_INBAND_DISABLE); in tg3_get_eeprom_hw_cfg()
15351 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); in tg3_get_eeprom_hw_cfg()
15353 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); in tg3_get_eeprom_hw_cfg()
15356 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15359 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
15360 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15361 tg3_flag(tp, WOL_ENABLE)); in tg3_get_eeprom_hw_cfg()
15363 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15366 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_ape_otp_read() argument
15371 err = tg3_nvram_lock(tp); in tg3_ape_otp_read()
15375 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE); in tg3_ape_otp_read()
15376 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN | in tg3_ape_otp_read()
15378 tg3_ape_read32(tp, TG3_APE_OTP_CTRL); in tg3_ape_otp_read()
15382 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS); in tg3_ape_otp_read()
15384 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); in tg3_ape_otp_read()
15390 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15392 tg3_nvram_unlock(tp); in tg3_ape_otp_read()
15399 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) in tg3_issue_otp_command() argument
15422 static u32 tg3_read_otp_phycfg(struct tg3 *tp) in tg3_read_otp_phycfg() argument
15428 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
15433 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15440 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15448 static void tg3_phy_init_link_config(struct tg3 *tp) in tg3_phy_init_link_config() argument
15452 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15453 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15458 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15467 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15468 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15469 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15470 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15471 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15472 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15474 tp->old_link = -1; in tg3_phy_init_link_config()
15477 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
15484 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_probe()
15485 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15487 if (tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15488 switch (tp->pci_fn) { in tg3_phy_probe()
15490 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15493 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15496 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15499 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15504 if (!tg3_flag(tp, ENABLE_ASF) && in tg3_phy_probe()
15505 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15506 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15507 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15510 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
15511 return tg3_phy_init(tp); in tg3_phy_probe()
15517 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15525 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
15526 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
15536 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15538 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15540 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15542 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15552 p = tg3_lookup_by_subsys(tp); in tg3_phy_probe()
15554 tp->phy_id = p->phy_id; in tg3_phy_probe()
15555 } else if (!tg3_flag(tp, IS_SSB_CORE)) { in tg3_phy_probe()
15566 if (!tp->phy_id || in tg3_phy_probe()
15567 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15568 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15572 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15573 (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_probe()
15574 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_phy_probe()
15575 tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_phy_probe()
15576 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_phy_probe()
15577 (tg3_asic_rev(tp) == ASIC_REV_5717 && in tg3_phy_probe()
15578 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || in tg3_phy_probe()
15579 (tg3_asic_rev(tp) == ASIC_REV_57765 && in tg3_phy_probe()
15580 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) { in tg3_phy_probe()
15581 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15583 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15585 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15587 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15588 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15589 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15592 tg3_phy_init_link_config(tp); in tg3_phy_probe()
15594 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15595 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15596 !tg3_flag(tp, ENABLE_APE) && in tg3_phy_probe()
15597 !tg3_flag(tp, ENABLE_ASF)) { in tg3_phy_probe()
15600 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_phy_probe()
15601 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
15605 err = tg3_phy_reset(tp); in tg3_phy_probe()
15609 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
15611 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
15612 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15613 tp->link_config.flowctrl); in tg3_phy_probe()
15615 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
15621 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15622 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15626 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15632 static void tg3_read_vpd(struct tg3 *tp) in tg3_read_vpd() argument
15639 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); in tg3_read_vpd()
15675 if (len >= sizeof(tp->fw_ver)) in tg3_read_vpd()
15676 len = sizeof(tp->fw_ver) - 1; in tg3_read_vpd()
15677 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15678 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, in tg3_read_vpd()
15695 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15699 if (tp->board_part_number[0]) in tg3_read_vpd()
15703 if (tg3_asic_rev(tp) == ASIC_REV_5717) { in tg3_read_vpd()
15704 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15705 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15706 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15707 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15708 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15711 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_read_vpd()
15712 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15713 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15714 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15715 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15716 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15717 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15718 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15719 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15722 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { in tg3_read_vpd()
15723 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15724 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15725 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15726 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15727 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15728 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15729 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15730 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15731 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15732 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15733 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15734 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15737 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_read_vpd()
15738 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15739 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15740 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15741 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15742 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15743 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15744 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15745 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15748 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_read_vpd()
15749 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15752 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15756 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) in tg3_fw_img_is_valid() argument
15760 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
15762 tg3_nvram_read(tp, offset + 4, &val) || in tg3_fw_img_is_valid()
15769 static void tg3_read_bc_ver(struct tg3 *tp) in tg3_read_bc_ver() argument
15775 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15776 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15779 offset = tg3_nvram_logical_addr(tp, offset); in tg3_read_bc_ver()
15781 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
15785 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
15792 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15796 tg3_nvram_read(tp, offset + 8, &ver_offset)) in tg3_read_bc_ver()
15802 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
15805 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15810 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
15816 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15821 static void tg3_read_hwsb_ver(struct tg3 *tp) in tg3_read_hwsb_ver() argument
15826 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
15834 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15837 static void tg3_read_sb_ver(struct tg3 *tp, u32 val) in tg3_read_sb_ver() argument
15841 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15869 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
15881 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15882 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15886 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15888 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15892 static void tg3_read_mgmtfw_ver(struct tg3 *tp) in tg3_read_mgmtfw_ver() argument
15900 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
15910 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
15912 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15915 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
15916 !tg3_fw_img_is_valid(tp, offset) || in tg3_read_mgmtfw_ver()
15917 tg3_nvram_read(tp, offset + 8, &val)) in tg3_read_mgmtfw_ver()
15922 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15924 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15925 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15929 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
15935 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15939 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15944 static void tg3_probe_ncsi(struct tg3 *tp) in tg3_probe_ncsi() argument
15948 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_probe_ncsi()
15952 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_probe_ncsi()
15956 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) in tg3_probe_ncsi()
15957 tg3_flag_set(tp, APE_HAS_NCSI); in tg3_probe_ncsi()
15960 static void tg3_read_dash_ver(struct tg3 *tp) in tg3_read_dash_ver() argument
15966 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); in tg3_read_dash_ver()
15968 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_read_dash_ver()
15970 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15975 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15977 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15985 static void tg3_read_otp_ver(struct tg3 *tp) in tg3_read_otp_ver() argument
15989 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_read_otp_ver()
15992 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && in tg3_read_otp_ver()
15993 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) && in tg3_read_otp_ver()
16005 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16006 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16010 static void tg3_read_fw_ver(struct tg3 *tp) in tg3_read_fw_ver() argument
16015 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16018 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
16019 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16020 tg3_read_otp_ver(tp); in tg3_read_fw_ver()
16024 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
16028 tg3_read_bc_ver(tp); in tg3_read_fw_ver()
16030 tg3_read_sb_ver(tp, val); in tg3_read_fw_ver()
16032 tg3_read_hwsb_ver(tp); in tg3_read_fw_ver()
16034 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
16035 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
16036 tg3_probe_ncsi(tp); in tg3_read_fw_ver()
16038 tg3_read_dash_ver(tp); in tg3_read_fw_ver()
16040 tg3_read_mgmtfw_ver(tp); in tg3_read_fw_ver()
16044 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16047 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) in tg3_rx_ret_ring_size() argument
16049 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
16051 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
16064 static struct pci_dev *tg3_find_peer(struct tg3 *tp) in tg3_find_peer() argument
16067 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16070 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16071 if (peer && peer != tp->pdev) in tg3_find_peer()
16079 peer = tp->pdev; in tg3_find_peer()
16092 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) in tg3_detect_asic_rev() argument
16094 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16095 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { in tg3_detect_asic_rev()
16101 tg3_flag_set(tp, CPMU_PRESENT); in tg3_detect_asic_rev()
16103 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16104 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16105 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16106 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16107 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16108 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16109 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16110 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16111 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16112 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16113 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16115 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16116 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16117 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16118 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16119 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16120 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16121 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16122 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16123 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16124 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16129 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16135 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) in tg3_detect_asic_rev()
16136 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16138 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) in tg3_detect_asic_rev()
16139 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16141 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_detect_asic_rev()
16142 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_detect_asic_rev()
16143 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_detect_asic_rev()
16144 tg3_flag_set(tp, 5717_PLUS); in tg3_detect_asic_rev()
16146 if (tg3_asic_rev(tp) == ASIC_REV_57765 || in tg3_detect_asic_rev()
16147 tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_detect_asic_rev()
16148 tg3_flag_set(tp, 57765_CLASS); in tg3_detect_asic_rev()
16150 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || in tg3_detect_asic_rev()
16151 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_detect_asic_rev()
16152 tg3_flag_set(tp, 57765_PLUS); in tg3_detect_asic_rev()
16155 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_detect_asic_rev()
16156 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_detect_asic_rev()
16157 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_detect_asic_rev()
16158 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_detect_asic_rev()
16159 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_detect_asic_rev()
16160 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_detect_asic_rev()
16161 tg3_flag(tp, 57765_PLUS)) in tg3_detect_asic_rev()
16162 tg3_flag_set(tp, 5755_PLUS); in tg3_detect_asic_rev()
16164 if (tg3_asic_rev(tp) == ASIC_REV_5780 || in tg3_detect_asic_rev()
16165 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_detect_asic_rev()
16166 tg3_flag_set(tp, 5780_CLASS); in tg3_detect_asic_rev()
16168 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_detect_asic_rev()
16169 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_detect_asic_rev()
16170 tg3_asic_rev(tp) == ASIC_REV_5906 || in tg3_detect_asic_rev()
16171 tg3_flag(tp, 5755_PLUS) || in tg3_detect_asic_rev()
16172 tg3_flag(tp, 5780_CLASS)) in tg3_detect_asic_rev()
16173 tg3_flag_set(tp, 5750_PLUS); in tg3_detect_asic_rev()
16175 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_detect_asic_rev()
16176 tg3_flag(tp, 5750_PLUS)) in tg3_detect_asic_rev()
16177 tg3_flag_set(tp, 5705_PLUS); in tg3_detect_asic_rev()
16180 static bool tg3_10_100_only_device(struct tg3 *tp, in tg3_10_100_only_device() argument
16185 if ((tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_10_100_only_device()
16187 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16191 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_10_100_only_device()
16202 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) in tg3_get_invariants() argument
16217 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16219 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16226 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16228 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16230 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16231 tp->misc_host_ctrl); in tg3_get_invariants()
16233 tg3_detect_asic_rev(tp, misc_ctrl_reg); in tg3_get_invariants()
16252 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
16253 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { in tg3_get_invariants()
16285 tp->pdev->bus->number)) { in tg3_get_invariants()
16286 tg3_flag_set(tp, ICH_WORKAROUND); in tg3_get_invariants()
16293 if (tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_get_invariants()
16315 tp->pdev->bus->number) && in tg3_get_invariants()
16317 tp->pdev->bus->number)) { in tg3_get_invariants()
16318 tg3_flag_set(tp, 5701_DMA_BUG); in tg3_get_invariants()
16331 if (tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16332 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16333 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16343 tp->pdev->bus->number) && in tg3_get_invariants()
16345 tp->pdev->bus->number)) { in tg3_get_invariants()
16346 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16353 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16354 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_get_invariants()
16355 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16358 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) in tg3_get_invariants()
16360 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
16361 tg3_flag_set(tp, HW_TSO_3); in tg3_get_invariants()
16362 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16363 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16364 tg3_flag_set(tp, HW_TSO_2); in tg3_get_invariants()
16365 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16366 tg3_flag_set(tp, HW_TSO_1); in tg3_get_invariants()
16367 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16368 if (tg3_asic_rev(tp) == ASIC_REV_5750 && in tg3_get_invariants()
16369 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) in tg3_get_invariants()
16370 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16371 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_invariants()
16372 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_invariants()
16373 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_get_invariants()
16374 tg3_flag_set(tp, FW_TSO); in tg3_get_invariants()
16375 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16376 if (tg3_asic_rev(tp) == ASIC_REV_5705) in tg3_get_invariants()
16377 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16379 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16383 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
16384 tg3_flag(tp, HW_TSO_2) || in tg3_get_invariants()
16385 tg3_flag(tp, HW_TSO_3) || in tg3_get_invariants()
16386 tg3_flag(tp, FW_TSO)) { in tg3_get_invariants()
16391 tg3_flag_set(tp, TSO_CAPABLE); in tg3_get_invariants()
16393 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16394 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16395 tp->fw_needed = NULL; in tg3_get_invariants()
16398 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) in tg3_get_invariants()
16399 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16401 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_get_invariants()
16402 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16404 tp->irq_max = 1; in tg3_get_invariants()
16406 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16407 tg3_flag_set(tp, SUPPORT_MSI); in tg3_get_invariants()
16408 if (tg3_chip_rev(tp) == CHIPREV_5750_AX || in tg3_get_invariants()
16409 tg3_chip_rev(tp) == CHIPREV_5750_BX || in tg3_get_invariants()
16410 (tg3_asic_rev(tp) == ASIC_REV_5714 && in tg3_get_invariants()
16411 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && in tg3_get_invariants()
16412 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16413 tg3_flag_clear(tp, SUPPORT_MSI); in tg3_get_invariants()
16415 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16416 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16417 tg3_flag_set(tp, 1SHOT_MSI); in tg3_get_invariants()
16420 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16421 tg3_flag_set(tp, SUPPORT_MSIX); in tg3_get_invariants()
16422 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16426 tp->txq_max = 1; in tg3_get_invariants()
16427 tp->rxq_max = 1; in tg3_get_invariants()
16428 if (tp->irq_max > 1) { in tg3_get_invariants()
16429 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16430 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); in tg3_get_invariants()
16432 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16433 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_invariants()
16434 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16437 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16438 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16439 tg3_flag_set(tp, SHORT_DMA_BUG); in tg3_get_invariants()
16441 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_get_invariants()
16442 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16444 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16445 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16446 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16447 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16448 tg3_flag_set(tp, LRG_PROD_RING_CAP); in tg3_get_invariants()
16450 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
16451 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) in tg3_get_invariants()
16452 tg3_flag_set(tp, USE_JUMBO_BDFLAG); in tg3_get_invariants()
16454 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16455 tg3_flag(tp, 5780_CLASS) || in tg3_get_invariants()
16456 tg3_flag(tp, USE_JUMBO_BDFLAG)) in tg3_get_invariants()
16457 tg3_flag_set(tp, JUMBO_CAPABLE); in tg3_get_invariants()
16459 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16462 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16465 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16467 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16469 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16470 tg3_flag_clear(tp, HW_TSO_2); in tg3_get_invariants()
16471 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16473 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16474 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_get_invariants()
16475 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || in tg3_get_invariants()
16476 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) in tg3_get_invariants()
16477 tg3_flag_set(tp, CLKREQ_BUG); in tg3_get_invariants()
16478 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
16479 tg3_flag_set(tp, L1PLLPD_EN); in tg3_get_invariants()
16481 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_get_invariants()
16486 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16487 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16488 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16489 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16490 if (!tp->pcix_cap) { in tg3_get_invariants()
16491 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16497 tg3_flag_set(tp, PCIX_MODE); in tg3_get_invariants()
16507 !tg3_flag(tp, PCI_EXPRESS)) in tg3_get_invariants()
16508 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_get_invariants()
16510 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16511 &tp->pci_cacheline_sz); in tg3_get_invariants()
16512 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16513 &tp->pci_lat_timer); in tg3_get_invariants()
16514 if (tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_get_invariants()
16515 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16516 tp->pci_lat_timer = 64; in tg3_get_invariants()
16517 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16518 tp->pci_lat_timer); in tg3_get_invariants()
16524 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { in tg3_get_invariants()
16528 tg3_flag_set(tp, TXD_MBOX_HWBUG); in tg3_get_invariants()
16535 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16538 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16544 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16545 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16549 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16550 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16554 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16556 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16561 tg3_flag_set(tp, PCI_HIGH_SPEED); in tg3_get_invariants()
16563 tg3_flag_set(tp, PCI_32BIT); in tg3_get_invariants()
16566 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
16569 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16573 tp->read32 = tg3_read32; in tg3_get_invariants()
16574 tp->write32 = tg3_write32; in tg3_get_invariants()
16575 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16576 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16577 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16578 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16581 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
16582 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16583 else if (tg3_asic_rev(tp) == ASIC_REV_5701 || in tg3_get_invariants()
16584 (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_invariants()
16585 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { in tg3_get_invariants()
16593 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16596 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
16597 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16598 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
16599 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16602 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
16603 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16604 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16605 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16606 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16607 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16608 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16610 iounmap(tp->regs); in tg3_get_invariants()
16611 tp->regs = NULL; in tg3_get_invariants()
16613 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16615 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16617 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16618 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16619 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16620 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16621 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16624 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16625 (tg3_flag(tp, PCIX_MODE) && in tg3_get_invariants()
16626 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16627 tg3_asic_rev(tp) == ASIC_REV_5701))) in tg3_get_invariants()
16628 tg3_flag_set(tp, SRAM_USE_CONFIG); in tg3_get_invariants()
16638 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16639 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16640 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16641 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16642 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16643 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16645 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16647 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16648 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16649 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_get_invariants()
16650 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); in tg3_get_invariants()
16654 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_get_invariants()
16655 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16657 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16661 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_get_invariants()
16662 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16663 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16674 tg3_get_eeprom_hw_cfg(tp); in tg3_get_invariants()
16676 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
16677 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16678 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16679 tp->fw_needed = NULL; in tg3_get_invariants()
16682 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
16689 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16692 tg3_ape_lock_init(tp); in tg3_get_invariants()
16693 tp->ape_hb_interval = in tg3_get_invariants()
16702 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16703 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16704 tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_get_invariants()
16705 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16710 else if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_get_invariants()
16711 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16713 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16714 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_get_invariants()
16715 tg3_flag(tp, 57765_CLASS)) in tg3_get_invariants()
16716 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16718 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16719 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16721 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16722 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
16724 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16728 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16729 tp->grc_local_ctrl |= in tg3_get_invariants()
16733 tg3_pwrsrc_switch_to_vmain(tp); in tg3_get_invariants()
16738 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16739 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_get_invariants()
16742 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16743 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16744 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16745 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { in tg3_get_invariants()
16746 tg3_flag_clear(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16748 tg3_flag_set(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16751 if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16752 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16755 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16756 (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16757 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
16758 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || in tg3_get_invariants()
16759 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16760 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16761 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16763 if (tg3_chip_rev(tp) == CHIPREV_5703_AX || in tg3_get_invariants()
16764 tg3_chip_rev(tp) == CHIPREV_5704_AX) in tg3_get_invariants()
16765 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16766 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) in tg3_get_invariants()
16767 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16769 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
16770 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16771 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_invariants()
16772 tg3_asic_rev(tp) != ASIC_REV_57780 && in tg3_get_invariants()
16773 !tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16774 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16775 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_get_invariants()
16776 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16777 tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_get_invariants()
16778 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16779 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16780 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16781 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16782 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16784 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16787 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_invariants()
16788 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_get_invariants()
16789 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16790 if (tp->phy_otp == 0) in tg3_get_invariants()
16791 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16794 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
16795 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16797 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16799 tp->coalesce_mode = 0; in tg3_get_invariants()
16800 if (tg3_chip_rev(tp) != CHIPREV_5700_AX && in tg3_get_invariants()
16801 tg3_chip_rev(tp) != CHIPREV_5700_BX) in tg3_get_invariants()
16802 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16805 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16806 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_get_invariants()
16807 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_get_invariants()
16808 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { in tg3_get_invariants()
16809 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16810 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16813 if (tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_get_invariants()
16814 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_get_invariants()
16815 tg3_flag_set(tp, USE_PHYLIB); in tg3_get_invariants()
16817 err = tg3_mdio_init(tp); in tg3_get_invariants()
16823 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16824 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16833 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16835 tg3_switch_clocks(tp); in tg3_get_invariants()
16843 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16846 !tg3_flag(tp, PCIX_TARGET_HWBUG)) { in tg3_get_invariants()
16847 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16848 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16849 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || in tg3_get_invariants()
16850 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { in tg3_get_invariants()
16857 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16863 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16868 tg3_nvram_init(tp); in tg3_get_invariants()
16871 if (tg3_asic_rev(tp) == ASIC_REV_57766 && in tg3_get_invariants()
16872 !tg3_flag(tp, NO_NVRAM)) in tg3_get_invariants()
16873 tp->fw_needed = NULL; in tg3_get_invariants()
16878 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16881 tg3_flag_set(tp, IS_5788); in tg3_get_invariants()
16883 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
16884 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_get_invariants()
16885 tg3_flag_set(tp, TAGGED_STATUS); in tg3_get_invariants()
16886 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
16887 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16890 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16891 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16892 tp->misc_host_ctrl); in tg3_get_invariants()
16896 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
16897 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16899 tp->mac_mode = 0; in tg3_get_invariants()
16901 if (tg3_10_100_only_device(tp, ent)) in tg3_get_invariants()
16902 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16904 err = tg3_phy_probe(tp); in tg3_get_invariants()
16906 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16908 tg3_mdio_fini(tp); in tg3_get_invariants()
16911 tg3_read_vpd(tp); in tg3_get_invariants()
16912 tg3_read_fw_ver(tp); in tg3_get_invariants()
16914 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16915 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16917 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16918 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16920 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16927 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16928 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16930 tg3_flag_clear(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16936 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16937 tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16938 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16939 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16940 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16944 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16945 tg3_flag_set(tp, POLL_SERDES); in tg3_get_invariants()
16947 tg3_flag_clear(tp, POLL_SERDES); in tg3_get_invariants()
16949 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF)) in tg3_get_invariants()
16950 tg3_flag_set(tp, POLL_CPMU_LINK); in tg3_get_invariants()
16952 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16953 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16954 if (tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16955 tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16956 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16958 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16962 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16963 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16964 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16966 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16971 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_invariants()
16972 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_get_invariants()
16973 tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_get_invariants()
16974 tp->rx_std_max_post = 8; in tg3_get_invariants()
16976 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
16977 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16983 static int tg3_get_device_address(struct tg3 *tp) in tg3_get_device_address() argument
16985 struct net_device *dev = tp->dev; in tg3_get_device_address()
16990 if (!eth_platform_get_mac_address(&tp->pdev->dev, dev->dev_addr)) in tg3_get_device_address()
16993 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_get_device_address()
16994 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); in tg3_get_device_address()
17000 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_device_address()
17001 tg3_flag(tp, 5780_CLASS)) { in tg3_get_device_address()
17004 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
17007 tg3_nvram_unlock(tp); in tg3_get_device_address()
17008 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
17009 if (tp->pci_fn & 1) in tg3_get_device_address()
17011 if (tp->pci_fn > 1) in tg3_get_device_address()
17013 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_device_address()
17017 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); in tg3_get_device_address()
17022 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); in tg3_get_device_address()
17033 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
17034 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
17035 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
17061 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) in tg3_calc_dma_bndry() argument
17067 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17076 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
17077 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_calc_dma_bndry()
17078 !tg3_flag(tp, PCI_EXPRESS)) in tg3_calc_dma_bndry()
17091 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
17110 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17135 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17202 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, in tg3_do_test_dma() argument
17253 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17255 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17257 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17290 static int tg3_test_dma(struct tg3 *tp) in tg3_test_dma() argument
17296 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17303 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17306 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17308 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
17311 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
17313 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17314 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
17315 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_test_dma()
17316 tg3_asic_rev(tp) == ASIC_REV_5750) in tg3_test_dma()
17317 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17319 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17321 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17322 tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_test_dma()
17330 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
17331 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17332 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17334 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17336 if (tg3_asic_rev(tp) == ASIC_REV_5703) in tg3_test_dma()
17339 tp->dma_rwctrl |= in tg3_test_dma()
17343 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { in tg3_test_dma()
17345 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17346 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_test_dma()
17348 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17350 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17353 if (tg3_flag(tp, ONE_DMA_AT_ONCE)) in tg3_test_dma()
17354 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17356 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17357 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17358 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17360 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_test_dma()
17361 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_test_dma()
17363 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17375 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17378 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17381 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_test_dma()
17382 tg3_asic_rev(tp) != ASIC_REV_5701) in tg3_test_dma()
17388 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17389 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17390 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17399 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); in tg3_test_dma()
17401 dev_err(&tp->pdev->dev, in tg3_test_dma()
17408 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); in tg3_test_dma()
17410 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17420 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17422 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17423 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17424 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17427 dev_err(&tp->pdev->dev, in tg3_test_dma()
17441 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17448 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17449 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17452 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17455 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17459 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17464 static void tg3_init_bufmgr_config(struct tg3 *tp) in tg3_init_bufmgr_config() argument
17466 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
17467 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17469 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17471 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17474 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17476 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17478 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17480 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
17481 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17483 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17485 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17487 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
17488 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17490 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17494 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17496 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17498 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17501 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17503 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17505 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17508 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17510 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17512 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17516 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17517 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17520 static char *tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
17522 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17552 static char *tg3_bus_string(struct tg3 *tp, char *str) in tg3_bus_string() argument
17554 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
17557 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
17576 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
17581 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
17588 static void tg3_init_coal(struct tg3 *tp) in tg3_init_coal() argument
17590 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17604 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17612 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
17623 struct tg3 *tp; in tg3_init_one() local
17646 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); in tg3_init_one()
17654 tp = netdev_priv(dev); in tg3_init_one()
17655 tp->pdev = pdev; in tg3_init_one()
17656 tp->dev = dev; in tg3_init_one()
17657 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17658 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17659 tp->irq_sync = 1; in tg3_init_one()
17660 tp->pcierr_recovery = false; in tg3_init_one()
17663 tp->msg_enable = tg3_debug; in tg3_init_one()
17665 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17668 tg3_flag_set(tp, IS_SSB_CORE); in tg3_init_one()
17670 tg3_flag_set(tp, FLUSH_POSTED_WRITES); in tg3_init_one()
17672 tg3_flag_set(tp, ONE_DMA_AT_ONCE); in tg3_init_one()
17674 tg3_flag_set(tp, USE_PHYLIB); in tg3_init_one()
17675 tg3_flag_set(tp, ROBOSWITCH); in tg3_init_one()
17678 tg3_flag_set(tp, RGMII_MODE); in tg3_init_one()
17685 tp->misc_host_ctrl = in tg3_init_one()
17697 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17700 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17702 spin_lock_init(&tp->lock); in tg3_init_one()
17703 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17704 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17706 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17707 if (!tp->regs) { in tg3_init_one()
17713 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17714 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17715 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17716 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17717 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17718 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17719 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17720 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17721 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17722 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17723 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17724 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17725 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17726 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17727 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17728 tg3_flag_set(tp, ENABLE_APE); in tg3_init_one()
17729 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17730 if (!tp->aperegs) { in tg3_init_one()
17738 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17739 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17746 err = tg3_get_invariants(tp, ent); in tg3_init_one()
17759 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
17761 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
17792 tg3_init_bufmgr_config(tp); in tg3_init_one()
17797 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { in tg3_init_one()
17800 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
17808 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
17809 tg3_flag(tp, HW_TSO_2) || in tg3_init_one()
17810 tg3_flag(tp, HW_TSO_3)) && in tg3_init_one()
17813 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
17816 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
17817 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_init_one()
17818 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_init_one()
17819 tg3_chip_rev(tp) != CHIPREV_5784_AX) || in tg3_init_one()
17820 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_init_one()
17821 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_init_one()
17834 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_init_one()
17835 !tg3_flag(tp, CPMU_PRESENT)) in tg3_init_one()
17844 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17846 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && in tg3_init_one()
17847 !tg3_flag(tp, TSO_CAPABLE) && in tg3_init_one()
17849 tg3_flag_set(tp, MAX_RXPEND_64); in tg3_init_one()
17850 tp->rx_pending = 63; in tg3_init_one()
17853 err = tg3_get_device_address(tp); in tg3_init_one()
17863 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17864 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17866 tnapi->tp = tp; in tg3_init_one()
17883 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
17911 tg3_full_lock(tp, 0); in tg3_init_one()
17913 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_init_one()
17914 tg3_full_unlock(tp); in tg3_init_one()
17917 err = tg3_test_dma(tp); in tg3_init_one()
17923 tg3_init_coal(tp); in tg3_init_one()
17927 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_init_one()
17928 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_init_one()
17929 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_init_one()
17930 tg3_flag_set(tp, PTP_CAPABLE); in tg3_init_one()
17932 tg3_timer_init(tp); in tg3_init_one()
17934 tg3_carrier_off(tp); in tg3_init_one()
17942 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_init_one()
17943 tg3_ptp_init(tp); in tg3_init_one()
17944 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17945 &tp->pdev->dev); in tg3_init_one()
17946 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17947 tp->ptp_clock = NULL; in tg3_init_one()
17951 tp->board_part_number, in tg3_init_one()
17952 tg3_chip_rev_id(tp), in tg3_init_one()
17953 tg3_bus_string(tp, str), in tg3_init_one()
17956 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17959 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17961 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17968 tg3_phy_string(tp), ethtype, in tg3_init_one()
17969 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17970 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17975 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
17976 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17977 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
17978 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
17980 tp->dma_rwctrl, in tg3_init_one()
17989 if (tp->aperegs) { in tg3_init_one()
17990 iounmap(tp->aperegs); in tg3_init_one()
17991 tp->aperegs = NULL; in tg3_init_one()
17995 if (tp->regs) { in tg3_init_one()
17996 iounmap(tp->regs); in tg3_init_one()
17997 tp->regs = NULL; in tg3_init_one()
18017 struct tg3 *tp = netdev_priv(dev); in tg3_remove_one() local
18019 tg3_ptp_fini(tp); in tg3_remove_one()
18021 release_firmware(tp->fw); in tg3_remove_one()
18023 tg3_reset_task_cancel(tp); in tg3_remove_one()
18025 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
18026 tg3_phy_fini(tp); in tg3_remove_one()
18027 tg3_mdio_fini(tp); in tg3_remove_one()
18031 if (tp->aperegs) { in tg3_remove_one()
18032 iounmap(tp->aperegs); in tg3_remove_one()
18033 tp->aperegs = NULL; in tg3_remove_one()
18035 if (tp->regs) { in tg3_remove_one()
18036 iounmap(tp->regs); in tg3_remove_one()
18037 tp->regs = NULL; in tg3_remove_one()
18049 struct tg3 *tp = netdev_priv(dev); in tg3_suspend() local
18057 tg3_reset_task_cancel(tp); in tg3_suspend()
18058 tg3_phy_stop(tp); in tg3_suspend()
18059 tg3_netif_stop(tp); in tg3_suspend()
18061 tg3_timer_stop(tp); in tg3_suspend()
18063 tg3_full_lock(tp, 1); in tg3_suspend()
18064 tg3_disable_ints(tp); in tg3_suspend()
18065 tg3_full_unlock(tp); in tg3_suspend()
18069 tg3_full_lock(tp, 0); in tg3_suspend()
18070 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_suspend()
18071 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_suspend()
18072 tg3_full_unlock(tp); in tg3_suspend()
18074 err = tg3_power_down_prepare(tp); in tg3_suspend()
18078 tg3_full_lock(tp, 0); in tg3_suspend()
18080 tg3_flag_set(tp, INIT_COMPLETE); in tg3_suspend()
18081 err2 = tg3_restart_hw(tp, true); in tg3_suspend()
18085 tg3_timer_start(tp); in tg3_suspend()
18088 tg3_netif_start(tp); in tg3_suspend()
18091 tg3_full_unlock(tp); in tg3_suspend()
18094 tg3_phy_start(tp); in tg3_suspend()
18105 struct tg3 *tp = netdev_priv(dev); in tg3_resume() local
18115 tg3_full_lock(tp, 0); in tg3_resume()
18117 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_resume()
18119 tg3_flag_set(tp, INIT_COMPLETE); in tg3_resume()
18120 err = tg3_restart_hw(tp, in tg3_resume()
18121 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18125 tg3_timer_start(tp); in tg3_resume()
18127 tg3_netif_start(tp); in tg3_resume()
18130 tg3_full_unlock(tp); in tg3_resume()
18133 tg3_phy_start(tp); in tg3_resume()
18146 struct tg3 *tp = netdev_priv(dev); in tg3_shutdown() local
18155 tg3_power_down(tp); in tg3_shutdown()
18172 struct tg3 *tp = netdev_priv(netdev); in tg3_io_error_detected() local
18185 tp->pcierr_recovery = true; in tg3_io_error_detected()
18187 tg3_phy_stop(tp); in tg3_io_error_detected()
18189 tg3_netif_stop(tp); in tg3_io_error_detected()
18191 tg3_timer_stop(tp); in tg3_io_error_detected()
18194 tg3_reset_task_cancel(tp); in tg3_io_error_detected()
18199 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18200 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18201 tg3_full_unlock(tp); in tg3_io_error_detected()
18206 tg3_napi_enable(tp); in tg3_io_error_detected()
18231 struct tg3 *tp = netdev_priv(netdev); in tg3_io_slot_reset() local
18252 err = tg3_power_up(tp); in tg3_io_slot_reset()
18260 tg3_napi_enable(tp); in tg3_io_slot_reset()
18278 struct tg3 *tp = netdev_priv(netdev); in tg3_io_resume() local
18286 tg3_full_lock(tp, 0); in tg3_io_resume()
18287 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_io_resume()
18288 tg3_flag_set(tp, INIT_COMPLETE); in tg3_io_resume()
18289 err = tg3_restart_hw(tp, true); in tg3_io_resume()
18291 tg3_full_unlock(tp); in tg3_io_resume()
18298 tg3_timer_start(tp); in tg3_io_resume()
18300 tg3_netif_start(tp); in tg3_io_resume()
18302 tg3_full_unlock(tp); in tg3_io_resume()
18304 tg3_phy_start(tp); in tg3_io_resume()
18307 tp->pcierr_recovery = false; in tg3_io_resume()