575 		u32 *data = bnx2x_sp(bp, wb_data[0]);  in bnx2x_write_dmae()
610 		u32 *data = bnx2x_sp(bp, wb_data[0]);  in bnx2x_read_dmae()
629 	dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));  in bnx2x_read_dmae()
630 	dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));  in bnx2x_read_dmae()
6701 		val = *bnx2x_sp(bp, wb_data[0]);  in bnx2x_int_mem_test()
6757 		val = *bnx2x_sp(bp, wb_data[0]);  in bnx2x_int_mem_test()
7444 		val = *bnx2x_sp(bp, wb_data[0]);  in bnx2x_init_hw_common()
8223 			bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),  in bnx2x_init_hw_func()
10499 			u32 wb_data[2];  in bnx2x_prev_unload_close_mac()  local
10512 			wb_data[0] = REG_RD(bp, base_addr + offset);  in bnx2x_prev_unload_close_mac()
10513 			wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);  in bnx2x_prev_unload_close_mac()
10515 			vals->bmac_val[0] = wb_data[0];  in bnx2x_prev_unload_close_mac()
10516 			vals->bmac_val[1] = wb_data[1];  in bnx2x_prev_unload_close_mac()
10517 			wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;  in bnx2x_prev_unload_close_mac()
10518 			REG_WR(bp, vals->bmac_addr, wb_data[0]);  in bnx2x_prev_unload_close_mac()
10519 			REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);  in bnx2x_prev_unload_close_mac()
15298 	u32 wb_data[2];  in bnx2x_cyclecounter_read()  local
15302 		    NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);  in bnx2x_cyclecounter_read()
15303 	phc_cycles = wb_data[1];  in bnx2x_cyclecounter_read()
15304 	phc_cycles = (phc_cycles << 32) + wb_data[0];  in bnx2x_cyclecounter_read()
15504 	u32 wb_data[2];  in bnx2x_configure_ptp()  local
15525 	wb_data[0] = 0;  in bnx2x_configure_ptp()
15526 	wb_data[1] = 0;  in bnx2x_configure_ptp()
15527 	REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);  in bnx2x_configure_ptp()