1451 				   params->phy[phy_index].mdio_ctrl);  in bnx2x_set_mdio_emac_per_phy()
2596 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2597 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_write()
2604 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl22_write()
2609 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2619 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_write()
2632 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2633 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_read()
2640 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl22_read()
2645 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2658 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_read()
2675 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_read()
2679 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2685 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2690 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2706 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2711 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2735 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2750 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_write()
2754 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
2761 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2766 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2781 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2786 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2808 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
8294 	fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in bnx2x_verify_sfp_module()
11630 	.mdio_ctrl	= 0,
11656 	.mdio_ctrl	= 0,
11691 	.mdio_ctrl	= 0,
11726 	.mdio_ctrl	= 0,
11766 	.mdio_ctrl	= 0,
11795 	.mdio_ctrl	= 0,
11826 	.mdio_ctrl	= 0,
11854 	.mdio_ctrl	= 0,
11885 	.mdio_ctrl	= 0,
11917 	.mdio_ctrl	= 0,
11947 	.mdio_ctrl	= 0,
11984 	.mdio_ctrl	= 0,
12021 	.mdio_ctrl	= 0,
12055 	.mdio_ctrl	= 0,
12089 	.mdio_ctrl	= 0,
12122 	.mdio_ctrl	= 0,
12335 	phy->mdio_ctrl = bnx2x_get_emac_base(bp,  in bnx2x_populate_int_phy()
12344 		   port, phy->addr, phy->mdio_ctrl);  in bnx2x_populate_int_phy()
12458 	phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);  in bnx2x_populate_ext_phy()
12474 		   phy->addr, phy->mdio_ctrl);  in bnx2x_populate_ext_phy()