Lines Matching +full:asym +full:- +full:pause
1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
269 link_status = REG_RD(bp, params->shmem_base + in bnx2x_check_lfa()
271 port_mb[params->port].link_status)); in bnx2x_check_lfa()
278 if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN) in bnx2x_check_lfa()
282 if (params->loopback_mode) in bnx2x_check_lfa()
286 if (!params->lfa_base) in bnx2x_check_lfa()
289 if (params->num_phys == 3) { in bnx2x_check_lfa()
298 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); in bnx2x_check_lfa()
307 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); in bnx2x_check_lfa()
316 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); in bnx2x_check_lfa()
326 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
330 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { in bnx2x_check_lfa()
333 params->speed_cap_mask[cfg_idx]); in bnx2x_check_lfa()
339 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
343 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { in bnx2x_check_lfa()
345 cur_req_fc_auto_adv, params->req_fc_auto_adv); in bnx2x_check_lfa()
349 eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_check_lfa()
351 eee_status[params->port])); in bnx2x_check_lfa()
354 (params->eee_mode & EEE_MODE_ENABLE_LPI)) || in bnx2x_check_lfa()
356 (params->eee_mode & EEE_MODE_ADV_LPI))) { in bnx2x_check_lfa()
357 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode, in bnx2x_check_lfa()
415 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_set_cfg_pin()
417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; in bnx2x_set_cfg_pin()
418 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; in bnx2x_set_cfg_pin()
426 return -EINVAL; in bnx2x_get_cfg_pin()
428 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_get_cfg_pin()
430 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; in bnx2x_get_cfg_pin()
431 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; in bnx2x_get_cfg_pin()
443 struct bnx2x *bp = params->bp; in bnx2x_ets_e2e3a0_disabled()
447 /* mapping between entry priority to client number (0,1,2 -debug and in bnx2x_ets_e2e3a0_disabled()
448 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) in bnx2x_ets_e2e3a0_disabled()
451 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 in bnx2x_ets_e2e3a0_disabled()
456 * as strict. Bits 0,1,2 - debug and management entries, 3 - in bnx2x_ets_e2e3a0_disabled()
457 * COS0 entry, 4 - COS1 entry. in bnx2x_ets_e2e3a0_disabled()
502 if (vars->link_up) { in bnx2x_ets_get_min_w_val_nig()
503 if (vars->line_speed == SPEED_20000) in bnx2x_ets_get_min_w_val_nig()
534 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
535 const u8 port = params->port; in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
572 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_nig_disabled()
573 const u8 port = params->port; in bnx2x_ets_e3b0_nig_disabled()
575 /* Mapping between entry priority to client number (0,1,2 -debug and in bnx2x_ets_e3b0_nig_disabled()
576 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - in bnx2x_ets_e3b0_nig_disabled()
577 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by in bnx2x_ets_e3b0_nig_disabled()
607 * as strict. Bits 0,1,2 - debug and management entries, 3 - in bnx2x_ets_e3b0_nig_disabled()
608 * COS0 entry, 4 - COS1 entry. in bnx2x_ets_e3b0_nig_disabled()
622 * for here is note appropriate.In 2 port mode port0 only COS0-5 in bnx2x_ets_e3b0_nig_disabled()
624 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT in bnx2x_ets_e3b0_nig_disabled()
656 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
659 const u8 port = params->port; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
663 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
664 * port mode port1 has COS0-2 that can be used for WFQ. in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
688 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_pbf_disabled()
689 const u8 port = params->port; in bnx2x_ets_e3b0_pbf_disabled()
695 /* Mapping between entry priority to client number 0 - COS0 in bnx2x_ets_e3b0_pbf_disabled()
696 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. in bnx2x_ets_e3b0_pbf_disabled()
697 * TODO_ETS - Should be done by reset value or init tool in bnx2x_ets_e3b0_pbf_disabled()
706 /* TODO_ETS - Should be done by reset value or init tool */ in bnx2x_ets_e3b0_pbf_disabled()
723 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. in bnx2x_ets_e3b0_pbf_disabled()
724 * In 4 port mode port1 has COS0-2 that can be used for WFQ. in bnx2x_ets_e3b0_pbf_disabled()
747 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_disabled()
752 return -EINVAL; in bnx2x_ets_e3b0_disabled()
770 struct bnx2x *bp = params->bp; in bnx2x_ets_disabled()
778 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n"); in bnx2x_ets_disabled()
779 return -EINVAL; in bnx2x_ets_disabled()
795 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_cli_map()
796 const u8 port = params->port; in bnx2x_ets_e3b0_cli_map()
834 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ in bnx2x_ets_e3b0_set_cos_bw()
863 return -EINVAL; in bnx2x_ets_e3b0_set_cos_bw()
869 return -EINVAL; in bnx2x_ets_e3b0_set_cos_bw()
875 return -EINVAL; in bnx2x_ets_e3b0_set_cos_bw()
897 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_get_total_bw()
903 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { in bnx2x_ets_e3b0_get_total_bw()
904 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { in bnx2x_ets_e3b0_get_total_bw()
906 if (!ets_params->cos[cos_idx].params.bw_params.bw) { in bnx2x_ets_e3b0_get_total_bw()
912 ets_params->cos[cos_idx].params.bw_params.bw in bnx2x_ets_e3b0_get_total_bw()
916 ets_params->cos[cos_idx].params.bw_params.bw; in bnx2x_ets_e3b0_get_total_bw()
925 return -EINVAL; in bnx2x_ets_e3b0_get_total_bw()
957 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_pri_to_cos_set()
958 const u8 port = params->port; in bnx2x_ets_e3b0_sp_pri_to_cos_set()
965 return -EINVAL; in bnx2x_ets_e3b0_sp_pri_to_cos_set()
972 return -EINVAL; in bnx2x_ets_e3b0_sp_pri_to_cos_set()
1038 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1040 const u8 port = params->port; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1049 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1058 return -EINVAL; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1073 return -EINVAL; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1100 return -EINVAL; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1132 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_config()
1134 const u8 port = params->port; in bnx2x_ets_e3b0_config()
1148 return -EINVAL; in bnx2x_ets_e3b0_config()
1151 if ((ets_params->num_of_cos > max_num_of_cos)) { in bnx2x_ets_e3b0_config()
1154 return -EINVAL; in bnx2x_ets_e3b0_config()
1166 return -EINVAL; in bnx2x_ets_e3b0_config()
1176 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { in bnx2x_ets_e3b0_config()
1177 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { in bnx2x_ets_e3b0_config()
1185 ets_params->cos[cos_entry].params.bw_params.bw, in bnx2x_ets_e3b0_config()
1188 ets_params->cos[cos_entry].state){ in bnx2x_ets_e3b0_config()
1194 ets_params->cos[cos_entry].params.sp_params.pri, in bnx2x_ets_e3b0_config()
1200 return -EINVAL; in bnx2x_ets_e3b0_config()
1233 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit_common()
1244 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 in bnx2x_ets_bw_limit_common()
1259 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 in bnx2x_ets_bw_limit_common()
1260 * entry, 4 - COS1 entry. in bnx2x_ets_bw_limit_common()
1278 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit()
1309 struct bnx2x *bp = params->bp; in bnx2x_ets_strict()
1314 * as strict. Bits 0,1,2 - debug and management entries, in bnx2x_ets_strict()
1315 * 3 - COS0 entry, 4 - COS1 entry. in bnx2x_ets_strict()
1333 /* Mapping between entry priority to client number (0,1,2 -debug and in bnx2x_ets_strict()
1334 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) in bnx2x_ets_strict()
1337 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 in bnx2x_ets_strict()
1338 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 in bnx2x_ets_strict()
1353 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_xmac()
1358 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_update_pfc_xmac()
1360 /* Initialize pause and pfc registers */ in bnx2x_update_pfc_xmac()
1366 if (!(params->feature_config_flags & in bnx2x_update_pfc_xmac()
1369 /* RX flow control - Process pause frame in receive direction in bnx2x_update_pfc_xmac()
1371 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) in bnx2x_update_pfc_xmac()
1374 /* TX flow control - Send pause packet when buffer is full */ in bnx2x_update_pfc_xmac()
1375 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_update_pfc_xmac()
1383 /* Write pause and PFC registers */ in bnx2x_update_pfc_xmac()
1391 /* Write pause and PFC registers */ in bnx2x_update_pfc_xmac()
1397 /* Set MAC address for source TX Pause/PFC frames */ in bnx2x_update_pfc_xmac()
1399 ((params->mac_addr[2] << 24) | in bnx2x_update_pfc_xmac()
1400 (params->mac_addr[3] << 16) | in bnx2x_update_pfc_xmac()
1401 (params->mac_addr[4] << 8) | in bnx2x_update_pfc_xmac()
1402 (params->mac_addr[5]))); in bnx2x_update_pfc_xmac()
1404 ((params->mac_addr[0] << 8) | in bnx2x_update_pfc_xmac()
1405 (params->mac_addr[1]))); in bnx2x_update_pfc_xmac()
1448 for (phy_index = INT_PHY; phy_index < params->num_phys; in bnx2x_set_mdio_emac_per_phy()
1450 bnx2x_set_mdio_clk(bp, params->chip_id, in bnx2x_set_mdio_emac_per_phy()
1451 params->phy[phy_index].mdio_ctrl); in bnx2x_set_mdio_emac_per_phy()
1457 /* Check 4-port override enabled */ in bnx2x_is_4_port_mode()
1460 /* Return 4-port mode override value */ in bnx2x_is_4_port_mode()
1463 /* Return 4-port mode from input pin */ in bnx2x_is_4_port_mode()
1471 struct bnx2x *bp = params->bp; in bnx2x_emac_init()
1472 u8 port = params->port; in bnx2x_emac_init()
1483 /* init emac - use read-modify-write */ in bnx2x_emac_init()
1496 timeout--; in bnx2x_emac_init()
1501 val = ((params->mac_addr[0] << 8) | in bnx2x_emac_init()
1502 params->mac_addr[1]); in bnx2x_emac_init()
1505 val = ((params->mac_addr[2] << 24) | in bnx2x_emac_init()
1506 (params->mac_addr[3] << 16) | in bnx2x_emac_init()
1507 (params->mac_addr[4] << 8) | in bnx2x_emac_init()
1508 params->mac_addr[5]); in bnx2x_emac_init()
1516 struct bnx2x *bp = params->bp; in bnx2x_set_xumac_nig()
1518 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1520 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1528 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bnx2x_set_umac_rxtx()
1530 struct bnx2x *bp = params->bp; in bnx2x_set_umac_rxtx()
1532 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) in bnx2x_set_umac_rxtx()
1549 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bnx2x_umac_enable()
1550 struct bnx2x *bp = params->bp; in bnx2x_umac_enable()
1553 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); in bnx2x_umac_enable()
1557 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); in bnx2x_umac_enable()
1562 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1568 switch (vars->line_speed) { in bnx2x_umac_enable()
1583 vars->line_speed); in bnx2x_umac_enable()
1586 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) in bnx2x_umac_enable()
1589 if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) in bnx2x_umac_enable()
1592 if (vars->duplex == DUPLEX_HALF) in bnx2x_umac_enable()
1599 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { in bnx2x_umac_enable()
1608 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ in bnx2x_umac_enable()
1610 ((params->mac_addr[2] << 24) | in bnx2x_umac_enable()
1611 (params->mac_addr[3] << 16) | in bnx2x_umac_enable()
1612 (params->mac_addr[4] << 8) | in bnx2x_umac_enable()
1613 (params->mac_addr[5]))); in bnx2x_umac_enable()
1615 ((params->mac_addr[0] << 8) | in bnx2x_umac_enable()
1616 (params->mac_addr[1]))); in bnx2x_umac_enable()
1633 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame in bnx2x_umac_enable()
1638 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); in bnx2x_umac_enable()
1639 vars->mac_type = MAC_TYPE_UMAC; in bnx2x_umac_enable()
1646 struct bnx2x *bp = params->bp; in bnx2x_xmac_init()
1649 /* In 4-port mode, need to set the mode only once, so if XMAC is in bnx2x_xmac_init()
1662 "XMAC already out of reset in 4-port mode\n"); in bnx2x_xmac_init()
1708 u8 port = params->port; in bnx2x_set_xmac_rxtx()
1709 struct bnx2x *bp = params->bp; in bnx2x_set_xmac_rxtx()
1738 struct bnx2x *bp = params->bp; in bnx2x_xmac_enable()
1741 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_xmac_enable()
1743 bnx2x_xmac_init(params, vars->line_speed); in bnx2x_xmac_enable()
1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1757 if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) { in bnx2x_xmac_enable()
1775 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { in bnx2x_xmac_enable()
1786 /* Set MAC in XLGMII mode for dual-mode */ in bnx2x_xmac_enable()
1787 if ((vars->line_speed == SPEED_20000) && in bnx2x_xmac_enable()
1788 (params->phy[INT_PHY].supported & in bnx2x_xmac_enable()
1797 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); in bnx2x_xmac_enable()
1799 vars->mac_type = MAC_TYPE_XMAC; in bnx2x_xmac_enable()
1807 struct bnx2x *bp = params->bp; in bnx2x_emac_enable()
1808 u8 port = params->port; in bnx2x_emac_enable()
1822 if (vars->phy_flags & PHY_XGXS_FLAG) { in bnx2x_emac_enable()
1823 u32 ser_lane = ((params->lane_config & in bnx2x_emac_enable()
1828 /* select the master lanes (out of 0-3) */ in bnx2x_emac_enable()
1844 /* pause enable/disable */ in bnx2x_emac_enable()
1851 if (!(params->feature_config_flags & in bnx2x_emac_enable()
1853 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) in bnx2x_emac_enable()
1858 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_emac_enable()
1871 /* Setting this bit causes MAC control frames (except for pause in bnx2x_emac_enable()
1873 * affect on the operation of the pause frames. This bit effects in bnx2x_emac_enable()
1879 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { in bnx2x_emac_enable()
1923 if ((params->feature_config_flags & in bnx2x_emac_enable()
1925 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) in bnx2x_emac_enable()
1933 vars->mac_type = MAC_TYPE_EMAC; in bnx2x_emac_enable()
1941 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac1()
1942 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in bnx2x_update_pfc_bmac1()
1946 if ((!(params->feature_config_flags & in bnx2x_update_pfc_bmac1()
1948 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) in bnx2x_update_pfc_bmac1()
1949 /* Enable BigMAC to react on received Pause packets */ in bnx2x_update_pfc_bmac1()
1957 if (!(params->feature_config_flags & in bnx2x_update_pfc_bmac1()
1959 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) in bnx2x_update_pfc_bmac1()
1974 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac2()
1975 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in bnx2x_update_pfc_bmac2()
1979 if ((!(params->feature_config_flags & in bnx2x_update_pfc_bmac2()
1981 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)) in bnx2x_update_pfc_bmac2()
1982 /* Enable BigMAC to react on received Pause packets */ in bnx2x_update_pfc_bmac2()
1991 if (!(params->feature_config_flags & in bnx2x_update_pfc_bmac2()
1993 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) in bnx2x_update_pfc_bmac2()
1999 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) { in bnx2x_update_pfc_bmac2()
2023 * re-sending of PP packets amd enable automatic re-send of in bnx2x_update_pfc_bmac2()
2024 * Per-Priroity Packet as long as pp_gen is asserted and in bnx2x_update_pfc_bmac2()
2028 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) in bnx2x_update_pfc_bmac2()
2029 val |= (1<<16); /* enable automatic re-send */ in bnx2x_update_pfc_bmac2()
2042 /* When PFC enabled, Pass pause frames towards the NIG. */ in bnx2x_update_pfc_bmac2()
2043 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) in bnx2x_update_pfc_bmac2()
2080 return -EINVAL; in bnx2x_pfc_nig_rx_priority_mask()
2085 return -EINVAL; in bnx2x_pfc_nig_rx_priority_mask()
2090 return -EINVAL; in bnx2x_pfc_nig_rx_priority_mask()
2101 struct bnx2x *bp = params->bp; in bnx2x_update_mng()
2103 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2105 port_mb[params->port].link_status), link_status); in bnx2x_update_mng()
2110 struct bnx2x *bp = params->bp; in bnx2x_update_link_attr()
2113 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2115 link_attr_sync[params->port]), link_attr); in bnx2x_update_link_attr()
2125 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_nig()
2126 u8 port = params->port; in bnx2x_update_pfc_nig()
2128 int set_pfc = params->feature_config_flags & in bnx2x_update_pfc_nig()
2133 * MAC control frames (that are not pause packets) in bnx2x_update_pfc_nig()
2155 llfc_out_en = nig_params->llfc_out_en; in bnx2x_update_pfc_nig()
2156 llfc_enable = nig_params->llfc_enable; in bnx2x_update_pfc_nig()
2157 pause_enable = nig_params->pause_enable; in bnx2x_update_pfc_nig()
2158 } else /* Default non PFC mode - PAUSE */ in bnx2x_update_pfc_nig()
2195 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; in bnx2x_update_pfc_nig()
2197 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) in bnx2x_update_pfc_nig()
2199 nig_params->rx_cos_priority_mask[i], port); in bnx2x_update_pfc_nig()
2203 nig_params->llfc_high_priority_classes); in bnx2x_update_pfc_nig()
2207 nig_params->llfc_low_priority_classes); in bnx2x_update_pfc_nig()
2218 /* The PFC and pause are orthogonal to one another, meaning when in bnx2x_update_pfc()
2219 * PFC is enabled, the pause are disabled, and when PFC is in bnx2x_update_pfc()
2220 * disabled, pause are set according to the pause result. in bnx2x_update_pfc()
2223 struct bnx2x *bp = params->bp; in bnx2x_update_pfc()
2224 u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC); in bnx2x_update_pfc()
2226 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) in bnx2x_update_pfc()
2227 vars->link_status |= LINK_STATUS_PFC_ENABLED; in bnx2x_update_pfc()
2229 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; in bnx2x_update_pfc()
2231 bnx2x_update_mng(params, vars->link_status); in bnx2x_update_pfc()
2236 if (!vars->link_up) in bnx2x_update_pfc()
2242 if (vars->mac_type == MAC_TYPE_XMAC) in bnx2x_update_pfc()
2247 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) in bnx2x_update_pfc()
2259 if ((params->feature_config_flags & in bnx2x_update_pfc()
2261 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) in bnx2x_update_pfc()
2263 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2272 struct bnx2x *bp = params->bp; in bnx2x_bmac1_enable()
2273 u8 port = params->port; in bnx2x_bmac1_enable()
2288 wb_data[0] = ((params->mac_addr[2] << 24) | in bnx2x_bmac1_enable()
2289 (params->mac_addr[3] << 16) | in bnx2x_bmac1_enable()
2290 (params->mac_addr[4] << 8) | in bnx2x_bmac1_enable()
2291 params->mac_addr[5]); in bnx2x_bmac1_enable()
2292 wb_data[1] = ((params->mac_addr[0] << 8) | in bnx2x_bmac1_enable()
2293 params->mac_addr[1]); in bnx2x_bmac1_enable()
2336 struct bnx2x *bp = params->bp; in bnx2x_bmac2_enable()
2337 u8 port = params->port; in bnx2x_bmac2_enable()
2358 wb_data[0] = ((params->mac_addr[2] << 24) | in bnx2x_bmac2_enable()
2359 (params->mac_addr[3] << 16) | in bnx2x_bmac2_enable()
2360 (params->mac_addr[4] << 8) | in bnx2x_bmac2_enable()
2361 params->mac_addr[5]); in bnx2x_bmac2_enable()
2362 wb_data[1] = ((params->mac_addr[0] << 8) | in bnx2x_bmac2_enable()
2363 params->mac_addr[1]); in bnx2x_bmac2_enable()
2388 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2; in bnx2x_bmac2_enable()
2402 u8 port = params->port; in bnx2x_bmac_enable()
2403 struct bnx2x *bp = params->bp; in bnx2x_bmac_enable()
2427 if ((params->feature_config_flags & in bnx2x_bmac_enable()
2429 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)) in bnx2x_bmac_enable()
2438 vars->mac_type = MAC_TYPE_BMAC; in bnx2x_bmac_enable()
2471 struct bnx2x *bp = params->bp; in bnx2x_pbf_update()
2472 u8 port = params->port; in bnx2x_pbf_update()
2487 count--; in bnx2x_pbf_update()
2493 return -EINVAL; in bnx2x_pbf_update()
2505 init_crd = 778; /* (800-18-4) */ in bnx2x_pbf_update()
2516 init_crd = thresh + 553 - 22; in bnx2x_pbf_update()
2521 return -EINVAL; in bnx2x_pbf_update()
2539 * bnx2x_get_emac_base - retrive emac base address
2596 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2597 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2601 tmp = ((phy->addr << 21) | (reg << 16) | val | in bnx2x_cl22_write()
2604 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2609 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2617 rc = -EFAULT; in bnx2x_cl22_write()
2619 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2632 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2633 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2637 val = ((phy->addr << 21) | (reg << 16) | in bnx2x_cl22_read()
2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2645 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2656 rc = -EFAULT; in bnx2x_cl22_read()
2658 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2672 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_read()
2675 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2678 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2679 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2682 val = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_read()
2685 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2690 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2698 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2700 rc = -EFAULT; in bnx2x_cl45_read()
2703 val = ((phy->addr << 21) | (devad << 16) | in bnx2x_cl45_read()
2706 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2711 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2720 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2722 rc = -EFAULT; in bnx2x_cl45_read()
2726 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_read()
2727 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_read()
2728 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_read()
2734 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_read()
2735 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2747 if (phy->flags & FLAGS_MDC_MDIO_WA_G) { in bnx2x_cl45_write()
2750 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2753 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2754 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2758 tmp = ((phy->addr << 21) | (devad << 16) | reg | in bnx2x_cl45_write()
2761 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2766 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2774 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2775 rc = -EFAULT; in bnx2x_cl45_write()
2778 tmp = ((phy->addr << 21) | (devad << 16) | val | in bnx2x_cl45_write()
2781 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2786 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2795 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2796 rc = -EFAULT; in bnx2x_cl45_write()
2800 if (phy->flags & FLAGS_MDC_MDIO_WA) { in bnx2x_cl45_write()
2801 phy->flags ^= FLAGS_DUMMY_READ; in bnx2x_cl45_write()
2802 if (phy->flags & FLAGS_DUMMY_READ) { in bnx2x_cl45_write()
2807 if (phy->flags & FLAGS_MDC_MDIO_WA_B0) in bnx2x_cl45_write()
2808 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2818 struct bnx2x *bp = params->bp; in bnx2x_eee_has_cap()
2820 if (REG_RD(bp, params->shmem2_base) <= in bnx2x_eee_has_cap()
2821 offsetof(struct shmem2_region, eee_status[params->port])) in bnx2x_eee_has_cap()
2870 struct bnx2x *bp = params->bp; in bnx2x_eee_calc_timer()
2872 if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) { in bnx2x_eee_calc_timer()
2873 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { in bnx2x_eee_calc_timer()
2874 /* time value in eee_mode --> used directly*/ in bnx2x_eee_calc_timer()
2875 eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK; in bnx2x_eee_calc_timer()
2877 /* hsi value in eee_mode --> time */ in bnx2x_eee_calc_timer()
2878 if (bnx2x_eee_nvram_to_time(params->eee_mode & in bnx2x_eee_calc_timer()
2884 /* hsi values in nvram --> time*/ in bnx2x_eee_calc_timer()
2885 eee_mode = ((REG_RD(bp, params->shmem_base + in bnx2x_eee_calc_timer()
2887 port_feature_config[params->port]. in bnx2x_eee_calc_timer()
2903 struct bnx2x *bp = params->bp; in bnx2x_eee_set_timers()
2908 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2910 } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) && in bnx2x_eee_set_timers()
2911 (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) && in bnx2x_eee_set_timers()
2912 (params->eee_mode & EEE_MODE_OUTPUT_TIME)) { in bnx2x_eee_set_timers()
2914 return -EINVAL; in bnx2x_eee_set_timers()
2917 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); in bnx2x_eee_set_timers()
2918 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) { in bnx2x_eee_set_timers()
2919 /* eee_idle in 1u --> eee_status in 16u */ in bnx2x_eee_set_timers()
2921 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | in bnx2x_eee_set_timers()
2925 return -EINVAL; in bnx2x_eee_set_timers()
2926 vars->eee_status |= eee_mode; in bnx2x_eee_set_timers()
2935 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; in bnx2x_eee_initial_config()
2937 /* Propagate params' bits --> vars (for migration exposure) */ in bnx2x_eee_initial_config()
2938 if (params->eee_mode & EEE_MODE_ENABLE_LPI) in bnx2x_eee_initial_config()
2939 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; in bnx2x_eee_initial_config()
2941 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; in bnx2x_eee_initial_config()
2943 if (params->eee_mode & EEE_MODE_ADV_LPI) in bnx2x_eee_initial_config()
2944 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; in bnx2x_eee_initial_config()
2946 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; in bnx2x_eee_initial_config()
2955 struct bnx2x *bp = params->bp; in bnx2x_eee_disable()
2958 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2962 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; in bnx2x_eee_disable()
2971 struct bnx2x *bp = params->bp; in bnx2x_eee_advertise()
2975 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
2978 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n"); in bnx2x_eee_advertise()
2982 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n"); in bnx2x_eee_advertise()
2988 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; in bnx2x_eee_advertise()
2989 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); in bnx2x_eee_advertise()
2996 struct bnx2x *bp = params->bp; in bnx2x_update_mng_eee()
2999 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3001 eee_status[params->port]), eee_status); in bnx2x_update_mng_eee()
3008 struct bnx2x *bp = params->bp; in bnx2x_eee_an_resolve()
3019 if (vars->line_speed == SPEED_100) in bnx2x_eee_an_resolve()
3021 DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n"); in bnx2x_eee_an_resolve()
3027 if (vars->line_speed == SPEED_1000) in bnx2x_eee_an_resolve()
3029 DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n"); in bnx2x_eee_an_resolve()
3035 if (vars->line_speed == SPEED_10000) in bnx2x_eee_an_resolve()
3037 DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n"); in bnx2x_eee_an_resolve()
3041 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; in bnx2x_eee_an_resolve()
3042 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); in bnx2x_eee_an_resolve()
3046 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; in bnx2x_eee_an_resolve()
3059 struct bnx2x *bp = params->bp; in bnx2x_bsc_module_sel()
3060 u8 port = params->port; in bnx2x_bsc_module_sel()
3062 board_cfg = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3070 sfp_ctrl = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3094 return -EINVAL; in bnx2x_bsc_read()
3098 xfer_cnt = 16 - lc_addr; in bnx2x_bsc_read()
3125 rc = -EFAULT; in bnx2x_bsc_read()
3129 if (rc == -EFAULT) in bnx2x_bsc_read()
3148 rc = -EFAULT; in bnx2x_bsc_read()
3152 if (rc == -EFAULT) in bnx2x_bsc_read()
3191 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { in bnx2x_phy_read()
3192 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_read()
3193 return bnx2x_cl45_read(params->bp, in bnx2x_phy_read()
3194 ¶ms->phy[phy_index], devad, in bnx2x_phy_read()
3198 return -EINVAL; in bnx2x_phy_read()
3208 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { in bnx2x_phy_write()
3209 if (params->phy[phy_index].addr == phy_addr) { in bnx2x_phy_write()
3210 return bnx2x_cl45_write(params->bp, in bnx2x_phy_write()
3211 ¶ms->phy[phy_index], devad, in bnx2x_phy_write()
3215 return -EINVAL; in bnx2x_phy_write()
3221 struct bnx2x *bp = params->bp; in bnx2x_get_warpcore_lane()
3226 port = params->port; in bnx2x_get_warpcore_lane()
3252 } else { /* Two port mode - no port swap */ in bnx2x_get_warpcore_lane()
3276 struct bnx2x *bp = params->bp; in bnx2x_set_aer_mmd()
3277 ser_lane = ((params->lane_config & in bnx2x_set_aer_mmd()
3281 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? in bnx2x_set_aer_mmd()
3282 (phy->addr + ser_lane) : 0; in bnx2x_set_aer_mmd()
3286 /* In Dual-lane mode, two lanes are joined together, in bnx2x_set_aer_mmd()
3292 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_aer_mmd()
3295 aer_val = 0x3800 + offset - 1; in bnx2x_set_aer_mmd()
3345 struct bnx2x *bp = params->bp; in bnx2x_xgxs_specific_func()
3349 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3350 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3351 phy->def_md_devad); in bnx2x_xgxs_specific_func()
3358 struct bnx2x *bp = params->bp; in bnx2x_xgxs_deassert()
3362 port = params->port; in bnx2x_xgxs_deassert()
3370 bnx2x_xgxs_specific_func(¶ms->phy[INT_PHY], params, in bnx2x_xgxs_deassert()
3377 struct bnx2x *bp = params->bp; in bnx2x_calc_ieee_aneg_adv()
3379 /* Resolve pause mode and advertisement Please refer to Table in bnx2x_calc_ieee_aneg_adv()
3380 * 28B-3 of the 802.3ab-1999 spec in bnx2x_calc_ieee_aneg_adv()
3383 switch (phy->req_flow_ctrl) { in bnx2x_calc_ieee_aneg_adv()
3385 switch (params->req_fc_auto_adv) { in bnx2x_calc_ieee_aneg_adv()
3418 struct bnx2x *bp = params->bp; in set_phy_vars()
3420 u8 phy_config_swapped = params->multi_phy_config & in set_phy_vars()
3422 for (phy_index = INT_PHY; phy_index < params->num_phys; in set_phy_vars()
3432 params->phy[actual_phy_idx].req_flow_ctrl = in set_phy_vars()
3433 params->req_flow_ctrl[link_cfg_idx]; in set_phy_vars()
3435 params->phy[actual_phy_idx].req_line_speed = in set_phy_vars()
3436 params->req_line_speed[link_cfg_idx]; in set_phy_vars()
3438 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()
3439 params->speed_cap_mask[link_cfg_idx]; in set_phy_vars()
3441 params->phy[actual_phy_idx].req_duplex = in set_phy_vars()
3442 params->req_duplex[link_cfg_idx]; in set_phy_vars()
3444 if (params->req_line_speed[link_cfg_idx] == in set_phy_vars()
3446 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; in set_phy_vars()
3450 params->phy[actual_phy_idx].req_flow_ctrl, in set_phy_vars()
3451 params->phy[actual_phy_idx].req_line_speed, in set_phy_vars()
3452 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()
3461 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_set_pause()
3462 /* Read modify write pause advertizing */ in bnx2x_ext_phy_set_pause()
3467 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ in bnx2x_ext_phy_set_pause()
3468 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_ext_phy_set_pause()
3469 if ((vars->ieee_fc & in bnx2x_ext_phy_set_pause()
3474 if ((vars->ieee_fc & in bnx2x_ext_phy_set_pause()
3488 struct bnx2x *bp = params->bp; in bnx2x_pause_resolve()
3490 switch (pause_result) { /* ASYM P ASYM P */ in bnx2x_pause_resolve()
3493 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX; in bnx2x_pause_resolve()
3498 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; in bnx2x_pause_resolve()
3509 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) { in bnx2x_pause_resolve()
3511 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH; in bnx2x_pause_resolve()
3514 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX; in bnx2x_pause_resolve()
3520 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_pause_resolve()
3524 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; in bnx2x_pause_resolve()
3526 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; in bnx2x_pause_resolve()
3537 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_update_adv_fc()
3538 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { in bnx2x_ext_phy_update_adv_fc()
3580 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); in bnx2x_ext_phy_update_adv_fc()
3590 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_ext_phy_resolve_fc()
3591 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_ext_phy_resolve_fc()
3592 /* Update the advertised flow-controled of LD/LP in AN */ in bnx2x_ext_phy_resolve_fc()
3593 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3595 /* But set the flow-control result as the requested one */ in bnx2x_ext_phy_resolve_fc()
3596 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_ext_phy_resolve_fc()
3597 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_ext_phy_resolve_fc()
3598 vars->flow_ctrl = params->req_fc_auto_adv; in bnx2x_ext_phy_resolve_fc()
3599 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { in bnx2x_ext_phy_resolve_fc()
3628 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR2()
3631 /* Step 1 - Program the TX/RX alignment markers */ in bnx2x_warpcore_enable_AN_KR2()
3638 /* Step 2 - Configure the NP registers */ in bnx2x_warpcore_enable_AN_KR2()
3649 DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n"); in bnx2x_warpcore_enable_AN_KR2()
3658 /* Start KR2 work-around timer which handles BCM8073 link-parner */ in bnx2x_warpcore_enable_AN_KR2()
3659 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; in bnx2x_warpcore_enable_AN_KR2()
3660 bnx2x_update_link_attr(params, params->link_attr_sync); in bnx2x_warpcore_enable_AN_KR2()
3667 struct bnx2x *bp = params->bp; in bnx2x_disable_kr2()
3670 /* Step 1 - Program the TX/RX alignment markers */ in bnx2x_disable_kr2()
3687 DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n"); in bnx2x_disable_kr2()
3692 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; in bnx2x_disable_kr2()
3693 bnx2x_update_link_attr(params, params->link_attr_sync); in bnx2x_disable_kr2()
3695 vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT; in bnx2x_disable_kr2()
3701 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_lpi_passthrough()
3714 struct bnx2x *bp = params->bp; in bnx2x_warpcore_restart_AN_KR()
3730 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR()
3736 /* Disable Autoneg: re-enable it after adv is done. */ in bnx2x_warpcore_enable_AN_KR()
3755 if (((vars->line_speed == SPEED_AUTO_NEG) && in bnx2x_warpcore_enable_AN_KR()
3756 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in bnx2x_warpcore_enable_AN_KR()
3757 (vars->line_speed == SPEED_1000)) { in bnx2x_warpcore_enable_AN_KR()
3765 if (((vars->line_speed == SPEED_AUTO_NEG) && in bnx2x_warpcore_enable_AN_KR()
3766 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in bnx2x_warpcore_enable_AN_KR()
3767 (vars->line_speed == SPEED_10000)) { in bnx2x_warpcore_enable_AN_KR()
3786 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_enable_AN_KR()
3808 if (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3810 port_hw_config[params->port].default_cfg)) & in bnx2x_warpcore_enable_AN_KR()
3818 /* Advertise pause */ in bnx2x_warpcore_enable_AN_KR()
3820 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; in bnx2x_warpcore_enable_AN_KR()
3824 /* Over 1G - AN local device user page 1 */ in bnx2x_warpcore_enable_AN_KR()
3828 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_warpcore_enable_AN_KR()
3829 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in bnx2x_warpcore_enable_AN_KR()
3830 (phy->req_line_speed == SPEED_20000)) { in bnx2x_warpcore_enable_AN_KR()
3845 /* Enable Auto-Detect to support 1G over CL37 as well */ in bnx2x_warpcore_enable_AN_KR()
3848 wc_lane_config = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3854 * parallel-detect loop when CL73 and CL37 are enabled. in bnx2x_warpcore_enable_AN_KR()
3881 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_KR()
3949 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_XFI()
3965 /* Disable 100FX Enable and Auto-Detect */ in bnx2x_warpcore_set_10G_XFI()
3977 /* Turn off auto-detect & fiber mode */ in bnx2x_warpcore_set_10G_XFI()
4000 cfg_tap_val = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_set_10G_XFI()
4002 port_hw_config[params->port]. in bnx2x_warpcore_set_10G_XFI()
4085 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_20G_force_KR2()
4193 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_sgmii_speed()
4196 /* Clear XFI clock comp in non-10G single lane mode. */ in bnx2x_warpcore_set_sgmii_speed()
4202 if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_set_sgmii_speed()
4212 switch (phy->req_line_speed) { in bnx2x_warpcore_set_sgmii_speed()
4223 "Speed not supported: 0x%x\n", phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4227 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_warpcore_set_sgmii_speed()
4234 phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4259 /* Re-enable parallel detect */ in bnx2x_warpcore_set_sgmii_speed()
4292 struct bnx2x *bp = params->bp; in bnx2x_warpcore_clear_regs()
4350 return -EINVAL; in bnx2x_get_mod_abs_int_cfg()
4353 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; in bnx2x_get_mod_abs_int_cfg()
4354 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; in bnx2x_get_mod_abs_int_cfg()
4366 struct bnx2x *bp = params->bp; in bnx2x_is_sfp_module_plugged()
4369 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, in bnx2x_is_sfp_module_plugged()
4370 params->shmem_base, params->port, in bnx2x_is_sfp_module_plugged()
4385 struct bnx2x *bp = params->bp; in bnx2x_warpcore_get_sigdet()
4399 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_runtime()
4403 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; in bnx2x_warpcore_config_runtime()
4405 if (!vars->turn_to_run_wc_rt) in bnx2x_warpcore_config_runtime()
4408 if (vars->rx_tx_asic_rst) { in bnx2x_warpcore_config_runtime()
4410 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_runtime()
4412 port_hw_config[params->port].default_cfg)) & in bnx2x_warpcore_config_runtime()
4425 vars->rx_tx_asic_rst = 0; in bnx2x_warpcore_config_runtime()
4435 vars->rx_tx_asic_rst--; in bnx2x_warpcore_config_runtime()
4437 vars->rx_tx_asic_rst); in bnx2x_warpcore_config_runtime()
4445 } /*params->rx_tx_asic_rst*/ in bnx2x_warpcore_config_runtime()
4452 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_sfi()
4454 if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] == in bnx2x_warpcore_config_sfi()
4456 (phy->media_type != ETH_PHY_SFP_1G_FIBER)) { in bnx2x_warpcore_config_sfi()
4469 struct bnx2x *bp = params->bp; in bnx2x_sfp_e3_set_transmitter()
4471 u8 port = params->port; in bnx2x_sfp_e3_set_transmitter()
4473 cfg_pin = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e3_set_transmitter()
4482 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in bnx2x_sfp_e3_set_transmitter()
4490 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_init()
4494 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_init()
4496 port_hw_config[params->port].default_cfg)) & in bnx2x_warpcore_config_init()
4500 vars->line_speed, serdes_net_if); in bnx2x_warpcore_config_init()
4503 vars->phy_flags |= PHY_XGXS_FLAG; in bnx2x_warpcore_config_init()
4505 (phy->req_line_speed && in bnx2x_warpcore_config_init()
4506 ((phy->req_line_speed == SPEED_100) || in bnx2x_warpcore_config_init()
4507 (phy->req_line_speed == SPEED_10)))) { in bnx2x_warpcore_config_init()
4508 vars->phy_flags |= PHY_SGMII_FLAG; in bnx2x_warpcore_config_init()
4516 if (params->loopback_mode != LOOPBACK_EXT) in bnx2x_warpcore_config_init()
4519 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n"); in bnx2x_warpcore_config_init()
4526 if (vars->line_speed == SPEED_10000) { in bnx2x_warpcore_config_init()
4550 if ((params->loopback_mode == LOOPBACK_NONE) || in bnx2x_warpcore_config_init()
4551 (params->loopback_mode == LOOPBACK_EXT)) { in bnx2x_warpcore_config_init()
4563 if (vars->line_speed != SPEED_20000) { in bnx2x_warpcore_config_init()
4574 if (!params->loopback_mode) { in bnx2x_warpcore_config_init()
4577 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n"); in bnx2x_warpcore_config_init()
4597 struct bnx2x *bp = params->bp; in bnx2x_warpcore_link_reset()
4613 /* Update those 1-copy registers */ in bnx2x_warpcore_link_reset()
4616 /* Enable 1G MDIO (1-copy) */ in bnx2x_warpcore_link_reset()
4628 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_warpcore_link_reset()
4637 if (phy->flags & FLAGS_WC_DUAL_MODE) { in bnx2x_warpcore_link_reset()
4652 struct bnx2x *bp = params->bp; in bnx2x_set_warpcore_loopback()
4656 params->loopback_mode, phy->req_line_speed); in bnx2x_set_warpcore_loopback()
4658 if (phy->req_line_speed < SPEED_10000 || in bnx2x_set_warpcore_loopback()
4659 phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_set_warpcore_loopback()
4660 /* 10/100/1000/20G-KR2 */ in bnx2x_set_warpcore_loopback()
4662 /* Update those 1-copy registers */ in bnx2x_set_warpcore_loopback()
4665 /* Enable 1G MDIO (1-copy) */ in bnx2x_set_warpcore_loopback()
4669 /* Set 1G loopback based on lane (1-copy) */ in bnx2x_set_warpcore_loopback()
4674 if (phy->flags & FLAGS_WC_DUAL_MODE) in bnx2x_set_warpcore_loopback()
4680 /* Switch back to 4-copy registers */ in bnx2x_set_warpcore_loopback()
4683 /* 10G / 20G-DXGXS */ in bnx2x_set_warpcore_loopback()
4697 struct bnx2x *bp = params->bp; in bnx2x_sync_link()
4699 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) in bnx2x_sync_link()
4700 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; in bnx2x_sync_link()
4701 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); in bnx2x_sync_link()
4702 if (vars->link_up) { in bnx2x_sync_link()
4705 vars->phy_link_up = 1; in bnx2x_sync_link()
4706 vars->duplex = DUPLEX_FULL; in bnx2x_sync_link()
4707 switch (vars->link_status & in bnx2x_sync_link()
4710 vars->duplex = DUPLEX_HALF; in bnx2x_sync_link()
4713 vars->line_speed = SPEED_10; in bnx2x_sync_link()
4717 vars->duplex = DUPLEX_HALF; in bnx2x_sync_link()
4721 vars->line_speed = SPEED_100; in bnx2x_sync_link()
4725 vars->duplex = DUPLEX_HALF; in bnx2x_sync_link()
4728 vars->line_speed = SPEED_1000; in bnx2x_sync_link()
4732 vars->duplex = DUPLEX_HALF; in bnx2x_sync_link()
4735 vars->line_speed = SPEED_2500; in bnx2x_sync_link()
4739 vars->line_speed = SPEED_10000; in bnx2x_sync_link()
4742 vars->line_speed = SPEED_20000; in bnx2x_sync_link()
4747 vars->flow_ctrl = 0; in bnx2x_sync_link()
4748 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) in bnx2x_sync_link()
4749 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX; in bnx2x_sync_link()
4751 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) in bnx2x_sync_link()
4752 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX; in bnx2x_sync_link()
4754 if (!vars->flow_ctrl) in bnx2x_sync_link()
4755 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_sync_link()
4757 if (vars->line_speed && in bnx2x_sync_link()
4758 ((vars->line_speed == SPEED_10) || in bnx2x_sync_link()
4759 (vars->line_speed == SPEED_100))) { in bnx2x_sync_link()
4760 vars->phy_flags |= PHY_SGMII_FLAG; in bnx2x_sync_link()
4762 vars->phy_flags &= ~PHY_SGMII_FLAG; in bnx2x_sync_link()
4764 if (vars->line_speed && in bnx2x_sync_link()
4766 (vars->line_speed == SPEED_1000)) in bnx2x_sync_link()
4767 vars->phy_flags |= PHY_SGMII_FLAG; in bnx2x_sync_link()
4769 link_10g_plus = (vars->line_speed >= SPEED_10000); in bnx2x_sync_link()
4773 vars->mac_type = MAC_TYPE_XMAC; in bnx2x_sync_link()
4775 vars->mac_type = MAC_TYPE_BMAC; in bnx2x_sync_link()
4778 vars->mac_type = MAC_TYPE_UMAC; in bnx2x_sync_link()
4780 vars->mac_type = MAC_TYPE_EMAC; in bnx2x_sync_link()
4785 vars->phy_link_up = 0; in bnx2x_sync_link()
4787 vars->line_speed = 0; in bnx2x_sync_link()
4788 vars->duplex = DUPLEX_FULL; in bnx2x_sync_link()
4789 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_sync_link()
4792 vars->mac_type = MAC_TYPE_NONE; in bnx2x_sync_link()
4793 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) in bnx2x_sync_link()
4794 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; in bnx2x_sync_link()
4795 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) in bnx2x_sync_link()
4796 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; in bnx2x_sync_link()
4803 struct bnx2x *bp = params->bp; in bnx2x_link_status_update()
4804 u8 port = params->port; in bnx2x_link_status_update()
4809 vars->link_status = REG_RD(bp, params->shmem_base + in bnx2x_link_status_update()
4814 if (params->loopback_mode != LOOPBACK_NONE && in bnx2x_link_status_update()
4815 params->loopback_mode != LOOPBACK_EXT) in bnx2x_link_status_update()
4816 vars->link_status |= LINK_STATUS_LINK_UP; in bnx2x_link_status_update()
4819 vars->eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_link_status_update()
4821 eee_status[params->port])); in bnx2x_link_status_update()
4823 vars->phy_flags = PHY_XGXS_FLAG; in bnx2x_link_status_update()
4826 sync_offset = params->shmem_base + in bnx2x_link_status_update()
4831 params->phy[INT_PHY].media_type = in bnx2x_link_status_update()
4834 params->phy[EXT_PHY1].media_type = in bnx2x_link_status_update()
4837 params->phy[EXT_PHY2].media_type = in bnx2x_link_status_update()
4843 sync_offset = params->shmem_base + in bnx2x_link_status_update()
4847 vars->aeu_int_mask = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4850 if (vars->link_status & LINK_STATUS_PFC_ENABLED) in bnx2x_link_status_update()
4851 params->feature_config_flags |= in bnx2x_link_status_update()
4854 params->feature_config_flags &= in bnx2x_link_status_update()
4858 params->link_attr_sync = SHMEM2_RD(bp, in bnx2x_link_status_update()
4859 link_attr_sync[params->port]); in bnx2x_link_status_update()
4862 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); in bnx2x_link_status_update()
4864 vars->line_speed, vars->duplex, vars->flow_ctrl); in bnx2x_link_status_update()
4870 struct bnx2x *bp = params->bp; in bnx2x_set_master_ln()
4872 ser_lane = ((params->lane_config & in bnx2x_set_master_ln()
4892 struct bnx2x *bp = params->bp; in bnx2x_reset_unicore()
4906 bnx2x_set_serdes_access(bp, params->port); in bnx2x_reset_unicore()
4924 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_reset_unicore()
4926 params->port); in bnx2x_reset_unicore()
4928 return -EINVAL; in bnx2x_reset_unicore()
4935 struct bnx2x *bp = params->bp; in bnx2x_set_swap_lanes()
4941 rx_lane_swap = ((params->lane_config & in bnx2x_set_swap_lanes()
4944 tx_lane_swap = ((params->lane_config & in bnx2x_set_swap_lanes()
4977 struct bnx2x *bp = params->bp; in bnx2x_set_parallel_detection()
4983 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) in bnx2x_set_parallel_detection()
4987 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", in bnx2x_set_parallel_detection()
4988 phy->speed_cap_mask, control2); in bnx2x_set_parallel_detection()
4994 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && in bnx2x_set_parallel_detection()
4995 (phy->speed_cap_mask & in bnx2x_set_parallel_detection()
5032 struct bnx2x *bp = params->bp; in bnx2x_set_autoneg()
5041 if (vars->line_speed == SPEED_AUTO_NEG) in bnx2x_set_autoneg()
5059 if (vars->line_speed == SPEED_AUTO_NEG) in bnx2x_set_autoneg()
5073 if (vars->line_speed == SPEED_AUTO_NEG) { in bnx2x_set_autoneg()
5107 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5110 if (phy->speed_cap_mask & in bnx2x_set_autoneg()
5135 struct bnx2x *bp = params->bp; in bnx2x_program_serdes()
5145 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_program_serdes()
5152 * - needed only if the speed is greater than 1G (2.5G or 10G) in bnx2x_program_serdes()
5163 if (!((vars->line_speed == SPEED_1000) || in bnx2x_program_serdes()
5164 (vars->line_speed == SPEED_100) || in bnx2x_program_serdes()
5165 (vars->line_speed == SPEED_10))) { in bnx2x_program_serdes()
5169 if (vars->line_speed == SPEED_10000) in bnx2x_program_serdes()
5183 struct bnx2x *bp = params->bp; in bnx2x_set_brcm_cl37_advertisement()
5187 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) in bnx2x_set_brcm_cl37_advertisement()
5189 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) in bnx2x_set_brcm_cl37_advertisement()
5204 struct bnx2x *bp = params->bp; in bnx2x_set_ieee_aneg_advertisement()
5225 struct bnx2x *bp = params->bp; in bnx2x_restart_autoneg()
5265 struct bnx2x *bp = params->bp; in bnx2x_initialize_sgmii_process()
5285 if (!(vars->line_speed == SPEED_AUTO_NEG)) { in bnx2x_initialize_sgmii_process()
5297 switch (vars->line_speed) { in bnx2x_initialize_sgmii_process()
5312 vars->line_speed); in bnx2x_initialize_sgmii_process()
5317 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_initialize_sgmii_process()
5336 struct bnx2x *bp = params->bp; in bnx2x_direct_parallel_detect_used()
5338 if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_direct_parallel_detect_used()
5350 params->port); in bnx2x_direct_parallel_detect_used()
5361 params->port); in bnx2x_direct_parallel_detect_used()
5375 struct bnx2x *bp = params->bp; in bnx2x_update_adv_fc()
5419 struct bnx2x *bp = params->bp; in bnx2x_flow_ctrl_resolve()
5420 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_flow_ctrl_resolve()
5423 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) { in bnx2x_flow_ctrl_resolve()
5424 /* Update the advertised flow-controled of LD/LP in AN */ in bnx2x_flow_ctrl_resolve()
5425 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5427 /* But set the flow-control result as the requested one */ in bnx2x_flow_ctrl_resolve()
5428 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_flow_ctrl_resolve()
5429 } else if (phy->req_line_speed != SPEED_AUTO_NEG) in bnx2x_flow_ctrl_resolve()
5430 vars->flow_ctrl = params->req_fc_auto_adv; in bnx2x_flow_ctrl_resolve()
5432 (!(vars->phy_flags & PHY_SGMII_FLAG))) { in bnx2x_flow_ctrl_resolve()
5434 vars->flow_ctrl = params->req_fc_auto_adv; in bnx2x_flow_ctrl_resolve()
5439 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); in bnx2x_flow_ctrl_resolve()
5445 struct bnx2x *bp = params->bp; in bnx2x_check_fallback_to_cl37()
5473 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. " in bnx2x_check_fallback_to_cl37()
5497 * restart cl37 auto-neg in bnx2x_check_fallback_to_cl37()
5516 vars->link_status |= in bnx2x_xgxs_an_resolve()
5520 vars->link_status |= in bnx2x_xgxs_an_resolve()
5530 struct bnx2x *bp = params->bp; in bnx2x_get_link_speed_duplex()
5531 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_get_link_speed_duplex()
5532 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; in bnx2x_get_link_speed_duplex()
5536 vars->phy_link_up = 1; in bnx2x_get_link_speed_duplex()
5537 vars->link_status |= LINK_STATUS_LINK_UP; in bnx2x_get_link_speed_duplex()
5541 vars->line_speed = SPEED_10; in bnx2x_get_link_speed_duplex()
5543 vars->link_status |= LINK_10TFD; in bnx2x_get_link_speed_duplex()
5545 vars->link_status |= LINK_10THD; in bnx2x_get_link_speed_duplex()
5549 vars->line_speed = SPEED_100; in bnx2x_get_link_speed_duplex()
5551 vars->link_status |= LINK_100TXFD; in bnx2x_get_link_speed_duplex()
5553 vars->link_status |= LINK_100TXHD; in bnx2x_get_link_speed_duplex()
5558 vars->line_speed = SPEED_1000; in bnx2x_get_link_speed_duplex()
5560 vars->link_status |= LINK_1000TFD; in bnx2x_get_link_speed_duplex()
5562 vars->link_status |= LINK_1000THD; in bnx2x_get_link_speed_duplex()
5566 vars->line_speed = SPEED_2500; in bnx2x_get_link_speed_duplex()
5568 vars->link_status |= LINK_2500TFD; in bnx2x_get_link_speed_duplex()
5570 vars->link_status |= LINK_2500THD; in bnx2x_get_link_speed_duplex()
5578 return -EINVAL; in bnx2x_get_link_speed_duplex()
5586 vars->line_speed = SPEED_10000; in bnx2x_get_link_speed_duplex()
5587 vars->link_status |= LINK_10GTFD; in bnx2x_get_link_speed_duplex()
5591 vars->line_speed = SPEED_20000; in bnx2x_get_link_speed_duplex()
5592 vars->link_status |= LINK_20GTFD; in bnx2x_get_link_speed_duplex()
5598 return -EINVAL; in bnx2x_get_link_speed_duplex()
5603 vars->phy_link_up = 0; in bnx2x_get_link_speed_duplex()
5605 vars->duplex = DUPLEX_FULL; in bnx2x_get_link_speed_duplex()
5606 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_get_link_speed_duplex()
5607 vars->mac_type = MAC_TYPE_NONE; in bnx2x_get_link_speed_duplex()
5610 vars->phy_link_up, vars->line_speed); in bnx2x_get_link_speed_duplex()
5618 struct bnx2x *bp = params->bp; in bnx2x_link_settings_status()
5637 if (rc == -EINVAL) in bnx2x_link_settings_status()
5642 vars->duplex = duplex; in bnx2x_link_settings_status()
5644 if (phy->req_line_speed == SPEED_AUTO_NEG) in bnx2x_link_settings_status()
5649 if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_link_settings_status()
5658 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { in bnx2x_link_settings_status()
5665 vars->link_status |= in bnx2x_link_settings_status()
5669 vars->link_status |= in bnx2x_link_settings_status()
5676 vars->link_status |= in bnx2x_link_settings_status()
5679 vars->link_status |= in bnx2x_link_settings_status()
5684 vars->duplex, vars->flow_ctrl, vars->link_status); in bnx2x_link_settings_status()
5692 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_status()
5698 if ((params->loopback_mode) && in bnx2x_warpcore_read_status()
5699 (phy->flags & FLAGS_WC_DUAL_MODE)) { in bnx2x_warpcore_read_status()
5705 } else if ((phy->req_line_speed > SPEED_10000) && in bnx2x_warpcore_read_status()
5706 (phy->supported & SUPPORTED_20000baseMLD2_Full)) { in bnx2x_warpcore_read_status()
5712 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", in bnx2x_warpcore_read_status()
5727 if (phy->supported & SUPPORTED_20000baseKR2_Full) { in bnx2x_warpcore_read_status()
5737 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_warpcore_read_status()
5743 vars->link_status |= in bnx2x_warpcore_read_status()
5751 vars->link_status |= in bnx2x_warpcore_read_status()
5755 vars->duplex = duplex; in bnx2x_warpcore_read_status()
5759 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && in bnx2x_warpcore_read_status()
5767 vars->link_status |= in bnx2x_warpcore_read_status()
5771 vars->link_status |= in bnx2x_warpcore_read_status()
5778 vars->link_status |= in bnx2x_warpcore_read_status()
5781 vars->link_status |= in bnx2x_warpcore_read_status()
5805 if ((!link_up) && (phy->media_type == ETH_PHY_KR) && in bnx2x_warpcore_read_status()
5806 (!(phy->flags & FLAGS_WC_DUAL_MODE))) in bnx2x_warpcore_read_status()
5807 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; in bnx2x_warpcore_read_status()
5810 vars->duplex, vars->flow_ctrl, vars->link_status); in bnx2x_warpcore_read_status()
5815 struct bnx2x *bp = params->bp; in bnx2x_set_gmii_tx_driver()
5816 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_set_gmii_tx_driver()
5835 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { in bnx2x_set_gmii_tx_driver()
5855 struct bnx2x *bp = params->bp; in bnx2x_emac_program()
5856 u8 port = params->port; in bnx2x_emac_program()
5865 switch (vars->line_speed) { in bnx2x_emac_program()
5885 vars->line_speed); in bnx2x_emac_program()
5886 return -EINVAL; in bnx2x_emac_program()
5889 if (vars->duplex == DUPLEX_HALF) in bnx2x_emac_program()
5895 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); in bnx2x_emac_program()
5904 struct bnx2x *bp = params->bp; in bnx2x_set_preemphasis()
5907 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { in bnx2x_set_preemphasis()
5911 phy->rx_preemphasis[i]); in bnx2x_set_preemphasis()
5915 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { in bnx2x_set_preemphasis()
5919 phy->tx_preemphasis[i]); in bnx2x_set_preemphasis()
5927 struct bnx2x *bp = params->bp; in bnx2x_xgxs_config_init()
5929 (params->loopback_mode == LOOPBACK_XGXS)); in bnx2x_xgxs_config_init()
5930 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { in bnx2x_xgxs_config_init()
5932 (params->feature_config_flags & in bnx2x_xgxs_config_init()
5937 if (vars->line_speed != SPEED_AUTO_NEG || in bnx2x_xgxs_config_init()
5939 params->loopback_mode == LOOPBACK_EXT)) { in bnx2x_xgxs_config_init()
5954 /* Program duplex & pause advertisement (for aneg) */ in bnx2x_xgxs_config_init()
5956 vars->ieee_fc); in bnx2x_xgxs_config_init()
5977 vars->phy_flags |= PHY_XGXS_FLAG; in bnx2x_prepare_xgxs()
5978 if ((phy->req_line_speed && in bnx2x_prepare_xgxs()
5979 ((phy->req_line_speed == SPEED_100) || in bnx2x_prepare_xgxs()
5980 (phy->req_line_speed == SPEED_10))) || in bnx2x_prepare_xgxs()
5981 (!phy->req_line_speed && in bnx2x_prepare_xgxs()
5982 (phy->speed_cap_mask >= in bnx2x_prepare_xgxs()
5984 (phy->speed_cap_mask < in bnx2x_prepare_xgxs()
5986 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) in bnx2x_prepare_xgxs()
5987 vars->phy_flags |= PHY_SGMII_FLAG; in bnx2x_prepare_xgxs()
5989 vars->phy_flags &= ~PHY_SGMII_FLAG; in bnx2x_prepare_xgxs()
5991 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_prepare_xgxs()
5993 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_prepare_xgxs()
6003 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { in bnx2x_prepare_xgxs()
6018 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) in bnx2x_wait_reset_complete()
6031 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_wait_reset_complete()
6033 params->port); in bnx2x_wait_reset_complete()
6040 u8 port = params->port; in bnx2x_link_int_enable()
6042 struct bnx2x *bp = params->bp; in bnx2x_link_int_enable()
6049 } else if (params->switch_cfg == SWITCH_CFG_10G) { in bnx2x_link_int_enable()
6054 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6064 params->phy[INT_PHY].type != in bnx2x_link_int_enable()
6075 (params->switch_cfg == SWITCH_CFG_10G), in bnx2x_link_int_enable()
6092 * status register. Link down indication is high-active-signal, in bnx2x_rearm_latch_signal()
6099 /* Handle only those with latched-signal=up.*/ in bnx2x_rearm_latch_signal()
6113 /* For all latched-signal=up : Re-Arm Latch signals */ in bnx2x_rearm_latch_signal()
6117 /* For all latched-signal=up,Write original_signal to status */ in bnx2x_rearm_latch_signal()
6123 struct bnx2x *bp = params->bp; in bnx2x_link_int_ack()
6124 u8 port = params->port; in bnx2x_link_int_ack()
6133 if (vars->phy_link_up) { in bnx2x_link_int_ack()
6139 else if (params->switch_cfg == SWITCH_CFG_10G) { in bnx2x_link_int_ack()
6144 ((params->lane_config & in bnx2x_link_int_ack()
6163 (*len)--; in bnx2x_null_format_ver()
6174 return -EINVAL; in bnx2x_format_ver()
6178 *len -= ret; in bnx2x_format_ver()
6189 return -EINVAL; in bnx2x_3_seq_format_ver()
6193 *len -= ret; in bnx2x_3_seq_format_ver()
6206 return -EINVAL; in bnx2x_get_ext_phy_fw_version()
6207 bp = params->bp; in bnx2x_get_ext_phy_fw_version()
6211 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6213 if (params->phy[EXT_PHY1].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6214 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver, in bnx2x_get_ext_phy_fw_version()
6217 ver_p += (len - remain_len); in bnx2x_get_ext_phy_fw_version()
6219 if ((params->num_phys == MAX_PHYS) && in bnx2x_get_ext_phy_fw_version()
6220 (params->phy[EXT_PHY2].ver_addr != 0)) { in bnx2x_get_ext_phy_fw_version()
6221 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6222 if (params->phy[EXT_PHY2].format_fw_ver) { in bnx2x_get_ext_phy_fw_version()
6225 remain_len--; in bnx2x_get_ext_phy_fw_version()
6226 status |= params->phy[EXT_PHY2].format_fw_ver( in bnx2x_get_ext_phy_fw_version()
6230 ver_p = version + (len - remain_len); in bnx2x_get_ext_phy_fw_version()
6240 u8 port = params->port; in bnx2x_set_xgxs_loopback()
6241 struct bnx2x *bp = params->bp; in bnx2x_set_xgxs_loopback()
6243 if (phy->req_line_speed != SPEED_1000) { in bnx2x_set_xgxs_loopback()
6295 u8 port = params->port; in bnx2x_set_led()
6296 u16 hw_led_mode = params->hw_led_mode; in bnx2x_set_led()
6301 struct bnx2x *bp = params->bp; in bnx2x_set_led()
6307 if (params->phy[phy_idx].set_link_led) { in bnx2x_set_led()
6308 params->phy[phy_idx].set_link_led( in bnx2x_set_led()
6309 ¶ms->phy[phy_idx], params, mode); in bnx2x_set_led()
6321 if (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6336 if (!vars->link_up) in bnx2x_set_led()
6340 if (((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6342 (params->phy[EXT_PHY1].type == in bnx2x_set_led()
6344 CHIP_IS_E2(bp) && params->num_phys == 2) { in bnx2x_set_led()
6345 /* This is a work-around for E2+8727 Configurations */ in bnx2x_set_led()
6363 /* This is a work-around for HW issue found when link in bnx2x_set_led()
6378 } else if ((params->phy[EXT_PHY1].type == in bnx2x_set_led()
6390 u32 nig_led_mode = ((params->hw_led_mode << in bnx2x_set_led()
6429 rc = -EINVAL; in bnx2x_set_led()
6444 struct bnx2x *bp = params->bp; in bnx2x_test_link()
6448 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_test_link()
6452 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] in bnx2x_test_link()
6471 return -ESRCH; in bnx2x_test_link()
6479 return -ESRCH; in bnx2x_test_link()
6482 if (params->loopback_mode == LOOPBACK_XGXS) in bnx2x_test_link()
6485 switch (params->num_phys) { in bnx2x_test_link()
6490 ext_phy_link_up = params->phy[EXT_PHY1].read_status( in bnx2x_test_link()
6491 ¶ms->phy[EXT_PHY1], in bnx2x_test_link()
6495 for (phy_index = EXT_PHY1; phy_index < params->num_phys; in bnx2x_test_link()
6497 serdes_phy_type = ((params->phy[phy_index].media_type == in bnx2x_test_link()
6499 (params->phy[phy_index].media_type == in bnx2x_test_link()
6501 (params->phy[phy_index].media_type == in bnx2x_test_link()
6503 (params->phy[phy_index].media_type == in bnx2x_test_link()
6508 if (params->phy[phy_index].read_status) { in bnx2x_test_link()
6510 params->phy[phy_index].read_status( in bnx2x_test_link()
6511 ¶ms->phy[phy_index], in bnx2x_test_link()
6519 return -ESRCH; in bnx2x_test_link()
6526 struct bnx2x *bp = params->bp; in bnx2x_link_initialize()
6532 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6539 bnx2x_prepare_xgxs(¶ms->phy[INT_PHY], params, vars); in bnx2x_link_initialize()
6542 (params->loopback_mode == LOOPBACK_XGXS)); in bnx2x_link_initialize()
6545 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) || in bnx2x_link_initialize()
6546 (params->loopback_mode == LOOPBACK_EXT_PHY)) { in bnx2x_link_initialize()
6547 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_link_initialize()
6548 if (vars->line_speed == SPEED_AUTO_NEG && in bnx2x_link_initialize()
6552 if (params->phy[INT_PHY].config_init) in bnx2x_link_initialize()
6553 params->phy[INT_PHY].config_init(phy, params, vars); in bnx2x_link_initialize()
6556 /* Re-read this value in case it was changed inside config_init due to in bnx2x_link_initialize()
6559 vars->line_speed = params->phy[INT_PHY].req_line_speed; in bnx2x_link_initialize()
6563 if (params->phy[INT_PHY].supported & in bnx2x_link_initialize()
6565 vars->link_status |= LINK_STATUS_SERDES_LINK; in bnx2x_link_initialize()
6567 for (phy_index = EXT_PHY1; phy_index < params->num_phys; in bnx2x_link_initialize()
6574 if (params->phy[phy_index].supported & in bnx2x_link_initialize()
6576 vars->link_status |= LINK_STATUS_SERDES_LINK; in bnx2x_link_initialize()
6585 params->phy[phy_index].config_init( in bnx2x_link_initialize()
6586 ¶ms->phy[phy_index], in bnx2x_link_initialize()
6592 params->port*4, in bnx2x_link_initialize()
6604 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6605 (0x1ff << (params->port*16))); in bnx2x_int_link_reset()
6611 struct bnx2x *bp = params->bp; in bnx2x_common_ext_link_reset()
6617 gpio_port = params->port; in bnx2x_common_ext_link_reset()
6630 struct bnx2x *bp = params->bp; in bnx2x_update_link_down()
6631 u8 port = params->port; in bnx2x_update_link_down()
6635 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; in bnx2x_update_link_down()
6637 vars->mac_type = MAC_TYPE_NONE; in bnx2x_update_link_down()
6640 vars->link_status &= ~LINK_UPDATE_MASK; in bnx2x_update_link_down()
6641 vars->line_speed = 0; in bnx2x_update_link_down()
6642 bnx2x_update_mng(params, vars->link_status); in bnx2x_update_link_down()
6655 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_update_link_down()
6659 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6661 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6663 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | in bnx2x_update_link_down()
6666 bnx2x_update_mng_eee(params, vars->eee_status); in bnx2x_update_link_down()
6678 struct bnx2x *bp = params->bp; in bnx2x_update_link_up()
6679 u8 phy_idx, port = params->port; in bnx2x_update_link_up()
6682 vars->link_status |= (LINK_STATUS_LINK_UP | in bnx2x_update_link_up()
6684 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; in bnx2x_update_link_up()
6686 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_update_link_up()
6687 vars->link_status |= in bnx2x_update_link_up()
6690 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) in bnx2x_update_link_up()
6691 vars->link_status |= in bnx2x_update_link_up()
6696 -ESRCH) { in bnx2x_update_link_up()
6698 vars->link_up = 0; in bnx2x_update_link_up()
6699 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; in bnx2x_update_link_up()
6700 vars->link_status &= ~LINK_STATUS_LINK_UP; in bnx2x_update_link_up()
6705 LED_MODE_OPER, vars->line_speed); in bnx2x_update_link_up()
6707 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && in bnx2x_update_link_up()
6708 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { in bnx2x_update_link_up()
6711 (params->port << 2), 1); in bnx2x_update_link_up()
6714 (params->port << 2), 0xfc20); in bnx2x_update_link_up()
6721 -ESRCH) { in bnx2x_update_link_up()
6723 vars->link_up = 0; in bnx2x_update_link_up()
6724 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; in bnx2x_update_link_up()
6725 vars->link_status &= ~LINK_STATUS_LINK_UP; in bnx2x_update_link_up()
6735 if ((vars->link_status & in bnx2x_update_link_up()
6737 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && in bnx2x_update_link_up()
6743 /* PBF - link up */ in bnx2x_update_link_up()
6745 rc |= bnx2x_pbf_update(params, vars->flow_ctrl, in bnx2x_update_link_up()
6746 vars->line_speed); in bnx2x_update_link_up()
6752 bnx2x_update_mng(params, vars->link_status); in bnx2x_update_link_up()
6753 bnx2x_update_mng_eee(params, vars->eee_status); in bnx2x_update_link_up()
6756 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_update_link_up()
6767 struct bnx2x *bp = params->bp; in bnx2x_chng_link_count()
6774 addr = params->shmem2_base + in bnx2x_chng_link_count()
6775 offsetof(struct shmem2_region, link_change_count[params->port]); in bnx2x_chng_link_count()
6786 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6788 * - SINGLE_MEDIA - The link between the 577xx and the external
6791 * - DUAL_MEDIA - The link between the 577xx and the first
6797 struct bnx2x *bp = params->bp; in bnx2x_link_update()
6799 u8 port = params->port; in bnx2x_link_update()
6801 u32 prev_link_status = vars->link_status; in bnx2x_link_update()
6805 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; in bnx2x_link_update()
6807 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; in bnx2x_link_update()
6808 vars->link_status &= ~LINK_UPDATE_MASK; in bnx2x_link_update()
6809 for (phy_index = INT_PHY; phy_index < params->num_phys; in bnx2x_link_update()
6819 phy_vars[phy_index].eee_status = vars->eee_status; in bnx2x_link_update()
6823 bnx2x_set_aer_mmd(params, ¶ms->phy[INT_PHY]); in bnx2x_link_update()
6826 port, (vars->phy_flags & PHY_XGXS_FLAG), in bnx2x_link_update()
6851 for (phy_index = EXT_PHY1; phy_index < params->num_phys; in bnx2x_link_update()
6853 struct bnx2x_phy *phy = ¶ms->phy[phy_index]; in bnx2x_link_update()
6854 if (!phy->read_status) in bnx2x_link_update()
6857 cur_link_up = phy->read_status(phy, params, in bnx2x_link_update()
6890 * - FIRST_PHY means that second phy wasn't initialized, in bnx2x_link_update()
6892 * - SECOND_PHY means that first phy should not be able in bnx2x_link_update()
6894 * - DEFAULT should be overridden during initialization in bnx2x_link_update()
6898 params->multi_phy_config); in bnx2x_link_update()
6904 prev_line_speed = vars->line_speed; in bnx2x_link_update()
6911 if (params->phy[INT_PHY].read_status) in bnx2x_link_update()
6912 params->phy[INT_PHY].read_status( in bnx2x_link_update()
6913 ¶ms->phy[INT_PHY], in bnx2x_link_update()
6923 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; in bnx2x_link_update()
6927 vars->link_status |= phy_vars[active_external_phy].link_status; in bnx2x_link_update()
6929 /* if active_external_phy is first PHY and link is up - disable in bnx2x_link_update()
6933 if (params->phy[EXT_PHY2].phy_specific_func) { in bnx2x_link_update()
6936 params->phy[EXT_PHY2].phy_specific_func( in bnx2x_link_update()
6937 ¶ms->phy[EXT_PHY2], in bnx2x_link_update()
6943 vars->duplex = phy_vars[active_external_phy].duplex; in bnx2x_link_update()
6944 if (params->phy[active_external_phy].supported & in bnx2x_link_update()
6946 vars->link_status |= LINK_STATUS_SERDES_LINK; in bnx2x_link_update()
6948 vars->link_status &= ~LINK_STATUS_SERDES_LINK; in bnx2x_link_update()
6950 vars->eee_status = phy_vars[active_external_phy].eee_status; in bnx2x_link_update()
6956 for (phy_index = EXT_PHY1; phy_index < params->num_phys; in bnx2x_link_update()
6958 if (params->phy[phy_index].flags & in bnx2x_link_update()
6966 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," in bnx2x_link_update()
6967 " ext_phy_line_speed = %d\n", vars->flow_ctrl, in bnx2x_link_update()
6968 vars->link_status, ext_phy_line_speed); in bnx2x_link_update()
6974 if (vars->phy_link_up) { in bnx2x_link_update()
6976 (ext_phy_line_speed != vars->line_speed)) { in bnx2x_link_update()
6979 " link speed %d\n", vars->line_speed, in bnx2x_link_update()
6981 vars->phy_link_up = 0; in bnx2x_link_update()
6982 } else if (prev_line_speed != vars->line_speed) { in bnx2x_link_update()
6983 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
6990 link_10g_plus = (vars->line_speed >= SPEED_10000); in bnx2x_link_update()
6997 * Note that after link down-up as result of cable plug, the xgxs in bnx2x_link_update()
7004 vars->phy_link_up, in bnx2x_link_update()
7005 params->phy[EXT_PHY1].flags & in bnx2x_link_update()
7007 if (!(params->phy[EXT_PHY1].flags & in bnx2x_link_update()
7009 && ext_phy_link_up && !vars->phy_link_up) { in bnx2x_link_update()
7010 vars->line_speed = ext_phy_line_speed; in bnx2x_link_update()
7011 if (vars->line_speed < SPEED_1000) in bnx2x_link_update()
7012 vars->phy_flags |= PHY_SGMII_FLAG; in bnx2x_link_update()
7014 vars->phy_flags &= ~PHY_SGMII_FLAG; in bnx2x_link_update()
7016 if (params->phy[INT_PHY].config_init) in bnx2x_link_update()
7017 params->phy[INT_PHY].config_init( in bnx2x_link_update()
7018 ¶ms->phy[INT_PHY], params, in bnx2x_link_update()
7023 * non-direct board) are up and no fault detected on active PHY. in bnx2x_link_update()
7025 vars->link_up = (vars->phy_link_up && in bnx2x_link_update()
7031 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) in bnx2x_link_update()
7032 vars->link_status |= LINK_STATUS_PFC_ENABLED; in bnx2x_link_update()
7034 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; in bnx2x_link_update()
7036 if (vars->link_up) in bnx2x_link_update()
7041 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) in bnx2x_link_update()
7045 if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX) in bnx2x_link_update()
7084 phy->ver_addr); in bnx2x_save_bcm_spirom_ver()
7099 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; in bnx2x_ext_phy_10G_an_resolve()
7101 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; in bnx2x_ext_phy_10G_an_resolve()
7111 struct bnx2x *bp = params->bp; in bnx2x_8073_resolve_fc()
7112 if (phy->req_line_speed == SPEED_10 || in bnx2x_8073_resolve_fc()
7113 phy->req_line_speed == SPEED_100) { in bnx2x_8073_resolve_fc()
7114 vars->flow_ctrl = phy->req_flow_ctrl; in bnx2x_8073_resolve_fc()
7119 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) { in bnx2x_8073_resolve_fc()
7136 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", in bnx2x_8073_resolve_fc()
7188 rc = -EINVAL; in bnx2x_8073_8727_external_rom_boot()
7201 ((fw_msgout & 0xff) != 0x03 && (phy->type == in bnx2x_8073_8727_external_rom_boot()
7271 * system initialization (XAUI work-around not required, as in bnx2x_8073_xaui_wa()
7275 DP(NETIF_MSG_LINK, "XAUI work-around not required\n"); in bnx2x_8073_xaui_wa()
7299 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n"); in bnx2x_8073_xaui_wa()
7300 return -EINVAL; in bnx2x_8073_xaui_wa()
7321 struct bnx2x *bp = params->bp; in bnx2x_8073_set_pause_cl37()
7326 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ in bnx2x_8073_set_pause_cl37()
7327 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_8073_set_pause_cl37()
7328 if ((vars->ieee_fc & in bnx2x_8073_set_pause_cl37()
7333 if ((vars->ieee_fc & in bnx2x_8073_set_pause_cl37()
7338 if ((vars->ieee_fc & in bnx2x_8073_set_pause_cl37()
7355 struct bnx2x *bp = params->bp; in bnx2x_8073_specific_func()
7371 struct bnx2x *bp = params->bp; in bnx2x_8073_config_init()
7379 gpio_port = params->port; in bnx2x_8073_config_init()
7398 /* Swap polarity if required - Must be done only in non-1G mode */ in bnx2x_8073_config_init()
7399 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { in bnx2x_8073_config_init()
7414 if (REG_RD(bp, params->shmem_base + in bnx2x_8073_config_init()
7416 port_hw_config[params->port].default_cfg)) & in bnx2x_8073_config_init()
7427 if (params->loopback_mode == LOOPBACK_EXT) { in bnx2x_8073_config_init()
7435 if (phy->req_line_speed != SPEED_AUTO_NEG) { in bnx2x_8073_config_init()
7436 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8073_config_init()
7438 } else if (phy->req_line_speed == SPEED_2500) { in bnx2x_8073_config_init()
7447 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7452 if (phy->speed_cap_mask & in bnx2x_8073_config_init()
7462 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && in bnx2x_8073_config_init()
7463 (phy->req_line_speed == SPEED_AUTO_NEG)) || in bnx2x_8073_config_init()
7464 (phy->req_line_speed == SPEED_2500)) { in bnx2x_8073_config_init()
7485 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? in bnx2x_8073_config_init()
7519 struct bnx2x *bp = params->bp; in bnx2x_8073_read_status()
7535 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); in bnx2x_8073_read_status()
7536 /* Clear MSG-OUT */ in bnx2x_8073_read_status()
7559 ((phy->req_line_speed != SPEED_10000))) { in bnx2x_8073_read_status()
7573 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," in bnx2x_8073_read_status()
7595 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ in bnx2x_8073_read_status()
7598 vars->line_speed = SPEED_10000; in bnx2x_8073_read_status()
7600 params->port); in bnx2x_8073_read_status()
7603 vars->line_speed = SPEED_2500; in bnx2x_8073_read_status()
7605 params->port); in bnx2x_8073_read_status()
7608 vars->line_speed = SPEED_1000; in bnx2x_8073_read_status()
7610 params->port); in bnx2x_8073_read_status()
7614 params->port); in bnx2x_8073_read_status()
7619 if (params->lane_config & in bnx2x_8073_read_status()
7628 if (vars->line_speed == SPEED_1000) { in bnx2x_8073_read_status()
7642 vars->duplex = DUPLEX_FULL; in bnx2x_8073_read_status()
7645 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { in bnx2x_8073_read_status()
7650 vars->link_status |= in bnx2x_8073_read_status()
7653 vars->link_status |= in bnx2x_8073_read_status()
7663 struct bnx2x *bp = params->bp; in bnx2x_8073_link_reset()
7668 gpio_port = params->port; in bnx2x_8073_link_reset()
7683 struct bnx2x *bp = params->bp; in bnx2x_8705_config_init()
7687 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in bnx2x_8705_config_init()
7689 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8705_config_init()
7702 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); in bnx2x_8705_config_init()
7712 struct bnx2x *bp = params->bp; in bnx2x_8705_read_status()
7733 vars->line_speed = SPEED_10000; in bnx2x_8705_read_status()
7746 struct bnx2x *bp = params->bp; in bnx2x_set_disable_pmd_transmit()
7751 if (params->feature_config_flags & in bnx2x_set_disable_pmd_transmit()
7769 struct bnx2x *bp = params->bp; in bnx2x_get_gpio_port()
7773 gpio_port = params->port; in bnx2x_get_gpio_port()
7784 u8 port = params->port; in bnx2x_sfp_e1e2_set_transmitter()
7785 struct bnx2x *bp = params->bp; in bnx2x_sfp_e1e2_set_transmitter()
7789 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e1e2_set_transmitter()
7825 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; in bnx2x_sfp_e1e2_set_transmitter()
7840 struct bnx2x *bp = params->bp; in bnx2x_sfp_set_transmitter()
7853 struct bnx2x *bp = params->bp; in bnx2x_8726_read_sfp_module_eeprom()
7859 return -EINVAL; in bnx2x_8726_read_sfp_module_eeprom()
7892 return -EINVAL; in bnx2x_8726_read_sfp_module_eeprom()
7912 return -EINVAL; in bnx2x_8726_read_sfp_module_eeprom()
7919 struct bnx2x *bp = params->bp; in bnx2x_warpcore_power_module()
7921 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_power_module()
7923 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & in bnx2x_warpcore_power_module()
7946 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_sfp_module_eeprom()
7951 return -EINVAL; in bnx2x_warpcore_read_sfp_module_eeprom()
7968 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { in bnx2x_warpcore_read_sfp_module_eeprom()
7982 struct bnx2x *bp = params->bp; in bnx2x_8727_read_sfp_module_eeprom()
7988 return -EINVAL; in bnx2x_8727_read_sfp_module_eeprom()
7991 /* Set 2-wire transfer rate of SFP+ module EEPROM in bnx2x_8727_read_sfp_module_eeprom()
8028 /* Wait appropriate time for two-wire command to finish before in bnx2x_8727_read_sfp_module_eeprom()
8049 return -EFAULT; in bnx2x_8727_read_sfp_module_eeprom()
8070 return -EINVAL; in bnx2x_8727_read_sfp_module_eeprom()
8077 struct bnx2x *bp = params->bp; in bnx2x_read_sfp_module_eeprom()
8084 return -EINVAL; in bnx2x_read_sfp_module_eeprom()
8087 switch (phy->type) { in bnx2x_read_sfp_module_eeprom()
8099 return -EOPNOTSUPP; in bnx2x_read_sfp_module_eeprom()
8107 byte_cnt -= xfer_size; in bnx2x_read_sfp_module_eeprom()
8118 struct bnx2x *bp = params->bp; in bnx2x_get_edc_mode()
8122 phy->media_type = ETH_PHY_UNSPECIFIED; in bnx2x_get_edc_mode()
8131 return -EINVAL; in bnx2x_get_edc_mode()
8133 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; in bnx2x_get_edc_mode()
8134 params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] << in bnx2x_get_edc_mode()
8136 bnx2x_update_link_attr(params, params->link_attr_sync); in bnx2x_get_edc_mode()
8141 phy->media_type = ETH_PHY_DA_TWINAX; in bnx2x_get_edc_mode()
8150 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_get_edc_mode()
8166 "Unknown copper-cable-type\n"); in bnx2x_get_edc_mode()
8181 phy->media_type = ETH_PHY_SFP_1G_FIBER; in bnx2x_get_edc_mode()
8182 if (phy->req_line_speed != SPEED_1000) { in bnx2x_get_edc_mode()
8183 u8 gport = params->port; in bnx2x_get_edc_mode()
8184 phy->req_line_speed = SPEED_1000; in bnx2x_get_edc_mode()
8187 (params->port << 1); in bnx2x_get_edc_mode()
8189 netdev_err(bp->dev, in bnx2x_get_edc_mode()
8203 if (params->phy[idx].type == phy->type) { in bnx2x_get_edc_mode()
8208 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_get_edc_mode()
8209 phy->req_line_speed = params->req_line_speed[cfg_idx]; in bnx2x_get_edc_mode()
8215 return -EINVAL; in bnx2x_get_edc_mode()
8217 sync_offset = params->shmem_base + in bnx2x_get_edc_mode()
8219 dev_info.port_hw_config[params->port].media_type); in bnx2x_get_edc_mode()
8221 /* Update media type for non-PMF sync */ in bnx2x_get_edc_mode()
8223 if (&(params->phy[phy_idx]) == phy) { in bnx2x_get_edc_mode()
8226 media_types |= ((phy->media_type & in bnx2x_get_edc_mode()
8243 return -EINVAL; in bnx2x_get_edc_mode()
8259 struct bnx2x *bp = params->bp; in bnx2x_verify_sfp_module()
8264 phy->flags &= ~FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8265 val = REG_RD(bp, params->shmem_base + in bnx2x_verify_sfp_module()
8267 port_feature_config[params->port].config)); in bnx2x_verify_sfp_module()
8274 if (params->feature_config_flags & in bnx2x_verify_sfp_module()
8278 } else if (params->feature_config_flags & in bnx2x_verify_sfp_module()
8280 /* Use first phy request only in case of non-dual media*/ in bnx2x_verify_sfp_module()
8284 return -EINVAL; in bnx2x_verify_sfp_module()
8291 return -EINVAL; in bnx2x_verify_sfp_module()
8294 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); in bnx2x_verify_sfp_module()
8321 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," in bnx2x_verify_sfp_module()
8323 params->port, vendor_name, vendor_pn); in bnx2x_verify_sfp_module()
8326 phy->flags |= FLAGS_SFP_NOT_APPROVED; in bnx2x_verify_sfp_module()
8327 return -EINVAL; in bnx2x_verify_sfp_module()
8336 struct bnx2x *bp = params->bp; in bnx2x_wait_for_sfp_module_initialized()
8338 /* Initialization time after hot-plug may take up to 300ms for in bnx2x_wait_for_sfp_module_initialized()
8343 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in bnx2x_wait_for_sfp_module_initialized()
8372 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 in bnx2x_8727_power_module()
8373 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 in bnx2x_8727_power_module()
8374 * where the 1st bit is the over-current(only input), and 2nd bit is in bnx2x_8727_power_module()
8378 * as input to enable listening of over-current indication in bnx2x_8727_power_module()
8380 if (phy->flags & FLAGS_NOC) in bnx2x_8727_power_module()
8465 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ in bnx2x_8727_set_limiting_mode()
8483 struct bnx2x *bp = params->bp; in bnx2x_8727_specific_func()
8490 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) in bnx2x_8727_specific_func()
8507 if (phy->flags & FLAGS_NOC) in bnx2x_8727_specific_func()
8510 * status which reflect SFP+ module over-current in bnx2x_8727_specific_func()
8512 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_specific_func()
8513 val &= 0xff8f; /* Reset bits 4-6 */ in bnx2x_8727_specific_func()
8528 struct bnx2x *bp = params->bp; in bnx2x_set_e1e2_module_fault_led()
8530 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + in bnx2x_set_e1e2_module_fault_led()
8532 dev_info.port_hw_config[params->port].sfp_ctrl)) & in bnx2x_set_e1e2_module_fault_led()
8543 u16 gpio_pin = fault_led_gpio - in bnx2x_set_e1e2_module_fault_led()
8545 DP(NETIF_MSG_LINK, "Set fault module-detected led " in bnx2x_set_e1e2_module_fault_led()
8561 u8 port = params->port; in bnx2x_set_e3_module_fault_led()
8562 struct bnx2x *bp = params->bp; in bnx2x_set_e3_module_fault_led()
8563 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_set_e3_module_fault_led()
8576 struct bnx2x *bp = params->bp; in bnx2x_set_sfp_module_fault_led()
8590 struct bnx2x *bp = params->bp; in bnx2x_warpcore_hw_reset()
8605 struct bnx2x *bp = params->bp; in bnx2x_power_sfp_module()
8608 switch (phy->type) { in bnx2x_power_sfp_module()
8611 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8626 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_limiting_mode()
8654 /* Restart microcode to re-read the new mode */ in bnx2x_warpcore_set_limiting_mode()
8664 switch (phy->type) { in bnx2x_set_limiting_mode()
8666 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8670 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8681 struct bnx2x *bp = params->bp; in bnx2x_sfp_module_detection()
8685 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_sfp_module_detection()
8687 port_feature_config[params->port].config)); in bnx2x_sfp_module_detection()
8691 params->port); in bnx2x_sfp_module_detection()
8696 return -EINVAL; in bnx2x_sfp_module_detection()
8700 rc = -EINVAL; in bnx2x_sfp_module_detection()
8701 /* Turn on fault module-detected led */ in bnx2x_sfp_module_detection()
8713 /* Turn off fault module-detected led */ in bnx2x_sfp_module_detection()
8735 struct bnx2x *bp = params->bp; in bnx2x_handle_module_detect_int()
8740 phy = ¶ms->phy[INT_PHY]; in bnx2x_handle_module_detect_int()
8744 phy = ¶ms->phy[EXT_PHY1]; in bnx2x_handle_module_detect_int()
8746 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, in bnx2x_handle_module_detect_int()
8747 params->port, &gpio_num, &gpio_port) == in bnx2x_handle_module_detect_int()
8748 -EINVAL) { in bnx2x_handle_module_detect_int()
8781 (params->link_flags & in bnx2x_handle_module_detect_int()
8798 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_handle_module_detect_int()
8834 struct bnx2x *bp = params->bp; in bnx2x_8706_8726_read_status()
8848 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); in bnx2x_8706_8726_read_status()
8867 vars->line_speed = SPEED_1000; in bnx2x_8706_8726_read_status()
8869 vars->line_speed = SPEED_10000; in bnx2x_8706_8726_read_status()
8871 vars->duplex = DUPLEX_FULL; in bnx2x_8706_8726_read_status()
8875 if (vars->line_speed == SPEED_10000) { in bnx2x_8706_8726_read_status()
8881 vars->fault_detected = 1; in bnx2x_8706_8726_read_status()
8896 struct bnx2x *bp = params->bp; in bnx2x_8706_config_init()
8899 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in bnx2x_8706_config_init()
8901 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8706_config_init()
8914 if ((params->feature_config_flags & in bnx2x_8706_config_init()
8920 i*(MDIO_XS_8706_REG_BANK_RX1 - in bnx2x_8706_config_init()
8926 val |= (phy->rx_preemphasis[i] & 0x7); in bnx2x_8706_config_init()
8928 " reg 0x%x <-- val 0x%x\n", reg, val); in bnx2x_8706_config_init()
8933 if (phy->req_line_speed == SPEED_10000) { in bnx2x_8706_config_init()
8953 /* Enable Full-Duplex advertisement on CL37 */ in bnx2x_8706_config_init()
8973 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
8979 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8706_config_init()
8981 dev_info.port_hw_config[params->port].sfp_ctrl)) in bnx2x_8706_config_init()
9009 struct bnx2x *bp = params->bp; in bnx2x_8726_config_loopback()
9017 struct bnx2x *bp = params->bp; in bnx2x_8726_external_rom_boot()
9021 /* Micro controller re-boot */ in bnx2x_8726_external_rom_boot()
9049 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
9056 struct bnx2x *bp = params->bp; in bnx2x_8726_read_status()
9066 vars->line_speed = 0; in bnx2x_8726_read_status()
9077 struct bnx2x *bp = params->bp; in bnx2x_8726_config_init()
9092 if (phy->req_line_speed == SPEED_1000) { in bnx2x_8726_config_init()
9103 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8726_config_init()
9104 (phy->speed_cap_mask & in bnx2x_8726_config_init()
9106 ((phy->speed_cap_mask & in bnx2x_8726_config_init()
9122 /* Enable RX-ALARM control to receive interrupt for 1G speed in bnx2x_8726_config_init()
9137 if ((params->feature_config_flags & in bnx2x_8726_config_init()
9141 phy->tx_preemphasis[0], in bnx2x_8726_config_init()
9142 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9146 phy->tx_preemphasis[0]); in bnx2x_8726_config_init()
9151 phy->tx_preemphasis[1]); in bnx2x_8726_config_init()
9161 struct bnx2x *bp = params->bp; in bnx2x_8726_link_reset()
9162 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port); in bnx2x_8726_link_reset()
9176 struct bnx2x *bp = params->bp; in bnx2x_8727_set_link_led()
9181 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_set_link_led()
9226 struct bnx2x *bp = params->bp; in bnx2x_8727_hw_reset()
9237 struct bnx2x *bp = params->bp; in bnx2x_8727_config_speed()
9240 if ((phy->req_line_speed == SPEED_1000) || in bnx2x_8727_config_speed()
9241 (phy->media_type == ETH_PHY_SFP_1G_FIBER)) { in bnx2x_8727_config_speed()
9250 /* Power down the XAUI until link is up in case of dual-media in bnx2x_8727_config_speed()
9262 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_8727_config_speed()
9263 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9265 ((phy->speed_cap_mask & in bnx2x_8727_config_speed()
9297 struct bnx2x *bp = params->bp; in bnx2x_8727_config_init()
9315 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_config_init()
9335 if ((params->feature_config_flags & in bnx2x_8727_config_init()
9338 phy->tx_preemphasis[0], in bnx2x_8727_config_init()
9339 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9342 phy->tx_preemphasis[0]); in bnx2x_8727_config_init()
9346 phy->tx_preemphasis[1]); in bnx2x_8727_config_init()
9352 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8727_config_init()
9354 dev_info.port_hw_config[params->port].sfp_ctrl)) in bnx2x_8727_config_init()
9380 struct bnx2x *bp = params->bp; in bnx2x_8727_handle_mod_abs()
9382 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_8727_handle_mod_abs()
9384 port_feature_config[params->port]. in bnx2x_8727_handle_mod_abs()
9394 phy->media_type = ETH_PHY_NOT_PRESENT; in bnx2x_8727_handle_mod_abs()
9403 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9428 if (!(phy->flags & FLAGS_NOC)) in bnx2x_8727_handle_mod_abs()
9467 struct bnx2x *bp = params->bp; in bnx2x_8727_read_status()
9468 u8 link_up = 0, oc_port = params->port; in bnx2x_8727_read_status()
9483 vars->line_speed = 0; in bnx2x_8727_read_status()
9494 /* Clear MSG-OUT */ in bnx2x_8727_read_status()
9501 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { in bnx2x_8727_read_status()
9502 /* Check over-current using 8727 GPIO0 input*/ in bnx2x_8727_read_status()
9509 oc_port = BP_PATH(bp) + (params->port << 1); in bnx2x_8727_read_status()
9513 netdev_err(bp->dev, "Error: Power fault on Port %d has " in bnx2x_8727_read_status()
9538 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9552 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_8727_read_status()
9564 /* Bits 0..2 --> speed detected, in bnx2x_8727_read_status()
9565 * Bits 13..15--> link is down in bnx2x_8727_read_status()
9569 vars->line_speed = SPEED_10000; in bnx2x_8727_read_status()
9571 params->port); in bnx2x_8727_read_status()
9574 vars->line_speed = SPEED_1000; in bnx2x_8727_read_status()
9576 params->port); in bnx2x_8727_read_status()
9580 params->port); in bnx2x_8727_read_status()
9584 if (vars->line_speed == SPEED_10000) { in bnx2x_8727_read_status()
9592 vars->fault_detected = 1; in bnx2x_8727_read_status()
9598 vars->duplex = DUPLEX_FULL; in bnx2x_8727_read_status()
9599 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); in bnx2x_8727_read_status()
9603 (phy->req_line_speed == SPEED_1000)) { in bnx2x_8727_read_status()
9607 /* In case of dual-media board and 1G, power up the XAUI side, in bnx2x_8727_read_status()
9624 struct bnx2x *bp = params->bp; in bnx2x_8727_link_reset()
9641 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in bnx2x_is_8483x_8485x()
9642 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) || in bnx2x_is_8483x_8485x()
9643 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)); in bnx2x_is_8483x_8485x()
9662 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) in bnx2x_save_848xx_spirom_version()
9664 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9666 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ in bnx2x_save_848xx_spirom_version()
9682 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9701 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9711 phy->ver_addr); in bnx2x_save_848xx_spirom_version()
9728 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { in bnx2x_848xx_set_led()
9751 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) in bnx2x_848xx_set_led()
9767 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) in bnx2x_848xx_set_led()
9784 struct bnx2x *bp = params->bp; in bnx2x_848xx_specific_func()
9789 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9795 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, in bnx2x_848xx_specific_func()
9807 struct bnx2x *bp = params->bp; in bnx2x_848xx_cmn_config_init()
9831 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9832 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9834 (phy->req_line_speed == SPEED_1000)) { in bnx2x_848xx_cmn_config_init()
9837 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9848 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_848xx_cmn_config_init()
9849 if (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9855 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); in bnx2x_848xx_cmn_config_init()
9858 if (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9864 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); in bnx2x_848xx_cmn_config_init()
9867 if ((phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9869 (phy->supported & SUPPORTED_10baseT_Full)) { in bnx2x_848xx_cmn_config_init()
9872 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); in bnx2x_848xx_cmn_config_init()
9875 if ((phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9877 (phy->supported & SUPPORTED_10baseT_Half)) { in bnx2x_848xx_cmn_config_init()
9880 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); in bnx2x_848xx_cmn_config_init()
9885 if ((phy->req_line_speed == SPEED_100) && in bnx2x_848xx_cmn_config_init()
9886 (phy->supported & in bnx2x_848xx_cmn_config_init()
9890 /* Enabled AUTO-MDIX when autoneg is disabled */ in bnx2x_848xx_cmn_config_init()
9898 if ((phy->req_line_speed == SPEED_10) && in bnx2x_848xx_cmn_config_init()
9899 (phy->supported & in bnx2x_848xx_cmn_config_init()
9902 /* Enabled AUTO-MDIX when autoneg is disabled */ in bnx2x_848xx_cmn_config_init()
9913 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_848xx_cmn_config_init()
9925 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_848xx_cmn_config_init()
9926 (phy->speed_cap_mask & in bnx2x_848xx_cmn_config_init()
9928 (phy->req_line_speed == SPEED_10000)) { in bnx2x_848xx_cmn_config_init()
9953 struct bnx2x *bp = params->bp; in bnx2x_8481_config_init()
9956 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in bnx2x_8481_config_init()
9959 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8481_config_init()
9976 struct bnx2x *bp = params->bp; in bnx2x_84858_cmd_hdlr()
9995 return -EINVAL; in bnx2x_84858_cmd_hdlr()
10030 return -EINVAL; in bnx2x_84858_cmd_hdlr()
10052 struct bnx2x *bp = params->bp; in bnx2x_84833_cmd_hdlr()
10080 return -EINVAL; in bnx2x_84833_cmd_hdlr()
10105 rc = -EINVAL; in bnx2x_84833_cmd_hdlr()
10130 struct bnx2x *bp = params->bp; in bnx2x_848xx_cmd_hdlr()
10132 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) || in bnx2x_848xx_cmd_hdlr()
10133 (REG_RD(bp, params->shmem2_base + in bnx2x_848xx_cmd_hdlr()
10135 link_attr_sync[params->port])) & in bnx2x_848xx_cmd_hdlr()
10152 struct bnx2x *bp = params->bp; in bnx2x_848xx_pair_swap_cfg()
10155 pair_swap = REG_RD(bp, params->shmem_base + in bnx2x_848xx_pair_swap_cfg()
10157 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & in bnx2x_848xx_pair_swap_cfg()
10192 reset_pin[idx] -= PIN_CFG_GPIO0_P0; in bnx2x_84833_get_reset_gpios()
10203 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; in bnx2x_84833_get_reset_gpios()
10216 struct bnx2x *bp = params->bp; in bnx2x_84833_hw_reset_phy()
10218 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + in bnx2x_84833_hw_reset_phy()
10232 shmem_base_path[0] = params->shmem_base; in bnx2x_84833_hw_reset_phy()
10236 params->chip_id); in bnx2x_84833_hw_reset_phy()
10251 struct bnx2x *bp = params->bp; in bnx2x_8483x_disable_eee()
10254 DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n"); in bnx2x_8483x_disable_eee()
10272 struct bnx2x *bp = params->bp; in bnx2x_8483x_enable_eee()
10290 struct bnx2x *bp = params->bp; in bnx2x_848x3_config_init()
10302 port = params->port; in bnx2x_848x3_config_init()
10304 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10324 temp = vars->line_speed; in bnx2x_848x3_config_init()
10325 vars->line_speed = SPEED_10000; in bnx2x_848x3_config_init()
10326 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); in bnx2x_848x3_config_init()
10327 bnx2x_program_serdes(¶ms->phy[INT_PHY], params, vars); in bnx2x_848x3_config_init()
10328 vars->line_speed = temp; in bnx2x_848x3_config_init()
10331 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { in bnx2x_848x3_config_init()
10337 params->link_attr_sync |= LINK_ATTR_84858; in bnx2x_848x3_config_init()
10338 bnx2x_update_link_attr(params, params->link_attr_sync); in bnx2x_848x3_config_init()
10342 /* Set dual-media configuration according to configuration */ in bnx2x_848x3_config_init()
10379 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000) in bnx2x_848x3_config_init()
10385 params->multi_phy_config, val); in bnx2x_848x3_config_init()
10404 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10406 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_config_init()
10407 u32 cms_enable = REG_RD(bp, params->shmem_base + in bnx2x_848x3_config_init()
10409 dev_info.port_hw_config[params->port].default_cfg)) & in bnx2x_848x3_config_init()
10436 if ((phy->req_duplex == DUPLEX_FULL) && in bnx2x_848x3_config_init()
10437 (params->eee_mode & EEE_MODE_ADV_LPI) && in bnx2x_848x3_config_init()
10439 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) in bnx2x_848x3_config_init()
10448 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; in bnx2x_848x3_config_init()
10451 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { in bnx2x_848x3_config_init()
10452 /* Additional settings for jumbo packets in 1000BASE-T mode */ in bnx2x_848x3_config_init()
10491 struct bnx2x *bp = params->bp; in bnx2x_848xx_read_status()
10496 /* Check 10G-BaseT link status */ in bnx2x_848xx_read_status()
10507 vars->line_speed = SPEED_10000; in bnx2x_848xx_read_status()
10508 vars->duplex = DUPLEX_FULL; in bnx2x_848xx_read_status()
10530 vars->line_speed = SPEED_10; in bnx2x_848xx_read_status()
10532 vars->line_speed = SPEED_100; in bnx2x_848xx_read_status()
10534 vars->line_speed = SPEED_1000; in bnx2x_848xx_read_status()
10536 vars->line_speed = 0; in bnx2x_848xx_read_status()
10542 vars->duplex = DUPLEX_FULL; in bnx2x_848xx_read_status()
10544 vars->duplex = DUPLEX_HALF; in bnx2x_848xx_read_status()
10548 vars->line_speed, in bnx2x_848xx_read_status()
10549 (vars->duplex == DUPLEX_FULL)); in bnx2x_848xx_read_status()
10556 vars->link_status |= in bnx2x_848xx_read_status()
10563 vars->link_status |= in bnx2x_848xx_read_status()
10569 vars->line_speed); in bnx2x_848xx_read_status()
10576 vars->link_status |= in bnx2x_848xx_read_status()
10579 vars->link_status |= in bnx2x_848xx_read_status()
10582 vars->link_status |= in bnx2x_848xx_read_status()
10585 vars->link_status |= in bnx2x_848xx_read_status()
10588 vars->link_status |= in bnx2x_848xx_read_status()
10595 vars->link_status |= in bnx2x_848xx_read_status()
10598 vars->link_status |= in bnx2x_848xx_read_status()
10605 vars->link_status |= in bnx2x_848xx_read_status()
10636 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10638 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10645 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10647 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10654 struct bnx2x *bp = params->bp; in bnx2x_848x3_link_reset()
10661 port = params->port; in bnx2x_848x3_link_reset()
10663 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in bnx2x_848x3_link_reset()
10681 struct bnx2x *bp = params->bp; in bnx2x_848xx_set_link_led()
10688 port = params->port; in bnx2x_848xx_set_link_led()
10695 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in bnx2x_848xx_set_link_led()
10726 if (phy->type == in bnx2x_848xx_set_link_led()
10746 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in bnx2x_848xx_set_link_led()
10775 if (phy->type == in bnx2x_848xx_set_link_led()
10781 params->port*4) & in bnx2x_848xx_set_link_led()
10783 params->link_flags |= in bnx2x_848xx_set_link_led()
10789 params->port*4, in bnx2x_848xx_set_link_led()
10797 if (phy->type == in bnx2x_848xx_set_link_led()
10816 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in bnx2x_848xx_set_link_led()
10856 if (phy->type == in bnx2x_848xx_set_link_led()
10862 params->port*4) & in bnx2x_848xx_set_link_led()
10864 params->link_flags |= in bnx2x_848xx_set_link_led()
10870 params->port*4, in bnx2x_848xx_set_link_led()
10874 if (phy->type == in bnx2x_848xx_set_link_led()
10904 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in bnx2x_848xx_set_link_led()
10949 val = ((params->hw_led_mode << in bnx2x_848xx_set_link_led()
10969 if (phy->type == in bnx2x_848xx_set_link_led()
10980 if (phy->type == in bnx2x_848xx_set_link_led()
10983 * and re-enable interrupts. in bnx2x_848xx_set_link_led()
10989 if (params->link_flags & in bnx2x_848xx_set_link_led()
10992 params->link_flags &= in bnx2x_848xx_set_link_led()
11016 struct bnx2x *bp = params->bp; in bnx2x_54618se_specific_func()
11045 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_init()
11056 port = params->port; in bnx2x_54618se_config_init()
11058 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_config_init()
11093 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ in bnx2x_54618se_config_init()
11094 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in bnx2x_54618se_config_init()
11096 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == in bnx2x_54618se_config_init()
11100 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == in bnx2x_54618se_config_init()
11122 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_54618se_config_init()
11123 (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11125 (phy->req_line_speed == SPEED_1000)) { in bnx2x_54618se_config_init()
11128 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
11142 if (phy->req_line_speed == SPEED_AUTO_NEG) { in bnx2x_54618se_config_init()
11143 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11147 DP(NETIF_MSG_LINK, "Advertising 10M-HD\n"); in bnx2x_54618se_config_init()
11149 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11153 DP(NETIF_MSG_LINK, "Advertising 10M-FD\n"); in bnx2x_54618se_config_init()
11155 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11159 DP(NETIF_MSG_LINK, "Advertising 100M-HD\n"); in bnx2x_54618se_config_init()
11161 if (phy->speed_cap_mask & in bnx2x_54618se_config_init()
11165 DP(NETIF_MSG_LINK, "Advertising 100M-FD\n"); in bnx2x_54618se_config_init()
11170 if (phy->req_line_speed == SPEED_100) { in bnx2x_54618se_config_init()
11172 /* Enabled AUTO-MDIX when autoneg is disabled */ in bnx2x_54618se_config_init()
11178 if (phy->req_line_speed == SPEED_10) { in bnx2x_54618se_config_init()
11179 /* Enabled AUTO-MDIX when autoneg is disabled */ in bnx2x_54618se_config_init()
11186 if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) { in bnx2x_54618se_config_init()
11200 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) && in bnx2x_54618se_config_init()
11201 (phy->req_duplex == DUPLEX_FULL) && in bnx2x_54618se_config_init()
11203 !(params->eee_mode & EEE_MODE_ENABLE_LPI))) { in bnx2x_54618se_config_init()
11212 DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n"); in bnx2x_54618se_config_init()
11216 vars->eee_status &= ~SHMEM_EEE_1G_ADV << in bnx2x_54618se_config_init()
11219 if (phy->flags & FLAGS_EEE) { in bnx2x_54618se_config_init()
11220 /* Handle legacy auto-grEEEn */ in bnx2x_54618se_config_init()
11221 if (params->feature_config_flags & in bnx2x_54618se_config_init()
11224 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n"); in bnx2x_54618se_config_init()
11238 if (phy->req_duplex == DUPLEX_FULL) in bnx2x_54618se_config_init()
11251 struct bnx2x *bp = params->bp; in bnx2x_5461x_set_link_led()
11287 struct bnx2x *bp = params->bp; in bnx2x_54618se_link_reset()
11298 port = params->port; in bnx2x_54618se_link_reset()
11299 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_link_reset()
11313 struct bnx2x *bp = params->bp; in bnx2x_54618se_read_status()
11334 vars->line_speed = SPEED_1000; in bnx2x_54618se_read_status()
11335 vars->duplex = DUPLEX_FULL; in bnx2x_54618se_read_status()
11337 vars->line_speed = SPEED_1000; in bnx2x_54618se_read_status()
11338 vars->duplex = DUPLEX_HALF; in bnx2x_54618se_read_status()
11340 vars->line_speed = SPEED_100; in bnx2x_54618se_read_status()
11341 vars->duplex = DUPLEX_FULL; in bnx2x_54618se_read_status()
11343 /* Omitting 100Base-T4 for now */ in bnx2x_54618se_read_status()
11345 vars->line_speed = SPEED_100; in bnx2x_54618se_read_status()
11346 vars->duplex = DUPLEX_HALF; in bnx2x_54618se_read_status()
11348 vars->line_speed = SPEED_10; in bnx2x_54618se_read_status()
11349 vars->duplex = DUPLEX_FULL; in bnx2x_54618se_read_status()
11351 vars->line_speed = SPEED_10; in bnx2x_54618se_read_status()
11352 vars->duplex = DUPLEX_HALF; in bnx2x_54618se_read_status()
11354 vars->line_speed = 0; in bnx2x_54618se_read_status()
11358 vars->line_speed, in bnx2x_54618se_read_status()
11359 (vars->duplex == DUPLEX_FULL)); in bnx2x_54618se_read_status()
11366 vars->link_status |= in bnx2x_54618se_read_status()
11372 vars->link_status |= in bnx2x_54618se_read_status()
11376 vars->line_speed); in bnx2x_54618se_read_status()
11380 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { in bnx2x_54618se_read_status()
11385 vars->link_status |= in bnx2x_54618se_read_status()
11388 vars->link_status |= in bnx2x_54618se_read_status()
11391 vars->link_status |= in bnx2x_54618se_read_status()
11394 vars->link_status |= in bnx2x_54618se_read_status()
11397 vars->link_status |= in bnx2x_54618se_read_status()
11402 vars->link_status |= in bnx2x_54618se_read_status()
11405 vars->link_status |= in bnx2x_54618se_read_status()
11408 if ((phy->flags & FLAGS_EEE) && in bnx2x_54618se_read_status()
11419 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_loopback()
11421 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bnx2x_54618se_config_loopback()
11448 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11450 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame in bnx2x_54618se_config_loopback()
11462 struct bnx2x *bp = params->bp; in bnx2x_7101_config_loopback()
11473 struct bnx2x *bp = params->bp; in bnx2x_7101_config_init()
11478 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in bnx2x_7101_config_init()
11480 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_7101_config_init()
11503 bnx2x_save_spirom_version(bp, params->port, in bnx2x_7101_config_init()
11504 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); in bnx2x_7101_config_init()
11512 struct bnx2x *bp = params->bp; in bnx2x_7101_read_status()
11519 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", in bnx2x_7101_read_status()
11525 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", in bnx2x_7101_read_status()
11533 vars->line_speed = SPEED_10000; in bnx2x_7101_read_status()
11534 vars->duplex = DUPLEX_FULL; in bnx2x_7101_read_status()
11535 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", in bnx2x_7101_read_status()
11542 vars->link_status |= in bnx2x_7101_read_status()
11551 return -EINVAL; in bnx2x_7101_format_ver()
11557 *len -= 5; in bnx2x_7101_format_ver()
11571 /* Writes a self-clearing reset */ in bnx2x_sfx7101_sp_sw_reset()
11589 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_hw_reset()
11590 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); in bnx2x_7101_hw_reset()
11592 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_7101_hw_reset()
11593 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); in bnx2x_7101_hw_reset()
11600 struct bnx2x *bp = params->bp; in bnx2x_7101_set_link_led()
12183 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); in bnx2x_populate_preemphasis()
12184 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); in bnx2x_populate_preemphasis()
12186 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); in bnx2x_populate_preemphasis()
12187 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); in bnx2x_populate_preemphasis()
12208 return -EINVAL; in bnx2x_get_ext_phy_config()
12232 phy->flags |= FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
12234 phy->flags &= ~FLAGS_4_PORT_MODE; in bnx2x_populate_int_phy()
12245 phy->supported &= (SUPPORTED_10baseT_Half | in bnx2x_populate_int_phy()
12254 phy->media_type = ETH_PHY_BASE_T; in bnx2x_populate_int_phy()
12257 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
12262 phy->media_type = ETH_PHY_XFP_FIBER; in bnx2x_populate_int_phy()
12265 phy->supported &= (SUPPORTED_1000baseT_Full | in bnx2x_populate_int_phy()
12270 phy->media_type = ETH_PHY_SFPP_10G_FIBER; in bnx2x_populate_int_phy()
12273 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12274 phy->supported &= (SUPPORTED_1000baseKX_Full | in bnx2x_populate_int_phy()
12282 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12283 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
12284 phy->supported &= (SUPPORTED_20000baseMLD2_Full | in bnx2x_populate_int_phy()
12290 phy->media_type = ETH_PHY_KR; in bnx2x_populate_int_phy()
12291 phy->flags |= FLAGS_WC_DUAL_MODE; in bnx2x_populate_int_phy()
12292 phy->supported &= (SUPPORTED_20000baseKR2_Full | in bnx2x_populate_int_phy()
12299 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_populate_int_phy()
12307 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC in bnx2x_populate_int_phy()
12312 phy->flags |= FLAGS_MDC_MDIO_WA; in bnx2x_populate_int_phy()
12314 phy->flags |= FLAGS_MDC_MDIO_WA_B0; in bnx2x_populate_int_phy()
12331 return -EINVAL; in bnx2x_populate_int_phy()
12334 phy->addr = (u8)phy_addr; in bnx2x_populate_int_phy()
12335 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
12339 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
12341 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR; in bnx2x_populate_int_phy()
12344 port, phy->addr, phy->mdio_ctrl); in bnx2x_populate_int_phy()
12382 phy->flags |= FLAGS_NOC; in bnx2x_populate_ext_phy()
12408 phy->flags |= FLAGS_EEE; in bnx2x_populate_ext_phy()
12415 return -EINVAL; in bnx2x_populate_ext_phy()
12421 return -EINVAL; in bnx2x_populate_ext_phy()
12425 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); in bnx2x_populate_ext_phy()
12435 phy->ver_addr = shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12447 phy->ver_addr = shmem2_base + in bnx2x_populate_ext_phy()
12455 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - in bnx2x_populate_ext_phy()
12458 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12460 if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) { in bnx2x_populate_ext_phy()
12464 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12467 phy->supported &= ~(SUPPORTED_100baseT_Half | in bnx2x_populate_ext_phy()
12474 phy->addr, phy->mdio_ctrl); in bnx2x_populate_ext_phy()
12481 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; in bnx2x_populate_phy()
12493 struct bnx2x *bp = params->bp; in bnx2x_phy_def_cfg()
12497 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12499 port_feature_config[params->port].link_config2)); in bnx2x_phy_def_cfg()
12500 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12503 port_hw_config[params->port].speed_capability_mask2)); in bnx2x_phy_def_cfg()
12505 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12507 port_feature_config[params->port].link_config)); in bnx2x_phy_def_cfg()
12508 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12511 port_hw_config[params->port].speed_capability_mask)); in bnx2x_phy_def_cfg()
12515 phy_index, link_config, phy->speed_cap_mask); in bnx2x_phy_def_cfg()
12517 phy->req_duplex = DUPLEX_FULL; in bnx2x_phy_def_cfg()
12520 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12523 phy->req_line_speed = SPEED_10; in bnx2x_phy_def_cfg()
12526 phy->req_duplex = DUPLEX_HALF; in bnx2x_phy_def_cfg()
12529 phy->req_line_speed = SPEED_100; in bnx2x_phy_def_cfg()
12532 phy->req_line_speed = SPEED_1000; in bnx2x_phy_def_cfg()
12535 phy->req_line_speed = SPEED_2500; in bnx2x_phy_def_cfg()
12538 phy->req_line_speed = SPEED_10000; in bnx2x_phy_def_cfg()
12541 phy->req_line_speed = SPEED_AUTO_NEG; in bnx2x_phy_def_cfg()
12547 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO; in bnx2x_phy_def_cfg()
12550 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX; in bnx2x_phy_def_cfg()
12553 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX; in bnx2x_phy_def_cfg()
12556 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH; in bnx2x_phy_def_cfg()
12559 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_phy_def_cfg()
12569 phy_config_swapped = params->multi_phy_config & in bnx2x_phy_selection()
12572 prio_cfg = params->multi_phy_config & in bnx2x_phy_selection()
12600 struct bnx2x *bp = params->bp; in bnx2x_phy_probe()
12602 params->num_phys = 0; in bnx2x_phy_probe()
12604 phy_config_swapped = params->multi_phy_config & in bnx2x_phy_probe()
12619 phy = ¶ms->phy[actual_phy_idx]; in bnx2x_phy_probe()
12620 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, in bnx2x_phy_probe()
12621 params->shmem2_base, params->port, in bnx2x_phy_probe()
12623 params->num_phys = 0; in bnx2x_phy_probe()
12630 return -EINVAL; in bnx2x_phy_probe()
12632 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) in bnx2x_phy_probe()
12635 if (params->feature_config_flags & in bnx2x_phy_probe()
12637 phy->flags &= ~FLAGS_TX_ERROR_CHECK; in bnx2x_phy_probe()
12639 if (!(params->feature_config_flags & in bnx2x_phy_probe()
12641 phy->flags |= FLAGS_MDC_MDIO_WA_G; in bnx2x_phy_probe()
12643 sync_offset = params->shmem_base + in bnx2x_phy_probe()
12645 dev_info.port_hw_config[params->port].media_type); in bnx2x_phy_probe()
12648 /* Update media type for non-PMF sync only for the first time in bnx2x_phy_probe()
12655 media_types |= ((phy->media_type & in bnx2x_phy_probe()
12663 params->num_phys++; in bnx2x_phy_probe()
12666 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys); in bnx2x_phy_probe()
12673 struct bnx2x *bp = params->bp; in bnx2x_init_bmac_loopback()
12674 vars->link_up = 1; in bnx2x_init_bmac_loopback()
12675 vars->line_speed = SPEED_10000; in bnx2x_init_bmac_loopback()
12676 vars->duplex = DUPLEX_FULL; in bnx2x_init_bmac_loopback()
12677 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_init_bmac_loopback()
12678 vars->mac_type = MAC_TYPE_BMAC; in bnx2x_init_bmac_loopback()
12680 vars->phy_flags = PHY_XGXS_FLAG; in bnx2x_init_bmac_loopback()
12687 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); in bnx2x_init_bmac_loopback()
12693 struct bnx2x *bp = params->bp; in bnx2x_init_emac_loopback()
12694 vars->link_up = 1; in bnx2x_init_emac_loopback()
12695 vars->line_speed = SPEED_1000; in bnx2x_init_emac_loopback()
12696 vars->duplex = DUPLEX_FULL; in bnx2x_init_emac_loopback()
12697 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_init_emac_loopback()
12698 vars->mac_type = MAC_TYPE_EMAC; in bnx2x_init_emac_loopback()
12700 vars->phy_flags = PHY_XGXS_FLAG; in bnx2x_init_emac_loopback()
12706 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); in bnx2x_init_emac_loopback()
12712 struct bnx2x *bp = params->bp; in bnx2x_init_xmac_loopback()
12713 vars->link_up = 1; in bnx2x_init_xmac_loopback()
12714 if (!params->req_line_speed[0]) in bnx2x_init_xmac_loopback()
12715 vars->line_speed = SPEED_10000; in bnx2x_init_xmac_loopback()
12717 vars->line_speed = params->req_line_speed[0]; in bnx2x_init_xmac_loopback()
12718 vars->duplex = DUPLEX_FULL; in bnx2x_init_xmac_loopback()
12719 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_init_xmac_loopback()
12720 vars->mac_type = MAC_TYPE_XMAC; in bnx2x_init_xmac_loopback()
12721 vars->phy_flags = PHY_XGXS_FLAG; in bnx2x_init_xmac_loopback()
12725 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); in bnx2x_init_xmac_loopback()
12726 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12727 params->phy[INT_PHY].config_loopback( in bnx2x_init_xmac_loopback()
12728 ¶ms->phy[INT_PHY], in bnx2x_init_xmac_loopback()
12732 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12738 struct bnx2x *bp = params->bp; in bnx2x_init_umac_loopback()
12739 vars->link_up = 1; in bnx2x_init_umac_loopback()
12740 vars->line_speed = SPEED_1000; in bnx2x_init_umac_loopback()
12741 vars->duplex = DUPLEX_FULL; in bnx2x_init_umac_loopback()
12742 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_init_umac_loopback()
12743 vars->mac_type = MAC_TYPE_UMAC; in bnx2x_init_umac_loopback()
12744 vars->phy_flags = PHY_XGXS_FLAG; in bnx2x_init_umac_loopback()
12747 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12753 struct bnx2x *bp = params->bp; in bnx2x_init_xgxs_loopback()
12754 struct bnx2x_phy *int_phy = ¶ms->phy[INT_PHY]; in bnx2x_init_xgxs_loopback()
12755 vars->link_up = 1; in bnx2x_init_xgxs_loopback()
12756 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_init_xgxs_loopback()
12757 vars->duplex = DUPLEX_FULL; in bnx2x_init_xgxs_loopback()
12758 if (params->req_line_speed[0] == SPEED_1000) in bnx2x_init_xgxs_loopback()
12759 vars->line_speed = SPEED_1000; in bnx2x_init_xgxs_loopback()
12760 else if ((params->req_line_speed[0] == SPEED_20000) || in bnx2x_init_xgxs_loopback()
12761 (int_phy->flags & FLAGS_WC_DUAL_MODE)) in bnx2x_init_xgxs_loopback()
12762 vars->line_speed = SPEED_20000; in bnx2x_init_xgxs_loopback()
12764 vars->line_speed = SPEED_10000; in bnx2x_init_xgxs_loopback()
12770 if (params->req_line_speed[0] == SPEED_1000) { in bnx2x_init_xgxs_loopback()
12784 if (params->loopback_mode == LOOPBACK_XGXS) { in bnx2x_init_xgxs_loopback()
12786 int_phy->config_loopback(int_phy, params); in bnx2x_init_xgxs_loopback()
12791 phy_index < params->num_phys; phy_index++) in bnx2x_init_xgxs_loopback()
12792 if (params->phy[phy_index].config_loopback) in bnx2x_init_xgxs_loopback()
12793 params->phy[phy_index].config_loopback( in bnx2x_init_xgxs_loopback()
12794 ¶ms->phy[phy_index], in bnx2x_init_xgxs_loopback()
12797 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12799 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed); in bnx2x_init_xgxs_loopback()
12804 struct bnx2x *bp = params->bp; in bnx2x_set_rx_filter()
12810 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12813 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12817 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12825 struct bnx2x *bp = params->bp; in bnx2x_avoid_link_flap()
12836 for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) { in bnx2x_avoid_link_flap()
12837 struct bnx2x_phy *phy = ¶ms->phy[phy_idx]; in bnx2x_avoid_link_flap()
12838 if (phy->phy_specific_func) { in bnx2x_avoid_link_flap()
12840 phy->phy_specific_func(phy, params, PHY_INIT); in bnx2x_avoid_link_flap()
12842 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) || in bnx2x_avoid_link_flap()
12843 (phy->media_type == ETH_PHY_SFP_1G_FIBER) || in bnx2x_avoid_link_flap()
12844 (phy->media_type == ETH_PHY_DA_TWINAX)) in bnx2x_avoid_link_flap()
12847 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12853 /* Re-enable the NIG/MAC */ in bnx2x_avoid_link_flap()
12859 params->port)); in bnx2x_avoid_link_flap()
12863 params->port)); in bnx2x_avoid_link_flap()
12865 if (vars->line_speed < SPEED_10000) in bnx2x_avoid_link_flap()
12870 if (vars->line_speed < SPEED_10000) in bnx2x_avoid_link_flap()
12884 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12888 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12900 struct bnx2x *bp = params->bp; in bnx2x_cannot_avoid_link_flap()
12904 if (!params->lfa_base) in bnx2x_cannot_avoid_link_flap()
12907 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12909 params->req_duplex[0] | (params->req_duplex[1] << 16)); in bnx2x_cannot_avoid_link_flap()
12911 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12913 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); in bnx2x_cannot_avoid_link_flap()
12915 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12917 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); in bnx2x_cannot_avoid_link_flap()
12920 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12923 params->speed_cap_mask[cfg_idx]); in bnx2x_cannot_avoid_link_flap()
12926 tmp_val = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12929 tmp_val |= params->req_fc_auto_adv; in bnx2x_cannot_avoid_link_flap()
12931 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12934 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12950 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12958 struct bnx2x *bp = params->bp; in bnx2x_phy_init()
12961 params->req_line_speed[0], params->req_flow_ctrl[0]); in bnx2x_phy_init()
12963 params->req_line_speed[1], params->req_flow_ctrl[1]); in bnx2x_phy_init()
12964 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); in bnx2x_phy_init()
12965 vars->link_status = 0; in bnx2x_phy_init()
12966 vars->phy_link_up = 0; in bnx2x_phy_init()
12967 vars->link_up = 0; in bnx2x_phy_init()
12968 vars->line_speed = 0; in bnx2x_phy_init()
12969 vars->duplex = DUPLEX_FULL; in bnx2x_phy_init()
12970 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x_phy_init()
12971 vars->mac_type = MAC_TYPE_NONE; in bnx2x_phy_init()
12972 vars->phy_flags = 0; in bnx2x_phy_init()
12973 vars->check_kr2_recovery_cnt = 0; in bnx2x_phy_init()
12974 params->link_flags = PHY_INITIALIZED; in bnx2x_phy_init()
12975 /* Driver opens NIG-BRB filters */ in bnx2x_phy_init()
12991 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_phy_init()
12999 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) in bnx2x_phy_init()
13000 vars->link_status |= LINK_STATUS_PFC_ENABLED; in bnx2x_phy_init()
13002 if (params->num_phys == 0) { in bnx2x_phy_init()
13004 return -EINVAL; in bnx2x_phy_init()
13008 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys); in bnx2x_phy_init()
13009 switch (params->loopback_mode) { in bnx2x_phy_init()
13028 if (params->switch_cfg == SWITCH_CFG_10G) in bnx2x_phy_init()
13031 bnx2x_serdes_deassert(bp, params->port); in bnx2x_phy_init()
13038 bnx2x_update_mng(params, vars->link_status); in bnx2x_phy_init()
13040 bnx2x_update_mng_eee(params, vars->eee_status); in bnx2x_phy_init()
13047 struct bnx2x *bp = params->bp; in bnx2x_link_reset()
13048 u8 phy_index, port = params->port, clear_latch_ind = 0; in bnx2x_link_reset()
13051 vars->link_status = 0; in bnx2x_link_reset()
13053 bnx2x_update_mng(params, vars->link_status); in bnx2x_link_reset()
13054 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | in bnx2x_link_reset()
13056 bnx2x_update_mng_eee(params, vars->eee_status); in bnx2x_link_reset()
13073 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); in bnx2x_link_reset()
13091 for (phy_index = EXT_PHY1; phy_index < params->num_phys; in bnx2x_link_reset()
13093 if (params->phy[phy_index].link_reset) { in bnx2x_link_reset()
13095 ¶ms->phy[phy_index]); in bnx2x_link_reset()
13096 params->phy[phy_index].link_reset( in bnx2x_link_reset()
13097 ¶ms->phy[phy_index], in bnx2x_link_reset()
13100 if (params->phy[phy_index].flags & in bnx2x_link_reset()
13112 if (params->phy[INT_PHY].link_reset) in bnx2x_link_reset()
13113 params->phy[INT_PHY].link_reset( in bnx2x_link_reset()
13114 ¶ms->phy[INT_PHY], params); in bnx2x_link_reset()
13124 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_link_reset()
13131 vars->link_up = 0; in bnx2x_link_reset()
13132 vars->phy_flags = 0; in bnx2x_link_reset()
13138 struct bnx2x *bp = params->bp; in bnx2x_lfa_reset()
13139 vars->link_up = 0; in bnx2x_lfa_reset()
13140 vars->phy_flags = 0; in bnx2x_lfa_reset()
13141 params->link_flags &= ~PHY_INITIALIZED; in bnx2x_lfa_reset()
13142 if (!params->lfa_base) in bnx2x_lfa_reset()
13148 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
13155 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_lfa_reset()
13164 /* Clean the NIG-BRB using the network filters in a way that will in bnx2x_lfa_reset()
13170 * Re-open the gate between the BMAC and the NIG, after verifying the in bnx2x_lfa_reset()
13176 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); in bnx2x_lfa_reset()
13183 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
13205 /* PART1 - Reset both phys */ in bnx2x_8073_common_init_phy()
13206 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in bnx2x_8073_common_init_phy()
13224 return -EINVAL; in bnx2x_8073_common_init_phy()
13259 /* PART2 - Download firmware to both phys */ in bnx2x_8073_common_init_phy()
13260 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in bnx2x_8073_common_init_phy()
13267 phy_blk[port]->addr); in bnx2x_8073_common_init_phy()
13270 return -EINVAL; in bnx2x_8073_common_init_phy()
13289 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ in bnx2x_8073_common_init_phy()
13290 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in bnx2x_8073_common_init_phy()
13302 /* Read modify write the SPI-ROM version select register */ in bnx2x_8073_common_init_phy()
13324 /* Use port1 because of the static port-swap */ in bnx2x_8726_common_init_phy()
13349 return -EINVAL; in bnx2x_8726_common_init_phy()
13445 /* PART1 - Reset both phys */ in bnx2x_8727_common_init_phy()
13446 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in bnx2x_8727_common_init_phy()
13465 return -EINVAL; in bnx2x_8727_common_init_phy()
13490 /* PART2 - Download firmware to both phys */ in bnx2x_8727_common_init_phy()
13491 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in bnx2x_8727_common_init_phy()
13497 phy_blk[port]->addr); in bnx2x_8727_common_init_phy()
13500 return -EINVAL; in bnx2x_8727_common_init_phy()
13565 rc = -EINVAL; in bnx2x_ext_phy_common_init()
13575 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_ext_phy_common_init()
13625 struct bnx2x *bp = params->bp; in bnx2x_check_over_curr()
13627 u8 port = params->port; in bnx2x_check_over_curr()
13630 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_check_over_curr()
13641 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { in bnx2x_check_over_curr()
13642 netdev_err(bp->dev, "Error: Power fault on Port %d has" in bnx2x_check_over_curr()
13649 params->port); in bnx2x_check_over_curr()
13650 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; in bnx2x_check_over_curr()
13654 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; in bnx2x_check_over_curr()
13662 struct bnx2x *bp = params->bp; in bnx2x_analyze_link_error()
13665 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; in bnx2x_analyze_link_error()
13681 DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up, in bnx2x_analyze_link_error()
13685 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) in bnx2x_analyze_link_error()
13688 /* a. Update shmem->link_status accordingly in bnx2x_analyze_link_error()
13689 * b. Update link_vars->link_up in bnx2x_analyze_link_error()
13692 vars->link_status &= ~LINK_STATUS_LINK_UP; in bnx2x_analyze_link_error()
13693 vars->link_status |= link_flag; in bnx2x_analyze_link_error()
13694 vars->link_up = 0; in bnx2x_analyze_link_error()
13695 vars->phy_flags |= phy_flag; in bnx2x_analyze_link_error()
13698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13704 vars->link_status |= LINK_STATUS_LINK_UP; in bnx2x_analyze_link_error()
13705 vars->link_status &= ~link_flag; in bnx2x_analyze_link_error()
13706 vars->link_up = 1; in bnx2x_analyze_link_error()
13707 vars->phy_flags &= ~phy_flag; in bnx2x_analyze_link_error()
13711 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13718 bnx2x_update_mng(params, vars->link_status); in bnx2x_analyze_link_error()
13721 vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT; in bnx2x_analyze_link_error()
13741 struct bnx2x *bp = params->bp; in bnx2x_check_half_open_conn()
13745 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || in bnx2x_check_half_open_conn()
13746 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) in bnx2x_check_half_open_conn()
13757 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_check_half_open_conn()
13771 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { in bnx2x_check_half_open_conn()
13775 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in bnx2x_check_half_open_conn()
13796 struct bnx2x *bp = params->bp; in bnx2x_sfp_tx_fault_detection()
13798 u8 led_change, port = params->port; in bnx2x_sfp_tx_fault_detection()
13801 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, in bnx2x_sfp_tx_fault_detection()
13819 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { in bnx2x_sfp_tx_fault_detection()
13821 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; in bnx2x_sfp_tx_fault_detection()
13824 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; in bnx2x_sfp_tx_fault_detection()
13828 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) { in bnx2x_sfp_tx_fault_detection()
13829 DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n", in bnx2x_sfp_tx_fault_detection()
13839 struct bnx2x *bp = params->bp; in bnx2x_kr2_recovery()
13849 struct bnx2x *bp = params->bp; in bnx2x_check_kr2_wa()
13858 if (vars->check_kr2_recovery_cnt > 0) { in bnx2x_check_kr2_wa()
13859 vars->check_kr2_recovery_cnt--; in bnx2x_check_kr2_wa()
13865 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { in bnx2x_check_kr2_wa()
13883 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { in bnx2x_check_kr2_wa()
13891 * but only KX is advertised, declare this link partner as non-KR2 in bnx2x_check_kr2_wa()
13898 /* In case KR2 is already disabled, check if we need to re-enable it */ in bnx2x_check_kr2_wa()
13899 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { in bnx2x_check_kr2_wa()
13921 struct bnx2x *bp = params->bp; in bnx2x_period_func()
13923 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { in bnx2x_period_func()
13924 bnx2x_set_aer_mmd(params, ¶ms->phy[phy_idx]); in bnx2x_period_func()
13933 struct bnx2x_phy *phy = ¶ms->phy[INT_PHY]; in bnx2x_period_func()
13935 if (((phy->req_line_speed == SPEED_AUTO_NEG) && in bnx2x_period_func()
13936 (phy->speed_cap_mask & in bnx2x_period_func()
13938 (phy->req_line_speed == SPEED_20000)) in bnx2x_period_func()
13941 if (vars->rx_tx_asic_rst) in bnx2x_period_func()
13944 if ((REG_RD(bp, params->shmem_base + in bnx2x_period_func()
13946 port_hw_config[params->port].default_cfg)) in bnx2x_period_func()
13951 } else if (vars->link_status & in bnx2x_period_func()
13954 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; in bnx2x_period_func()
13955 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; in bnx2x_period_func()
13957 bnx2x_update_mng(params, vars->link_status); in bnx2x_period_func()
13987 struct bnx2x *bp = params->bp; in bnx2x_hw_reset_phy()
13989 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_hw_reset_phy()
13997 if (params->phy[phy_index].hw_reset) { in bnx2x_hw_reset_phy()
13998 params->phy[phy_index].hw_reset( in bnx2x_hw_reset_phy()
13999 ¶ms->phy[phy_index], in bnx2x_hw_reset_phy()
14001 params->phy[phy_index] = phy_null; in bnx2x_hw_reset_phy()
14048 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << in bnx2x_init_mod_abs_int()
14054 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
14057 gpio_num, gpio_port, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
14066 aeu_mask |= vars->aeu_int_mask; in bnx2x_init_mod_abs_int()