250 static void bnx2_init_napi(struct bnx2 *bp);
251 static void bnx2_del_napi(struct bnx2 *bp);
253 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)  in bnx2_tx_avail()  argument
266 	return bp->tx_ring_size - diff;  in bnx2_tx_avail()
270 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)  in bnx2_reg_rd_ind()  argument
275 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_reg_rd_ind()
276 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_rd_ind()
277 	val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);  in bnx2_reg_rd_ind()
278 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_reg_rd_ind()
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_reg_wr_ind()  argument
287 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_reg_wr_ind()
288 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);  in bnx2_reg_wr_ind()
289 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);  in bnx2_reg_wr_ind()
290 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_reg_wr_ind()
294 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)  in bnx2_shmem_wr()  argument
296 	bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);  in bnx2_shmem_wr()
300 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)  in bnx2_shmem_rd()  argument
302 	return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);  in bnx2_shmem_rd()
306 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)  in bnx2_ctx_wr()  argument
311 	spin_lock_irqsave(&bp->indirect_lock, flags);  in bnx2_ctx_wr()
312 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_ctx_wr()
315 		BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);  in bnx2_ctx_wr()
316 		BNX2_WR(bp, BNX2_CTX_CTX_CTRL,  in bnx2_ctx_wr()
319 			val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);  in bnx2_ctx_wr()
325 		BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);  in bnx2_ctx_wr()
326 		BNX2_WR(bp, BNX2_CTX_DATA, val);  in bnx2_ctx_wr()
328 	spin_unlock_irqrestore(&bp->indirect_lock, flags);  in bnx2_ctx_wr()
335 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_drv_ctl()  local
340 		bnx2_reg_wr_ind(bp, io->offset, io->data);  in bnx2_drv_ctl()
343 		io->data = bnx2_reg_rd_ind(bp, io->offset);  in bnx2_drv_ctl()
346 		bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);  in bnx2_drv_ctl()
354 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)  in bnx2_setup_cnic_irq_info()  argument
356 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_setup_cnic_irq_info()
357 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_setup_cnic_irq_info()
360 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_setup_cnic_irq_info()
363 		sb_id = bp->irq_nvecs;  in bnx2_setup_cnic_irq_info()
373 	cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;  in bnx2_setup_cnic_irq_info()
384 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_register_cnic()  local
385 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_register_cnic()
393 	if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))  in bnx2_register_cnic()
396 	bp->cnic_data = data;  in bnx2_register_cnic()
397 	rcu_assign_pointer(bp->cnic_ops, ops);  in bnx2_register_cnic()
402 	bnx2_setup_cnic_irq_info(bp);  in bnx2_register_cnic()
409 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_unregister_cnic()  local
410 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_unregister_cnic()
411 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_unregister_cnic()
413 	mutex_lock(&bp->cnic_lock);  in bnx2_unregister_cnic()
416 	RCU_INIT_POINTER(bp->cnic_ops, NULL);  in bnx2_unregister_cnic()
417 	mutex_unlock(&bp->cnic_lock);  in bnx2_unregister_cnic()
424 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_cnic_probe()  local
425 	struct cnic_eth_dev *cp = &bp->cnic_eth_dev;  in bnx2_cnic_probe()
431 	cp->chip_id = bp->chip_id;  in bnx2_cnic_probe()
432 	cp->pdev = bp->pdev;  in bnx2_cnic_probe()
433 	cp->io_base = bp->regview;  in bnx2_cnic_probe()
442 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
447 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_stop()
448 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_stop()
449 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_stop()
452 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_stop()
454 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_stop()
458 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
463 	mutex_lock(&bp->cnic_lock);  in bnx2_cnic_start()
464 	c_ops = rcu_dereference_protected(bp->cnic_ops,  in bnx2_cnic_start()
465 					  lockdep_is_held(&bp->cnic_lock));  in bnx2_cnic_start()
467 		if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_cnic_start()
468 			struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_cnic_start()
473 		c_ops->cnic_ctl(bp->cnic_data, &info);  in bnx2_cnic_start()
475 	mutex_unlock(&bp->cnic_lock);  in bnx2_cnic_start()
481 bnx2_cnic_stop(struct bnx2 *bp)  in bnx2_cnic_stop()  argument
486 bnx2_cnic_start(struct bnx2 *bp)  in bnx2_cnic_start()  argument
493 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)  in bnx2_read_phy()  argument
498 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
499 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
502 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
503 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
508 	val1 = (bp->phy_addr << 21) | (reg << 16) |  in bnx2_read_phy()
511 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_read_phy()
516 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
520 			val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_read_phy()
536 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_read_phy()
537 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
540 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_read_phy()
541 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_read_phy()
550 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)  in bnx2_write_phy()  argument
555 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
556 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
559 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
560 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
565 	val1 = (bp->phy_addr << 21) | (reg << 16) | val |  in bnx2_write_phy()
568 	BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);  in bnx2_write_phy()
573 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);  in bnx2_write_phy()
585 	if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {  in bnx2_write_phy()
586 		val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
589 		BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);  in bnx2_write_phy()
590 		BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);  in bnx2_write_phy()
599 bnx2_disable_int(struct bnx2 *bp)  in bnx2_disable_int()  argument
604 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_disable_int()
605 		bnapi = &bp->bnx2_napi[i];  in bnx2_disable_int()
606 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_disable_int()
609 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_disable_int()
613 bnx2_enable_int(struct bnx2 *bp)  in bnx2_enable_int()  argument
618 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_enable_int()
619 		bnapi = &bp->bnx2_napi[i];  in bnx2_enable_int()
621 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
626 		BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_enable_int()
630 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_enable_int()
634 bnx2_disable_int_sync(struct bnx2 *bp)  in bnx2_disable_int_sync()  argument
638 	atomic_inc(&bp->intr_sem);  in bnx2_disable_int_sync()
639 	if (!netif_running(bp->dev))  in bnx2_disable_int_sync()
642 	bnx2_disable_int(bp);  in bnx2_disable_int_sync()
643 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_disable_int_sync()
644 		synchronize_irq(bp->irq_tbl[i].vector);  in bnx2_disable_int_sync()
648 bnx2_napi_disable(struct bnx2 *bp)  in bnx2_napi_disable()  argument
652 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_disable()
653 		napi_disable(&bp->bnx2_napi[i].napi);  in bnx2_napi_disable()
657 bnx2_napi_enable(struct bnx2 *bp)  in bnx2_napi_enable()  argument
661 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_napi_enable()
662 		napi_enable(&bp->bnx2_napi[i].napi);  in bnx2_napi_enable()
666 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)  in bnx2_netif_stop()  argument
669 		bnx2_cnic_stop(bp);  in bnx2_netif_stop()
670 	if (netif_running(bp->dev)) {  in bnx2_netif_stop()
671 		bnx2_napi_disable(bp);  in bnx2_netif_stop()
672 		netif_tx_disable(bp->dev);  in bnx2_netif_stop()
674 	bnx2_disable_int_sync(bp);  in bnx2_netif_stop()
675 	netif_carrier_off(bp->dev);	/* prevent tx timeout */  in bnx2_netif_stop()
679 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)  in bnx2_netif_start()  argument
681 	if (atomic_dec_and_test(&bp->intr_sem)) {  in bnx2_netif_start()
682 		if (netif_running(bp->dev)) {  in bnx2_netif_start()
683 			netif_tx_wake_all_queues(bp->dev);  in bnx2_netif_start()
684 			spin_lock_bh(&bp->phy_lock);  in bnx2_netif_start()
685 			if (bp->link_up)  in bnx2_netif_start()
686 				netif_carrier_on(bp->dev);  in bnx2_netif_start()
687 			spin_unlock_bh(&bp->phy_lock);  in bnx2_netif_start()
688 			bnx2_napi_enable(bp);  in bnx2_netif_start()
689 			bnx2_enable_int(bp);  in bnx2_netif_start()
691 				bnx2_cnic_start(bp);  in bnx2_netif_start()
697 bnx2_free_tx_mem(struct bnx2 *bp)  in bnx2_free_tx_mem()  argument
701 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_mem()
702 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_mem()
706 			dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_free_tx_mem()
717 bnx2_free_rx_mem(struct bnx2 *bp)  in bnx2_free_rx_mem()  argument
721 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_mem()
722 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_mem()
726 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_free_rx_mem()
728 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
736 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_free_rx_mem()
738 				dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,  in bnx2_free_rx_mem()
749 bnx2_alloc_tx_mem(struct bnx2 *bp)  in bnx2_alloc_tx_mem()  argument
753 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_alloc_tx_mem()
754 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_tx_mem()
762 			dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,  in bnx2_alloc_tx_mem()
771 bnx2_alloc_rx_mem(struct bnx2 *bp)  in bnx2_alloc_rx_mem()  argument
775 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_alloc_rx_mem()
776 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_rx_mem()
781 			vzalloc(array_size(SW_RXBD_RING_SIZE, bp->rx_max_ring));  in bnx2_alloc_rx_mem()
785 		for (j = 0; j < bp->rx_max_ring; j++) {  in bnx2_alloc_rx_mem()
787 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
796 		if (bp->rx_pg_ring_size) {  in bnx2_alloc_rx_mem()
799 						   bp->rx_max_pg_ring));  in bnx2_alloc_rx_mem()
805 		for (j = 0; j < bp->rx_max_pg_ring; j++) {  in bnx2_alloc_rx_mem()
807 				dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_rx_mem()
822 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_free_stats_blk()  local
824 	if (bp->status_blk) {  in bnx2_free_stats_blk()
825 		dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_free_stats_blk()
826 				  bp->status_blk,  in bnx2_free_stats_blk()
827 				  bp->status_blk_mapping);  in bnx2_free_stats_blk()
828 		bp->status_blk = NULL;  in bnx2_free_stats_blk()
829 		bp->stats_blk = NULL;  in bnx2_free_stats_blk()
838 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_alloc_stats_blk()  local
842 	if (bp->flags & BNX2_FLAG_MSIX_CAP)  in bnx2_alloc_stats_blk()
845 	bp->status_stats_size = status_blk_size +  in bnx2_alloc_stats_blk()
847 	status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,  in bnx2_alloc_stats_blk()
848 					&bp->status_blk_mapping, GFP_KERNEL);  in bnx2_alloc_stats_blk()
852 	bp->status_blk = status_blk;  in bnx2_alloc_stats_blk()
853 	bp->stats_blk = status_blk + status_blk_size;  in bnx2_alloc_stats_blk()
854 	bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;  in bnx2_alloc_stats_blk()
860 bnx2_free_mem(struct bnx2 *bp)  in bnx2_free_mem()  argument
863 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_free_mem()
865 	bnx2_free_tx_mem(bp);  in bnx2_free_mem()
866 	bnx2_free_rx_mem(bp);  in bnx2_free_mem()
868 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_free_mem()
869 		if (bp->ctx_blk[i]) {  in bnx2_free_mem()
870 			dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,  in bnx2_free_mem()
871 					  bp->ctx_blk[i],  in bnx2_free_mem()
872 					  bp->ctx_blk_mapping[i]);  in bnx2_free_mem()
873 			bp->ctx_blk[i] = NULL;  in bnx2_free_mem()
882 bnx2_alloc_mem(struct bnx2 *bp)  in bnx2_alloc_mem()  argument
887 	bnapi = &bp->bnx2_napi[0];  in bnx2_alloc_mem()
888 	bnapi->status_blk.msi = bp->status_blk;  in bnx2_alloc_mem()
893 	if (bp->flags & BNX2_FLAG_MSIX_CAP) {  in bnx2_alloc_mem()
894 		for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_alloc_mem()
897 			bnapi = &bp->bnx2_napi[i];  in bnx2_alloc_mem()
899 			sblk = (bp->status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);  in bnx2_alloc_mem()
909 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_alloc_mem()
910 		bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;  in bnx2_alloc_mem()
911 		if (bp->ctx_pages == 0)  in bnx2_alloc_mem()
912 			bp->ctx_pages = 1;  in bnx2_alloc_mem()
913 		for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_alloc_mem()
914 			bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,  in bnx2_alloc_mem()
916 						&bp->ctx_blk_mapping[i],  in bnx2_alloc_mem()
918 			if (!bp->ctx_blk[i])  in bnx2_alloc_mem()
923 	err = bnx2_alloc_rx_mem(bp);  in bnx2_alloc_mem()
927 	err = bnx2_alloc_tx_mem(bp);  in bnx2_alloc_mem()
934 	bnx2_free_mem(bp);  in bnx2_alloc_mem()
939 bnx2_report_fw_link(struct bnx2 *bp)  in bnx2_report_fw_link()  argument
943 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_report_fw_link()
946 	if (bp->link_up) {  in bnx2_report_fw_link()
949 		switch (bp->line_speed) {  in bnx2_report_fw_link()
951 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
957 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
963 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
969 			if (bp->duplex == DUPLEX_HALF)  in bnx2_report_fw_link()
978 		if (bp->autoneg) {  in bnx2_report_fw_link()
981 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
982 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_report_fw_link()
985 			    bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)  in bnx2_report_fw_link()
994 	bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);  in bnx2_report_fw_link()
998 bnx2_xceiver_str(struct bnx2 *bp)  in bnx2_xceiver_str()  argument
1000 	return (bp->phy_port == PORT_FIBRE) ? "SerDes" :  in bnx2_xceiver_str()
1001 		((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :  in bnx2_xceiver_str()
1006 bnx2_report_link(struct bnx2 *bp)  in bnx2_report_link()  argument
1008 	if (bp->link_up) {  in bnx2_report_link()
1009 		netif_carrier_on(bp->dev);  in bnx2_report_link()
1010 		netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",  in bnx2_report_link()
1011 			    bnx2_xceiver_str(bp),  in bnx2_report_link()
1012 			    bp->line_speed,  in bnx2_report_link()
1013 			    bp->duplex == DUPLEX_FULL ? "full" : "half");  in bnx2_report_link()
1015 		if (bp->flow_ctrl) {  in bnx2_report_link()
1016 			if (bp->flow_ctrl & FLOW_CTRL_RX) {  in bnx2_report_link()
1018 				if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_report_link()
1028 		netif_carrier_off(bp->dev);  in bnx2_report_link()
1029 		netdev_err(bp->dev, "NIC %s Link is Down\n",  in bnx2_report_link()
1030 			   bnx2_xceiver_str(bp));  in bnx2_report_link()
1033 	bnx2_report_fw_link(bp);  in bnx2_report_link()
1037 bnx2_resolve_flow_ctrl(struct bnx2 *bp)  in bnx2_resolve_flow_ctrl()  argument
1041 	bp->flow_ctrl = 0;  in bnx2_resolve_flow_ctrl()
1042 	if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_resolve_flow_ctrl()
1045 		if (bp->duplex == DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1046 			bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_resolve_flow_ctrl()
1051 	if (bp->duplex != DUPLEX_FULL) {  in bnx2_resolve_flow_ctrl()
1055 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_resolve_flow_ctrl()
1056 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_resolve_flow_ctrl()
1059 		bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_resolve_flow_ctrl()
1061 			bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1063 			bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1067 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_resolve_flow_ctrl()
1068 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_resolve_flow_ctrl()
1070 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_resolve_flow_ctrl()
1091 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1094 				bp->flow_ctrl = FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1099 				bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in bnx2_resolve_flow_ctrl()
1107 			bp->flow_ctrl = FLOW_CTRL_TX;  in bnx2_resolve_flow_ctrl()
1113 bnx2_5709s_linkup(struct bnx2 *bp)  in bnx2_5709s_linkup()  argument
1117 	bp->link_up = 1;  in bnx2_5709s_linkup()
1119 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);  in bnx2_5709s_linkup()
1120 	bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);  in bnx2_5709s_linkup()
1121 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_5709s_linkup()
1123 	if ((bp->autoneg & AUTONEG_SPEED) == 0) {  in bnx2_5709s_linkup()
1124 		bp->line_speed = bp->req_line_speed;  in bnx2_5709s_linkup()
1125 		bp->duplex = bp->req_duplex;  in bnx2_5709s_linkup()
1131 			bp->line_speed = SPEED_10;  in bnx2_5709s_linkup()
1134 			bp->line_speed = SPEED_100;  in bnx2_5709s_linkup()
1138 			bp->line_speed = SPEED_1000;  in bnx2_5709s_linkup()
1141 			bp->line_speed = SPEED_2500;  in bnx2_5709s_linkup()
1145 		bp->duplex = DUPLEX_FULL;  in bnx2_5709s_linkup()
1147 		bp->duplex = DUPLEX_HALF;  in bnx2_5709s_linkup()
1152 bnx2_5708s_linkup(struct bnx2 *bp)  in bnx2_5708s_linkup()  argument
1156 	bp->link_up = 1;  in bnx2_5708s_linkup()
1157 	bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);  in bnx2_5708s_linkup()
1160 			bp->line_speed = SPEED_10;  in bnx2_5708s_linkup()
1163 			bp->line_speed = SPEED_100;  in bnx2_5708s_linkup()
1166 			bp->line_speed = SPEED_1000;  in bnx2_5708s_linkup()
1169 			bp->line_speed = SPEED_2500;  in bnx2_5708s_linkup()
1173 		bp->duplex = DUPLEX_FULL;  in bnx2_5708s_linkup()
1175 		bp->duplex = DUPLEX_HALF;  in bnx2_5708s_linkup()
1181 bnx2_5706s_linkup(struct bnx2 *bp)  in bnx2_5706s_linkup()  argument
1185 	bp->link_up = 1;  in bnx2_5706s_linkup()
1186 	bp->line_speed = SPEED_1000;  in bnx2_5706s_linkup()
1188 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706s_linkup()
1190 		bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1193 		bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1200 	bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_5706s_linkup()
1201 	bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_5706s_linkup()
1207 			bp->duplex = DUPLEX_FULL;  in bnx2_5706s_linkup()
1210 			bp->duplex = DUPLEX_HALF;  in bnx2_5706s_linkup()
1218 bnx2_copper_linkup(struct bnx2 *bp)  in bnx2_copper_linkup()  argument
1222 	bp->phy_flags &= ~BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1224 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_copper_linkup()
1228 		bnx2_read_phy(bp, MII_CTRL1000, &local_adv);  in bnx2_copper_linkup()
1229 		bnx2_read_phy(bp, MII_STAT1000, &remote_adv);  in bnx2_copper_linkup()
1233 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1234 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1237 			bp->line_speed = SPEED_1000;  in bnx2_copper_linkup()
1238 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1241 			bnx2_read_phy(bp, bp->mii_adv, &local_adv);  in bnx2_copper_linkup()
1242 			bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);  in bnx2_copper_linkup()
1246 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1247 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1250 				bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1251 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1254 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1255 				bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1258 				bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1259 				bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1262 				bp->line_speed = 0;  in bnx2_copper_linkup()
1263 				bp->link_up = 0;  in bnx2_copper_linkup()
1269 			bp->line_speed = SPEED_100;  in bnx2_copper_linkup()
1272 			bp->line_speed = SPEED_10;  in bnx2_copper_linkup()
1275 			bp->duplex = DUPLEX_FULL;  in bnx2_copper_linkup()
1278 			bp->duplex = DUPLEX_HALF;  in bnx2_copper_linkup()
1282 	if (bp->link_up) {  in bnx2_copper_linkup()
1285 		bnx2_read_phy(bp, MII_BNX2_EXT_STATUS, &ext_status);  in bnx2_copper_linkup()
1287 			bp->phy_flags |= BNX2_PHY_FLAG_MDIX;  in bnx2_copper_linkup()
1294 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)  in bnx2_init_rx_context()  argument
1302 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_init_rx_context()
1305 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);  in bnx2_init_rx_context()
1309 bnx2_init_all_rx_contexts(struct bnx2 *bp)  in bnx2_init_all_rx_contexts()  argument
1314 	for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {  in bnx2_init_all_rx_contexts()
1317 		bnx2_init_rx_context(bp, cid);  in bnx2_init_all_rx_contexts()
1322 bnx2_set_mac_link(struct bnx2 *bp)  in bnx2_set_mac_link()  argument
1326 	BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);  in bnx2_set_mac_link()
1327 	if (bp->link_up && (bp->line_speed == SPEED_1000) &&  in bnx2_set_mac_link()
1328 		(bp->duplex == DUPLEX_HALF)) {  in bnx2_set_mac_link()
1329 		BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);  in bnx2_set_mac_link()
1333 	val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_link()
1339 	if (bp->link_up) {  in bnx2_set_mac_link()
1340 		switch (bp->line_speed) {  in bnx2_set_mac_link()
1342 				if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {  in bnx2_set_mac_link()
1363 	if (bp->duplex == DUPLEX_HALF)  in bnx2_set_mac_link()
1365 	BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_mac_link()
1368 	bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1370 	if (bp->flow_ctrl & FLOW_CTRL_RX)  in bnx2_set_mac_link()
1371 		bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;  in bnx2_set_mac_link()
1372 	BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);  in bnx2_set_mac_link()
1375 	val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);  in bnx2_set_mac_link()
1378 	if (bp->flow_ctrl & FLOW_CTRL_TX)  in bnx2_set_mac_link()
1380 	BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);  in bnx2_set_mac_link()
1383 	BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);  in bnx2_set_mac_link()
1385 	bnx2_init_all_rx_contexts(bp);  in bnx2_set_mac_link()
1389 bnx2_enable_bmsr1(struct bnx2 *bp)  in bnx2_enable_bmsr1()  argument
1391 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_enable_bmsr1()
1392 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_enable_bmsr1()
1393 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_bmsr1()
1398 bnx2_disable_bmsr1(struct bnx2 *bp)  in bnx2_disable_bmsr1()  argument
1400 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_disable_bmsr1()
1401 	    (BNX2_CHIP(bp) == BNX2_CHIP_5709))  in bnx2_disable_bmsr1()
1402 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_bmsr1()
1407 bnx2_test_and_enable_2g5(struct bnx2 *bp)  in bnx2_test_and_enable_2g5()  argument
1412 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_enable_2g5()
1415 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_test_and_enable_2g5()
1416 		bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_test_and_enable_2g5()
1418 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1419 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_enable_2g5()
1421 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_enable_2g5()
1424 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_enable_2g5()
1428 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_enable_2g5()
1429 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_enable_2g5()
1436 bnx2_test_and_disable_2g5(struct bnx2 *bp)  in bnx2_test_and_disable_2g5()  argument
1441 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_test_and_disable_2g5()
1444 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1445 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_test_and_disable_2g5()
1447 	bnx2_read_phy(bp, bp->mii_up1, &up1);  in bnx2_test_and_disable_2g5()
1450 		bnx2_write_phy(bp, bp->mii_up1, up1);  in bnx2_test_and_disable_2g5()
1454 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_and_disable_2g5()
1455 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_test_and_disable_2g5()
1462 bnx2_enable_forced_2g5(struct bnx2 *bp)  in bnx2_enable_forced_2g5()  argument
1467 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_enable_forced_2g5()
1470 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_enable_forced_2g5()
1473 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1475 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_enable_forced_2g5()
1479 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_enable_forced_2g5()
1482 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_enable_forced_2g5()
1484 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1486 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_enable_forced_2g5()
1487 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_enable_forced_2g5()
1497 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_enable_forced_2g5()
1499 		if (bp->req_duplex == DUPLEX_FULL)  in bnx2_enable_forced_2g5()
1502 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_enable_forced_2g5()
1506 bnx2_disable_forced_2g5(struct bnx2 *bp)  in bnx2_disable_forced_2g5()  argument
1511 	if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_disable_forced_2g5()
1514 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_disable_forced_2g5()
1517 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1519 		if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {  in bnx2_disable_forced_2g5()
1521 			bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);  in bnx2_disable_forced_2g5()
1524 		bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,  in bnx2_disable_forced_2g5()
1526 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1528 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_disable_forced_2g5()
1529 		err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_disable_forced_2g5()
1539 	if (bp->autoneg & AUTONEG_SPEED)  in bnx2_disable_forced_2g5()
1541 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_disable_forced_2g5()
1545 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)  in bnx2_5706s_force_link_dn()  argument
1549 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);  in bnx2_5706s_force_link_dn()
1550 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_5706s_force_link_dn()
1552 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);  in bnx2_5706s_force_link_dn()
1554 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);  in bnx2_5706s_force_link_dn()
1558 bnx2_set_link(struct bnx2 *bp)  in bnx2_set_link()  argument
1563 	if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {  in bnx2_set_link()
1564 		bp->link_up = 1;  in bnx2_set_link()
1568 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_set_link()
1571 	link_up = bp->link_up;  in bnx2_set_link()
1573 	bnx2_enable_bmsr1(bp);  in bnx2_set_link()
1574 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1575 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_set_link()
1576 	bnx2_disable_bmsr1(bp);  in bnx2_set_link()
1578 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1579 	    (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {  in bnx2_set_link()
1582 		if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {  in bnx2_set_link()
1583 			bnx2_5706s_force_link_dn(bp, 0);  in bnx2_set_link()
1584 			bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_set_link()
1586 		val = BNX2_RD(bp, BNX2_EMAC_STATUS);  in bnx2_set_link()
1588 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_set_link()
1589 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1590 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_set_link()
1600 		bp->link_up = 1;  in bnx2_set_link()
1602 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_link()
1603 			if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_set_link()
1604 				bnx2_5706s_linkup(bp);  in bnx2_set_link()
1605 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_set_link()
1606 				bnx2_5708s_linkup(bp);  in bnx2_set_link()
1607 			else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_set_link()
1608 				bnx2_5709s_linkup(bp);  in bnx2_set_link()
1611 			bnx2_copper_linkup(bp);  in bnx2_set_link()
1613 		bnx2_resolve_flow_ctrl(bp);  in bnx2_set_link()
1616 		if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_set_link()
1617 		    (bp->autoneg & AUTONEG_SPEED))  in bnx2_set_link()
1618 			bnx2_disable_forced_2g5(bp);  in bnx2_set_link()
1620 		if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {  in bnx2_set_link()
1623 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_set_link()
1625 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_set_link()
1627 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_set_link()
1629 		bp->link_up = 0;  in bnx2_set_link()
1632 	if (bp->link_up != link_up) {  in bnx2_set_link()
1633 		bnx2_report_link(bp);  in bnx2_set_link()
1636 	bnx2_set_mac_link(bp);  in bnx2_set_link()
1642 bnx2_reset_phy(struct bnx2 *bp)  in bnx2_reset_phy()  argument
1647         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);  in bnx2_reset_phy()
1653 		bnx2_read_phy(bp, bp->mii_bmcr, &reg);  in bnx2_reset_phy()
1666 bnx2_phy_get_pause_adv(struct bnx2 *bp)  in bnx2_phy_get_pause_adv()  argument
1670 	if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==  in bnx2_phy_get_pause_adv()
1673 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1680 	else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {  in bnx2_phy_get_pause_adv()
1681 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1688 	else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {  in bnx2_phy_get_pause_adv()
1689 		if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_phy_get_pause_adv()
1702 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_remote_phy()  argument
1703 __releases(&bp->phy_lock)  in bnx2_setup_remote_phy()
1704 __acquires(&bp->phy_lock)  in bnx2_setup_remote_phy()
1708 	pause_adv = bnx2_phy_get_pause_adv(bp);  in bnx2_setup_remote_phy()
1710 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_remote_phy()
1712 		if (bp->advertising & ADVERTISED_10baseT_Half)  in bnx2_setup_remote_phy()
1714 		if (bp->advertising & ADVERTISED_10baseT_Full)  in bnx2_setup_remote_phy()
1716 		if (bp->advertising & ADVERTISED_100baseT_Half)  in bnx2_setup_remote_phy()
1718 		if (bp->advertising & ADVERTISED_100baseT_Full)  in bnx2_setup_remote_phy()
1720 		if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_remote_phy()
1722 		if (bp->advertising & ADVERTISED_2500baseX_Full)  in bnx2_setup_remote_phy()
1725 		if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_remote_phy()
1727 		else if (bp->req_line_speed == SPEED_1000)  in bnx2_setup_remote_phy()
1729 		else if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_remote_phy()
1730 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1734 		} else if (bp->req_line_speed == SPEED_10) {  in bnx2_setup_remote_phy()
1735 			if (bp->req_duplex == DUPLEX_FULL)  in bnx2_setup_remote_phy()
1751 	bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);  in bnx2_setup_remote_phy()
1753 	spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1754 	bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);  in bnx2_setup_remote_phy()
1755 	spin_lock_bh(&bp->phy_lock);  in bnx2_setup_remote_phy()
1761 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_serdes_phy()  argument
1762 __releases(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1763 __acquires(&bp->phy_lock)  in bnx2_setup_serdes_phy()
1768 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_setup_serdes_phy()
1769 		return bnx2_setup_remote_phy(bp, port);  in bnx2_setup_serdes_phy()
1771 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_setup_serdes_phy()
1775 		if (bp->req_line_speed == SPEED_2500) {  in bnx2_setup_serdes_phy()
1776 			if (!bnx2_test_and_enable_2g5(bp))  in bnx2_setup_serdes_phy()
1778 		} else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1779 			if (bnx2_test_and_disable_2g5(bp))  in bnx2_setup_serdes_phy()
1782 		bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1785 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1789 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_serdes_phy()
1790 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1791 				bnx2_enable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1792 			else if (bp->req_line_speed == SPEED_1000) {  in bnx2_setup_serdes_phy()
1793 				bnx2_disable_forced_2g5(bp);  in bnx2_setup_serdes_phy()
1797 		} else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {  in bnx2_setup_serdes_phy()
1798 			if (bp->req_line_speed == SPEED_2500)  in bnx2_setup_serdes_phy()
1804 		if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_serdes_phy()
1814 			if (bp->link_up) {  in bnx2_setup_serdes_phy()
1815 				bnx2_write_phy(bp, bp->mii_adv, adv &  in bnx2_setup_serdes_phy()
1818 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr |  in bnx2_setup_serdes_phy()
1821 				bp->link_up = 0;  in bnx2_setup_serdes_phy()
1822 				netif_carrier_off(bp->dev);  in bnx2_setup_serdes_phy()
1823 				bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1824 				bnx2_report_link(bp);  in bnx2_setup_serdes_phy()
1826 			bnx2_write_phy(bp, bp->mii_adv, adv);  in bnx2_setup_serdes_phy()
1827 			bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_serdes_phy()
1829 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1830 			bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1835 	bnx2_test_and_enable_2g5(bp);  in bnx2_setup_serdes_phy()
1837 	if (bp->advertising & ADVERTISED_1000baseT_Full)  in bnx2_setup_serdes_phy()
1840 	new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_serdes_phy()
1842 	bnx2_read_phy(bp, bp->mii_adv, &adv);  in bnx2_setup_serdes_phy()
1843 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_serdes_phy()
1845 	bp->serdes_an_pending = 0;  in bnx2_setup_serdes_phy()
1848 		if (bp->link_up) {  in bnx2_setup_serdes_phy()
1849 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_serdes_phy()
1850 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1852 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_serdes_phy()
1855 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_serdes_phy()
1856 		bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |  in bnx2_setup_serdes_phy()
1866 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_setup_serdes_phy()
1867 		bp->serdes_an_pending = 1;  in bnx2_setup_serdes_phy()
1868 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_setup_serdes_phy()
1870 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_serdes_phy()
1871 		bnx2_set_mac_link(bp);  in bnx2_setup_serdes_phy()
1878 	(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?			\
1893 bnx2_set_default_remote_link(struct bnx2 *bp)  in bnx2_set_default_remote_link()  argument
1897 	if (bp->phy_port == PORT_TP)  in bnx2_set_default_remote_link()
1898 		link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);  in bnx2_set_default_remote_link()
1900 		link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);  in bnx2_set_default_remote_link()
1903 		bp->req_line_speed = 0;  in bnx2_set_default_remote_link()
1904 		bp->autoneg |= AUTONEG_SPEED;  in bnx2_set_default_remote_link()
1905 		bp->advertising = ADVERTISED_Autoneg;  in bnx2_set_default_remote_link()
1907 			bp->advertising |= ADVERTISED_10baseT_Half;  in bnx2_set_default_remote_link()
1909 			bp->advertising |= ADVERTISED_10baseT_Full;  in bnx2_set_default_remote_link()
1911 			bp->advertising |= ADVERTISED_100baseT_Half;  in bnx2_set_default_remote_link()
1913 			bp->advertising |= ADVERTISED_100baseT_Full;  in bnx2_set_default_remote_link()
1915 			bp->advertising |= ADVERTISED_1000baseT_Full;  in bnx2_set_default_remote_link()
1917 			bp->advertising |= ADVERTISED_2500baseX_Full;  in bnx2_set_default_remote_link()
1919 		bp->autoneg = 0;  in bnx2_set_default_remote_link()
1920 		bp->advertising = 0;  in bnx2_set_default_remote_link()
1921 		bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_remote_link()
1923 			bp->req_line_speed = SPEED_10;  in bnx2_set_default_remote_link()
1925 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1928 			bp->req_line_speed = SPEED_100;  in bnx2_set_default_remote_link()
1930 				bp->req_duplex = DUPLEX_HALF;  in bnx2_set_default_remote_link()
1933 			bp->req_line_speed = SPEED_1000;  in bnx2_set_default_remote_link()
1935 			bp->req_line_speed = SPEED_2500;  in bnx2_set_default_remote_link()
1940 bnx2_set_default_link(struct bnx2 *bp)  in bnx2_set_default_link()  argument
1942 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_set_default_link()
1943 		bnx2_set_default_remote_link(bp);  in bnx2_set_default_link()
1947 	bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;  in bnx2_set_default_link()
1948 	bp->req_line_speed = 0;  in bnx2_set_default_link()
1949 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_set_default_link()
1952 		bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1954 		reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);  in bnx2_set_default_link()
1957 			bp->autoneg = 0;  in bnx2_set_default_link()
1958 			bp->req_line_speed = bp->line_speed = SPEED_1000;  in bnx2_set_default_link()
1959 			bp->req_duplex = DUPLEX_FULL;  in bnx2_set_default_link()
1962 		bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;  in bnx2_set_default_link()
1966 bnx2_send_heart_beat(struct bnx2 *bp)  in bnx2_send_heart_beat()  argument
1971 	spin_lock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1972 	msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);  in bnx2_send_heart_beat()
1973 	addr = bp->shmem_base + BNX2_DRV_PULSE_MB;  in bnx2_send_heart_beat()
1974 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);  in bnx2_send_heart_beat()
1975 	BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);  in bnx2_send_heart_beat()
1976 	spin_unlock(&bp->indirect_lock);  in bnx2_send_heart_beat()
1980 bnx2_remote_phy_event(struct bnx2 *bp)  in bnx2_remote_phy_event()  argument
1983 	u8 link_up = bp->link_up;  in bnx2_remote_phy_event()
1986 	msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_remote_phy_event()
1989 		bnx2_send_heart_beat(bp);  in bnx2_remote_phy_event()
1994 		bp->link_up = 0;  in bnx2_remote_phy_event()
1998 		bp->link_up = 1;  in bnx2_remote_phy_event()
2000 		bp->duplex = DUPLEX_FULL;  in bnx2_remote_phy_event()
2003 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2006 				bp->line_speed = SPEED_10;  in bnx2_remote_phy_event()
2009 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2013 				bp->line_speed = SPEED_100;  in bnx2_remote_phy_event()
2016 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2019 				bp->line_speed = SPEED_1000;  in bnx2_remote_phy_event()
2022 				bp->duplex = DUPLEX_HALF;  in bnx2_remote_phy_event()
2025 				bp->line_speed = SPEED_2500;  in bnx2_remote_phy_event()
2028 				bp->line_speed = 0;  in bnx2_remote_phy_event()
2032 		bp->flow_ctrl = 0;  in bnx2_remote_phy_event()
2033 		if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=  in bnx2_remote_phy_event()
2035 			if (bp->duplex == DUPLEX_FULL)  in bnx2_remote_phy_event()
2036 				bp->flow_ctrl = bp->req_flow_ctrl;  in bnx2_remote_phy_event()
2039 				bp->flow_ctrl |= FLOW_CTRL_TX;  in bnx2_remote_phy_event()
2041 				bp->flow_ctrl |= FLOW_CTRL_RX;  in bnx2_remote_phy_event()
2044 		old_port = bp->phy_port;  in bnx2_remote_phy_event()
2046 			bp->phy_port = PORT_FIBRE;  in bnx2_remote_phy_event()
2048 			bp->phy_port = PORT_TP;  in bnx2_remote_phy_event()
2050 		if (old_port != bp->phy_port)  in bnx2_remote_phy_event()
2051 			bnx2_set_default_link(bp);  in bnx2_remote_phy_event()
2054 	if (bp->link_up != link_up)  in bnx2_remote_phy_event()
2055 		bnx2_report_link(bp);  in bnx2_remote_phy_event()
2057 	bnx2_set_mac_link(bp);  in bnx2_remote_phy_event()
2061 bnx2_set_remote_link(struct bnx2 *bp)  in bnx2_set_remote_link()  argument
2065 	evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);  in bnx2_set_remote_link()
2068 			bnx2_remote_phy_event(bp);  in bnx2_set_remote_link()
2072 			bnx2_send_heart_beat(bp);  in bnx2_set_remote_link()
2079 bnx2_setup_copper_phy(struct bnx2 *bp)  in bnx2_setup_copper_phy()  argument
2080 __releases(&bp->phy_lock)  in bnx2_setup_copper_phy()
2081 __acquires(&bp->phy_lock)  in bnx2_setup_copper_phy()
2086 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_setup_copper_phy()
2088 	bnx2_read_phy(bp, bp->mii_adv, &adv_reg);  in bnx2_setup_copper_phy()
2092 	new_adv = ADVERTISE_CSMA | ethtool_adv_to_mii_adv_t(bp->advertising);  in bnx2_setup_copper_phy()
2094 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_setup_copper_phy()
2098 		new_adv |= bnx2_phy_get_pause_adv(bp);  in bnx2_setup_copper_phy()
2100 		bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);  in bnx2_setup_copper_phy()
2103 		new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);  in bnx2_setup_copper_phy()
2108 			bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2109 			bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);  in bnx2_setup_copper_phy()
2110 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |  in bnx2_setup_copper_phy()
2113 		else if (bp->link_up) {  in bnx2_setup_copper_phy()
2117 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2118 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2125 		bnx2_write_phy(bp, bp->mii_adv, new_adv);  in bnx2_setup_copper_phy()
2128 	if (bp->req_line_speed == SPEED_100) {  in bnx2_setup_copper_phy()
2131 	if (bp->req_duplex == DUPLEX_FULL) {  in bnx2_setup_copper_phy()
2137 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2138 		bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2142 			bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_setup_copper_phy()
2143 			spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2145 			spin_lock_bh(&bp->phy_lock);  in bnx2_setup_copper_phy()
2147 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2148 			bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);  in bnx2_setup_copper_phy()
2151 		bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);  in bnx2_setup_copper_phy()
2158 			bp->line_speed = bp->req_line_speed;  in bnx2_setup_copper_phy()
2159 			bp->duplex = bp->req_duplex;  in bnx2_setup_copper_phy()
2160 			bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2161 			bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2164 		bnx2_resolve_flow_ctrl(bp);  in bnx2_setup_copper_phy()
2165 		bnx2_set_mac_link(bp);  in bnx2_setup_copper_phy()
2171 bnx2_setup_phy(struct bnx2 *bp, u8 port)  in bnx2_setup_phy()  argument
2172 __releases(&bp->phy_lock)  in bnx2_setup_phy()
2173 __acquires(&bp->phy_lock)  in bnx2_setup_phy()
2175 	if (bp->loopback == MAC_LOOPBACK)  in bnx2_setup_phy()
2178 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_setup_phy()
2179 		return bnx2_setup_serdes_phy(bp, port);  in bnx2_setup_phy()
2182 		return bnx2_setup_copper_phy(bp);  in bnx2_setup_phy()
2187 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5709s_phy()  argument
2191 	bp->mii_bmcr = MII_BMCR + 0x10;  in bnx2_init_5709s_phy()
2192 	bp->mii_bmsr = MII_BMSR + 0x10;  in bnx2_init_5709s_phy()
2193 	bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;  in bnx2_init_5709s_phy()
2194 	bp->mii_adv = MII_ADVERTISE + 0x10;  in bnx2_init_5709s_phy()
2195 	bp->mii_lpa = MII_LPA + 0x10;  in bnx2_init_5709s_phy()
2196 	bp->mii_up1 = MII_BNX2_OVER1G_UP1;  in bnx2_init_5709s_phy()
2198 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);  in bnx2_init_5709s_phy()
2199 	bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);  in bnx2_init_5709s_phy()
2201 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2203 		bnx2_reset_phy(bp);  in bnx2_init_5709s_phy()
2205 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);  in bnx2_init_5709s_phy()
2207 	bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);  in bnx2_init_5709s_phy()
2210 	bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);  in bnx2_init_5709s_phy()
2212 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);  in bnx2_init_5709s_phy()
2213 	bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);  in bnx2_init_5709s_phy()
2214 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_init_5709s_phy()
2218 	bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);  in bnx2_init_5709s_phy()
2220 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);  in bnx2_init_5709s_phy()
2221 	bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);  in bnx2_init_5709s_phy()
2223 	bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);  in bnx2_init_5709s_phy()
2225 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);  in bnx2_init_5709s_phy()
2229 	bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);  in bnx2_init_5709s_phy()
2231 	bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);  in bnx2_init_5709s_phy()
2237 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5708s_phy()  argument
2242 		bnx2_reset_phy(bp);  in bnx2_init_5708s_phy()
2244 	bp->mii_up1 = BCM5708S_UP1;  in bnx2_init_5708s_phy()
2246 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);  in bnx2_init_5708s_phy()
2247 	bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);  in bnx2_init_5708s_phy()
2248 	bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2250 	bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);  in bnx2_init_5708s_phy()
2252 	bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);  in bnx2_init_5708s_phy()
2254 	bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);  in bnx2_init_5708s_phy()
2256 	bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);  in bnx2_init_5708s_phy()
2258 	if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {  in bnx2_init_5708s_phy()
2259 		bnx2_read_phy(bp, BCM5708S_UP1, &val);  in bnx2_init_5708s_phy()
2261 		bnx2_write_phy(bp, BCM5708S_UP1, val);  in bnx2_init_5708s_phy()
2264 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_5708s_phy()
2265 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_5708s_phy()
2266 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {  in bnx2_init_5708s_phy()
2268 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2270 		bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);  in bnx2_init_5708s_phy()
2272 		bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);  in bnx2_init_5708s_phy()
2273 		bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);  in bnx2_init_5708s_phy()
2276 	val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &  in bnx2_init_5708s_phy()
2282 		is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_5708s_phy()
2284 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2286 			bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);  in bnx2_init_5708s_phy()
2287 			bnx2_write_phy(bp, BCM5708S_BLK_ADDR,  in bnx2_init_5708s_phy()
2295 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_5706s_phy()  argument
2298 		bnx2_reset_phy(bp);  in bnx2_init_5706s_phy()
2300 	bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_init_5706s_phy()
2302 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_5706s_phy()
2303 		BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);  in bnx2_init_5706s_phy()
2305 	if (bp->dev->mtu > ETH_DATA_LEN) {  in bnx2_init_5706s_phy()
2309 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2310 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2311 		bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);  in bnx2_init_5706s_phy()
2313 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2314 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2315 		bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);  in bnx2_init_5706s_phy()
2320 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_5706s_phy()
2321 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_5706s_phy()
2322 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_5706s_phy()
2324 		bnx2_write_phy(bp, 0x1c, 0x6c00);  in bnx2_init_5706s_phy()
2325 		bnx2_read_phy(bp, 0x1c, &val);  in bnx2_init_5706s_phy()
2326 		bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);  in bnx2_init_5706s_phy()
2333 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_copper_phy()  argument
2338 		bnx2_reset_phy(bp);  in bnx2_init_copper_phy()
2340 	if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {  in bnx2_init_copper_phy()
2341 		bnx2_write_phy(bp, 0x18, 0x0c00);  in bnx2_init_copper_phy()
2342 		bnx2_write_phy(bp, 0x17, 0x000a);  in bnx2_init_copper_phy()
2343 		bnx2_write_phy(bp, 0x15, 0x310b);  in bnx2_init_copper_phy()
2344 		bnx2_write_phy(bp, 0x17, 0x201f);  in bnx2_init_copper_phy()
2345 		bnx2_write_phy(bp, 0x15, 0x9506);  in bnx2_init_copper_phy()
2346 		bnx2_write_phy(bp, 0x17, 0x401f);  in bnx2_init_copper_phy()
2347 		bnx2_write_phy(bp, 0x15, 0x14e2);  in bnx2_init_copper_phy()
2348 		bnx2_write_phy(bp, 0x18, 0x0400);  in bnx2_init_copper_phy()
2351 	if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {  in bnx2_init_copper_phy()
2352 		bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,  in bnx2_init_copper_phy()
2354 		bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);  in bnx2_init_copper_phy()
2356 		bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);  in bnx2_init_copper_phy()
2359 	if (bp->dev->mtu > ETH_DATA_LEN) {  in bnx2_init_copper_phy()
2361 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2362 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2363 		bnx2_write_phy(bp, 0x18, val | 0x4000);  in bnx2_init_copper_phy()
2365 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2366 		bnx2_write_phy(bp, 0x10, val | 0x1);  in bnx2_init_copper_phy()
2369 		bnx2_write_phy(bp, 0x18, 0x7);  in bnx2_init_copper_phy()
2370 		bnx2_read_phy(bp, 0x18, &val);  in bnx2_init_copper_phy()
2371 		bnx2_write_phy(bp, 0x18, val & ~0x4007);  in bnx2_init_copper_phy()
2373 		bnx2_read_phy(bp, 0x10, &val);  in bnx2_init_copper_phy()
2374 		bnx2_write_phy(bp, 0x10, val & ~0x1);  in bnx2_init_copper_phy()
2378 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL);  in bnx2_init_copper_phy()
2379 	bnx2_read_phy(bp, MII_BNX2_AUX_CTL, &val);  in bnx2_init_copper_phy()
2383 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_copper_phy()
2386 	bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val);  in bnx2_init_copper_phy()
2392 bnx2_init_phy(struct bnx2 *bp, int reset_phy)  in bnx2_init_phy()  argument
2393 __releases(&bp->phy_lock)  in bnx2_init_phy()
2394 __acquires(&bp->phy_lock)  in bnx2_init_phy()
2399 	bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;  in bnx2_init_phy()
2400 	bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;  in bnx2_init_phy()
2402 	bp->mii_bmcr = MII_BMCR;  in bnx2_init_phy()
2403 	bp->mii_bmsr = MII_BMSR;  in bnx2_init_phy()
2404 	bp->mii_bmsr1 = MII_BMSR;  in bnx2_init_phy()
2405 	bp->mii_adv = MII_ADVERTISE;  in bnx2_init_phy()
2406 	bp->mii_lpa = MII_LPA;  in bnx2_init_phy()
2408 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_phy()
2410 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_phy()
2413 	bnx2_read_phy(bp, MII_PHYSID1, &val);  in bnx2_init_phy()
2414 	bp->phy_id = val << 16;  in bnx2_init_phy()
2415 	bnx2_read_phy(bp, MII_PHYSID2, &val);  in bnx2_init_phy()
2416 	bp->phy_id |= val & 0xffff;  in bnx2_init_phy()
2418 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_phy()
2419 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_init_phy()
2420 			rc = bnx2_init_5706s_phy(bp, reset_phy);  in bnx2_init_phy()
2421 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_phy()
2422 			rc = bnx2_init_5708s_phy(bp, reset_phy);  in bnx2_init_phy()
2423 		else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_phy()
2424 			rc = bnx2_init_5709s_phy(bp, reset_phy);  in bnx2_init_phy()
2427 		rc = bnx2_init_copper_phy(bp, reset_phy);  in bnx2_init_phy()
2432 		rc = bnx2_setup_phy(bp, bp->phy_port);  in bnx2_init_phy()
2438 bnx2_set_mac_loopback(struct bnx2 *bp)  in bnx2_set_mac_loopback()  argument
2442 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_mac_loopback()
2445 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_mac_loopback()
2446 	bp->link_up = 1;  in bnx2_set_mac_loopback()
2453 bnx2_set_phy_loopback(struct bnx2 *bp)  in bnx2_set_phy_loopback()  argument
2458 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2459 	rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |  in bnx2_set_phy_loopback()
2461 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_phy_loopback()
2466 		if (bnx2_test_link(bp) == 0)  in bnx2_set_phy_loopback()
2471 	mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_phy_loopback()
2477 	BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);  in bnx2_set_phy_loopback()
2478 	bp->link_up = 1;  in bnx2_set_phy_loopback()
2483 bnx2_dump_mcp_state(struct bnx2 *bp)  in bnx2_dump_mcp_state()  argument
2485 	struct net_device *dev = bp->dev;  in bnx2_dump_mcp_state()
2489 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_dump_mcp_state()
2497 		   bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));  in bnx2_dump_mcp_state()
2499 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),  in bnx2_dump_mcp_state()
2500 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),  in bnx2_dump_mcp_state()
2501 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));  in bnx2_dump_mcp_state()
2503 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2504 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),  in bnx2_dump_mcp_state()
2505 		   bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));  in bnx2_dump_mcp_state()
2508 		   bnx2_shmem_rd(bp, BNX2_DRV_MB),  in bnx2_dump_mcp_state()
2509 		   bnx2_shmem_rd(bp, BNX2_FW_MB),  in bnx2_dump_mcp_state()
2510 		   bnx2_shmem_rd(bp, BNX2_LINK_STATUS));  in bnx2_dump_mcp_state()
2511 	pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));  in bnx2_dump_mcp_state()
2513 		   bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),  in bnx2_dump_mcp_state()
2514 		   bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));  in bnx2_dump_mcp_state()
2516 		bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));  in bnx2_dump_mcp_state()
2517 	DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);  in bnx2_dump_mcp_state()
2518 	DP_SHMEM_LINE(bp, 0x3cc);  in bnx2_dump_mcp_state()
2519 	DP_SHMEM_LINE(bp, 0x3dc);  in bnx2_dump_mcp_state()
2520 	DP_SHMEM_LINE(bp, 0x3ec);  in bnx2_dump_mcp_state()
2521 	netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));  in bnx2_dump_mcp_state()
2526 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)  in bnx2_fw_sync()  argument
2531 	bp->fw_wr_seq++;  in bnx2_fw_sync()
2532 	msg_data |= bp->fw_wr_seq;  in bnx2_fw_sync()
2533 	bp->fw_last_msg = msg_data;  in bnx2_fw_sync()
2535 	bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2544 		val = bnx2_shmem_rd(bp, BNX2_FW_MB);  in bnx2_fw_sync()
2557 		bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);  in bnx2_fw_sync()
2560 			bnx2_dump_mcp_state(bp);  in bnx2_fw_sync()
2573 bnx2_init_5709_context(struct bnx2 *bp)  in bnx2_init_5709_context()  argument
2580 	BNX2_WR(bp, BNX2_CTX_COMMAND, val);  in bnx2_init_5709_context()
2582 		val = BNX2_RD(bp, BNX2_CTX_COMMAND);  in bnx2_init_5709_context()
2590 	for (i = 0; i < bp->ctx_pages; i++) {  in bnx2_init_5709_context()
2593 		if (bp->ctx_blk[i])  in bnx2_init_5709_context()
2594 			memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);  in bnx2_init_5709_context()
2598 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,  in bnx2_init_5709_context()
2599 			(bp->ctx_blk_mapping[i] & 0xffffffff) |  in bnx2_init_5709_context()
2601 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,  in bnx2_init_5709_context()
2602 			(u64) bp->ctx_blk_mapping[i] >> 32);  in bnx2_init_5709_context()
2603 		BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |  in bnx2_init_5709_context()
2607 			val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);  in bnx2_init_5709_context()
2621 bnx2_init_context(struct bnx2 *bp)  in bnx2_init_context()  argument
2632 		if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_context()
2653 			BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);  in bnx2_init_context()
2654 			BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);  in bnx2_init_context()
2658 				bnx2_ctx_wr(bp, vcid_addr, offset, 0);  in bnx2_init_context()
2664 bnx2_alloc_bad_rbuf(struct bnx2 *bp)  in bnx2_alloc_bad_rbuf()  argument
2674 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_alloc_bad_rbuf()
2680 	val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2682 		bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,  in bnx2_alloc_bad_rbuf()
2685 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);  in bnx2_alloc_bad_rbuf()
2695 		val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);  in bnx2_alloc_bad_rbuf()
2706 		bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);  in bnx2_alloc_bad_rbuf()
2713 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)  in bnx2_set_mac_addr()  argument
2719 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);  in bnx2_set_mac_addr()
2724 	BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);  in bnx2_set_mac_addr()
2728 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_page()  argument
2738 	mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,  in bnx2_alloc_rx_page()
2740 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_page()
2753 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)  in bnx2_free_rx_page()  argument
2761 	dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),  in bnx2_free_rx_page()
2769 bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)  in bnx2_alloc_rx_data()  argument
2777 	data = kmalloc(bp->rx_buf_size, gfp);  in bnx2_alloc_rx_data()
2781 	mapping = dma_map_single(&bp->pdev->dev,  in bnx2_alloc_rx_data()
2783 				 bp->rx_buf_use_size,  in bnx2_alloc_rx_data()
2785 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_alloc_rx_data()
2796 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_alloc_rx_data()
2802 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)  in bnx2_phy_event_is_set()  argument
2812 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);  in bnx2_phy_event_is_set()
2814 			BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);  in bnx2_phy_event_is_set()
2822 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_phy_int()  argument
2824 	spin_lock(&bp->phy_lock);  in bnx2_phy_int()
2826 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))  in bnx2_phy_int()
2827 		bnx2_set_link(bp);  in bnx2_phy_int()
2828 	if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))  in bnx2_phy_int()
2829 		bnx2_set_remote_link(bp);  in bnx2_phy_int()
2831 	spin_unlock(&bp->phy_lock);  in bnx2_phy_int()
2848 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_tx_int()  argument
2856 	index = (bnapi - bp->bnx2_napi);  in bnx2_tx_int()
2857 	txq = netdev_get_tx_queue(bp->dev, index);  in bnx2_tx_int()
2889 		dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_tx_int()
2901 			dma_unmap_page(&bp->pdev->dev,  in bnx2_tx_int()
2931 		     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {  in bnx2_tx_int()
2934 		    (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))  in bnx2_tx_int()
2943 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_skb_pages()  argument
3001 bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,  in bnx2_reuse_rx_data()  argument
3010 	dma_sync_single_for_device(&bp->pdev->dev,  in bnx2_reuse_rx_data()
3014 	rxr->rx_prod_bseq += bp->rx_buf_use_size;  in bnx2_reuse_rx_data()
3031 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,  in bnx2_rx_skb()  argument
3039 	err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);  in bnx2_rx_skb()
3041 		bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);  in bnx2_rx_skb()
3047 			bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_skb()
3052 	dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,  in bnx2_rx_skb()
3082 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL,  in bnx2_rx_skb()
3107 			err = bnx2_alloc_rx_page(bp, rxr,  in bnx2_rx_skb()
3113 				bnx2_reuse_rx_skb_pages(bp, rxr, skb,  in bnx2_rx_skb()
3118 			dma_unmap_page(&bp->pdev->dev, mapping_old,  in bnx2_rx_skb()
3148 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)  in bnx2_rx_int()  argument
3187 		dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,  in bnx2_rx_int()
3202 		} else if (len > bp->rx_jumbo_thresh) {  in bnx2_rx_int()
3203 			hdr_len = bp->rx_jumbo_thresh;  in bnx2_rx_int()
3213 			bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3220 				bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);  in bnx2_rx_int()
3227 		if (len <= bp->rx_copy_thresh) {  in bnx2_rx_int()
3228 			skb = netdev_alloc_skb(bp->dev, len + 6);  in bnx2_rx_int()
3230 				bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,  in bnx2_rx_int()
3242 			bnx2_reuse_rx_data(bp, rxr, data,  in bnx2_rx_int()
3246 			skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,  in bnx2_rx_int()
3252 		    !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))  in bnx2_rx_int()
3255 		skb->protocol = eth_type_trans(skb, bp->dev);  in bnx2_rx_int()
3257 		if (len > (bp->dev->mtu + ETH_HLEN) &&  in bnx2_rx_int()
3267 		if ((bp->dev->features & NETIF_F_RXCSUM) &&  in bnx2_rx_int()
3275 		if ((bp->dev->features & NETIF_F_RXHASH) &&  in bnx2_rx_int()
3281 		skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);  in bnx2_rx_int()
3302 		BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_rx_int()
3304 	BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);  in bnx2_rx_int()
3306 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_rx_int()
3319 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi()  local
3322 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_msi()
3327 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi()
3339 	struct bnx2 *bp = bnapi->bp;  in bnx2_msi_1shot()  local
3344 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_msi_1shot()
3356 	struct bnx2 *bp = bnapi->bp;  in bnx2_interrupt()  local
3366 	    (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &  in bnx2_interrupt()
3370 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_interrupt()
3377 	BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);  in bnx2_interrupt()
3380 	if (unlikely(atomic_read(&bp->intr_sem) != 0))  in bnx2_interrupt()
3427 bnx2_chk_missed_msi(struct bnx2 *bp)  in bnx2_chk_missed_msi()  argument
3429 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0];  in bnx2_chk_missed_msi()
3433 		msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);  in bnx2_chk_missed_msi()
3437 		if (bnapi->last_status_idx == bp->idle_chk_status_idx) {  in bnx2_chk_missed_msi()
3438 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &  in bnx2_chk_missed_msi()
3440 			BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);  in bnx2_chk_missed_msi()
3441 			bnx2_msi(bp->irq_tbl[0].vector, bnapi);  in bnx2_chk_missed_msi()
3445 	bp->idle_chk_status_idx = bnapi->last_status_idx;  in bnx2_chk_missed_msi()
3449 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_cnic()  argument
3457 	c_ops = rcu_dereference(bp->cnic_ops);  in bnx2_poll_cnic()
3459 		bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,  in bnx2_poll_cnic()
3465 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)  in bnx2_poll_link()  argument
3474 		bnx2_phy_int(bp, bnapi);  in bnx2_poll_link()
3479 		BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_poll_link()
3480 			bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_poll_link()
3481 		BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_poll_link()
3485 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,  in bnx2_poll_work()  argument
3492 		bnx2_tx_int(bp, bnapi, 0);  in bnx2_poll_work()
3495 		work_done += bnx2_rx_int(bp, bnapi, budget - work_done);  in bnx2_poll_work()
3503 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll_msix()  local
3508 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll_msix()
3518 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |  in bnx2_poll_msix()
3530 	struct bnx2 *bp = bnapi->bp;  in bnx2_poll()  local
3535 		bnx2_poll_link(bp, bnapi);  in bnx2_poll()
3537 		work_done = bnx2_poll_work(bp, bnapi, work_done, budget);  in bnx2_poll()
3540 		bnx2_poll_cnic(bp, bnapi);  in bnx2_poll()
3555 			if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {  in bnx2_poll()
3556 				BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3561 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3566 			BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,  in bnx2_poll()
3582 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_rx_mode()  local
3590 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3592 	rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |  in bnx2_set_rx_mode()
3596 	     (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_set_rx_mode()
3606 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3629 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_set_rx_mode()
3644 			bnx2_set_mac_addr(bp, ha->addr,  in bnx2_set_rx_mode()
3653 	if (rx_mode != bp->rx_mode) {  in bnx2_set_rx_mode()
3654 		bp->rx_mode = rx_mode;  in bnx2_set_rx_mode()
3655 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);  in bnx2_set_rx_mode()
3658 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_set_rx_mode()
3659 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);  in bnx2_set_rx_mode()
3660 	BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);  in bnx2_set_rx_mode()
3662 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_rx_mode()
3692 static void bnx2_release_firmware(struct bnx2 *bp)  in bnx2_release_firmware()  argument
3694 	if (bp->rv2p_firmware) {  in bnx2_release_firmware()
3695 		release_firmware(bp->mips_firmware);  in bnx2_release_firmware()
3696 		release_firmware(bp->rv2p_firmware);  in bnx2_release_firmware()
3697 		bp->rv2p_firmware = NULL;  in bnx2_release_firmware()
3701 static int bnx2_request_uncached_firmware(struct bnx2 *bp)  in bnx2_request_uncached_firmware()  argument
3708 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_request_uncached_firmware()
3710 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||  in bnx2_request_uncached_firmware()
3711 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))  in bnx2_request_uncached_firmware()
3720 	rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3726 	rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);  in bnx2_request_uncached_firmware()
3731 	mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_request_uncached_firmware()
3732 	rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_request_uncached_firmware()
3733 	if (bp->mips_firmware->size < sizeof(*mips_fw) ||  in bnx2_request_uncached_firmware()
3734 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||  in bnx2_request_uncached_firmware()
3735 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||  in bnx2_request_uncached_firmware()
3736 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||  in bnx2_request_uncached_firmware()
3737 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||  in bnx2_request_uncached_firmware()
3738 	    check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {  in bnx2_request_uncached_firmware()
3743 	if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||  in bnx2_request_uncached_firmware()
3744 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||  in bnx2_request_uncached_firmware()
3745 	    check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {  in bnx2_request_uncached_firmware()
3754 	release_firmware(bp->rv2p_firmware);  in bnx2_request_uncached_firmware()
3755 	bp->rv2p_firmware = NULL;  in bnx2_request_uncached_firmware()
3757 	release_firmware(bp->mips_firmware);  in bnx2_request_uncached_firmware()
3761 static int bnx2_request_firmware(struct bnx2 *bp)  in bnx2_request_firmware()  argument
3763 	return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);  in bnx2_request_firmware()
3779 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,  in load_rv2p_fw()  argument
3790 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3801 		BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3803 		BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));  in load_rv2p_fw()
3807 		BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3810 	rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);  in load_rv2p_fw()
3817 			BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);  in load_rv2p_fw()
3820 			BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);  in load_rv2p_fw()
3823 			BNX2_WR(bp, addr, val);  in load_rv2p_fw()
3829 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);  in load_rv2p_fw()
3832 		BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);  in load_rv2p_fw()
3839 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,  in load_cpu_fw()  argument
3848 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3850 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3851 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3857 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3864 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3871 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3878 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3885 	data = (__be32 *)(bp->mips_firmware->data + file_offset);  in load_cpu_fw()
3892 			bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));  in load_cpu_fw()
3896 	bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);  in load_cpu_fw()
3899 	bnx2_reg_wr_ind(bp, cpu_reg->pc, val);  in load_cpu_fw()
3902 	val = bnx2_reg_rd_ind(bp, cpu_reg->mode);  in load_cpu_fw()
3904 	bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);  in load_cpu_fw()
3905 	bnx2_reg_wr_ind(bp, cpu_reg->mode, val);  in load_cpu_fw()
3911 bnx2_init_cpus(struct bnx2 *bp)  in bnx2_init_cpus()  argument
3914 		(const struct bnx2_mips_fw_file *) bp->mips_firmware->data;  in bnx2_init_cpus()
3916 		(const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;  in bnx2_init_cpus()
3920 	load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);  in bnx2_init_cpus()
3921 	load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);  in bnx2_init_cpus()
3924 	rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);  in bnx2_init_cpus()
3929 	rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);  in bnx2_init_cpus()
3934 	rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);  in bnx2_init_cpus()
3939 	rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);  in bnx2_init_cpus()
3944 	rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);  in bnx2_init_cpus()
3951 bnx2_setup_wol(struct bnx2 *bp)  in bnx2_setup_wol()  argument
3956 	if (bp->wol) {  in bnx2_setup_wol()
3960 		autoneg = bp->autoneg;  in bnx2_setup_wol()
3961 		advertising = bp->advertising;  in bnx2_setup_wol()
3963 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3964 			bp->autoneg = AUTONEG_SPEED;  in bnx2_setup_wol()
3965 			bp->advertising = ADVERTISED_10baseT_Half |  in bnx2_setup_wol()
3972 		spin_lock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3973 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_setup_wol()
3974 		spin_unlock_bh(&bp->phy_lock);  in bnx2_setup_wol()
3976 		bp->autoneg = autoneg;  in bnx2_setup_wol()
3977 		bp->advertising = advertising;  in bnx2_setup_wol()
3979 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_setup_wol()
3981 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_setup_wol()
3988 		if (bp->phy_port == PORT_TP) {  in bnx2_setup_wol()
3992 			if (bp->line_speed == SPEED_2500)  in bnx2_setup_wol()
3996 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_setup_wol()
4000 			BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),  in bnx2_setup_wol()
4003 		BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);  in bnx2_setup_wol()
4006 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);  in bnx2_setup_wol()
4007 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);  in bnx2_setup_wol()
4008 		BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);  in bnx2_setup_wol()
4011 		BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_setup_wol()
4016 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_setup_wol()
4018 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_setup_wol()
4025 	if (!(bp->flags & BNX2_FLAG_NO_WOL)) {  in bnx2_setup_wol()
4029 		if (bp->fw_last_msg || BNX2_CHIP(bp) != BNX2_CHIP_5709) {  in bnx2_setup_wol()
4030 			bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4036 		val = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_setup_wol()
4037 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE,  in bnx2_setup_wol()
4039 		bnx2_fw_sync(bp, wol_msg, 1, 0);  in bnx2_setup_wol()
4040 		bnx2_shmem_wr(bp, BNX2_PORT_FEATURE, val);  in bnx2_setup_wol()
4046 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)  in bnx2_set_power_state()  argument
4052 		pci_enable_wake(bp->pdev, PCI_D0, false);  in bnx2_set_power_state()
4053 		pci_set_power_state(bp->pdev, PCI_D0);  in bnx2_set_power_state()
4055 		val = BNX2_RD(bp, BNX2_EMAC_MODE);  in bnx2_set_power_state()
4058 		BNX2_WR(bp, BNX2_EMAC_MODE, val);  in bnx2_set_power_state()
4060 		val = BNX2_RD(bp, BNX2_RPM_CONFIG);  in bnx2_set_power_state()
4062 		BNX2_WR(bp, BNX2_RPM_CONFIG, val);  in bnx2_set_power_state()
4066 		bnx2_setup_wol(bp);  in bnx2_set_power_state()
4067 		pci_wake_from_d3(bp->pdev, bp->wol);  in bnx2_set_power_state()
4068 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_set_power_state()
4069 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {  in bnx2_set_power_state()
4071 			if (bp->wol)  in bnx2_set_power_state()
4072 				pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4076 		if (!bp->fw_last_msg && BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_set_power_state()
4083 			val = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_set_power_state()
4086 			bnx2_shmem_wr(bp, BNX2_BC_STATE_CONDITION, val);  in bnx2_set_power_state()
4088 		pci_set_power_state(bp->pdev, PCI_D3hot);  in bnx2_set_power_state()
4102 bnx2_acquire_nvram_lock(struct bnx2 *bp)  in bnx2_acquire_nvram_lock()  argument
4108 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);  in bnx2_acquire_nvram_lock()
4110 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_acquire_nvram_lock()
4124 bnx2_release_nvram_lock(struct bnx2 *bp)  in bnx2_release_nvram_lock()  argument
4130 	BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);  in bnx2_release_nvram_lock()
4133 		val = BNX2_RD(bp, BNX2_NVM_SW_ARB);  in bnx2_release_nvram_lock()
4148 bnx2_enable_nvram_write(struct bnx2 *bp)  in bnx2_enable_nvram_write()  argument
4152 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_enable_nvram_write()
4153 	BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);  in bnx2_enable_nvram_write()
4155 	if (bp->flash_info->flags & BNX2_NV_WREN) {  in bnx2_enable_nvram_write()
4158 		BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_enable_nvram_write()
4159 		BNX2_WR(bp, BNX2_NVM_COMMAND,  in bnx2_enable_nvram_write()
4165 			val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_enable_nvram_write()
4177 bnx2_disable_nvram_write(struct bnx2 *bp)  in bnx2_disable_nvram_write()  argument
4181 	val = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_disable_nvram_write()
4182 	BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);  in bnx2_disable_nvram_write()
4187 bnx2_enable_nvram_access(struct bnx2 *bp)  in bnx2_enable_nvram_access()  argument
4191 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_enable_nvram_access()
4193 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_enable_nvram_access()
4198 bnx2_disable_nvram_access(struct bnx2 *bp)  in bnx2_disable_nvram_access()  argument
4202 	val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);  in bnx2_disable_nvram_access()
4204 	BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,  in bnx2_disable_nvram_access()
4210 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)  in bnx2_nvram_erase_page()  argument
4215 	if (bp->flash_info->flags & BNX2_NV_BUFFERED)  in bnx2_nvram_erase_page()
4224 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_erase_page()
4227 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_erase_page()
4230 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_erase_page()
4238 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_erase_page()
4250 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)  in bnx2_nvram_read_dword()  argument
4259 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_read_dword()
4260 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_read_dword()
4261 			   bp->flash_info->page_bits) +  in bnx2_nvram_read_dword()
4262 			  (offset % bp->flash_info->page_size);  in bnx2_nvram_read_dword()
4266 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_read_dword()
4269 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_read_dword()
4272 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_read_dword()
4280 		val = BNX2_RD(bp, BNX2_NVM_COMMAND);  in bnx2_nvram_read_dword()
4282 			__be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));  in bnx2_nvram_read_dword()
4295 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)  in bnx2_nvram_write_dword()  argument
4305 	if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {  in bnx2_nvram_write_dword()
4306 		offset = ((offset / bp->flash_info->page_size) <<  in bnx2_nvram_write_dword()
4307 			  bp->flash_info->page_bits) +  in bnx2_nvram_write_dword()
4308 			 (offset % bp->flash_info->page_size);  in bnx2_nvram_write_dword()
4312 	BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);  in bnx2_nvram_write_dword()
4317 	BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));  in bnx2_nvram_write_dword()
4320 	BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);  in bnx2_nvram_write_dword()
4323 	BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);  in bnx2_nvram_write_dword()
4329 		if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)  in bnx2_nvram_write_dword()
4339 bnx2_init_nvram(struct bnx2 *bp)  in bnx2_init_nvram()  argument
4345 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_nvram()
4346 		bp->flash_info = &flash_5709;  in bnx2_init_nvram()
4351 	val = BNX2_RD(bp, BNX2_NVM_CFG1);  in bnx2_init_nvram()
4362 				bp->flash_info = flash;  in bnx2_init_nvram()
4380 				bp->flash_info = flash;  in bnx2_init_nvram()
4383 				if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_init_nvram()
4387 				bnx2_enable_nvram_access(bp);  in bnx2_init_nvram()
4390 				BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);  in bnx2_init_nvram()
4391 				BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);  in bnx2_init_nvram()
4392 				BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);  in bnx2_init_nvram()
4393 				BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);  in bnx2_init_nvram()
4396 				bnx2_disable_nvram_access(bp);  in bnx2_init_nvram()
4397 				bnx2_release_nvram_lock(bp);  in bnx2_init_nvram()
4405 		bp->flash_info = NULL;  in bnx2_init_nvram()
4411 	val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);  in bnx2_init_nvram()
4414 		bp->flash_size = val;  in bnx2_init_nvram()
4416 		bp->flash_size = bp->flash_info->total_size;  in bnx2_init_nvram()
4422 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,  in bnx2_nvram_read()  argument
4432 	if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_read()
4436 	bnx2_enable_nvram_access(bp);  in bnx2_nvram_read()
4460 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4485 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4498 		rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);  in bnx2_nvram_read()
4506 			rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);  in bnx2_nvram_read()
4518 		rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);  in bnx2_nvram_read()
4524 	bnx2_disable_nvram_access(bp);  in bnx2_nvram_read()
4526 	bnx2_release_nvram_lock(bp);  in bnx2_nvram_read()
4532 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,  in bnx2_nvram_write()  argument
4550 		if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))  in bnx2_nvram_write()
4557 		if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))  in bnx2_nvram_write()
4575 	if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4591 		page_start -= (page_start % bp->flash_info->page_size);  in bnx2_nvram_write()
4593 		page_end = page_start + bp->flash_info->page_size;  in bnx2_nvram_write()
4601 		if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)  in bnx2_nvram_write()
4605 		bnx2_enable_nvram_access(bp);  in bnx2_nvram_write()
4608 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4613 			for (j = 0; j < bp->flash_info->page_size; j += 4) {  in bnx2_nvram_write()
4614 				if (j == (bp->flash_info->page_size - 4)) {  in bnx2_nvram_write()
4617 				rc = bnx2_nvram_read_dword(bp,  in bnx2_nvram_write()
4630 		if ((rc = bnx2_enable_nvram_write(bp)) != 0)  in bnx2_nvram_write()
4636 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4638 			if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)  in bnx2_nvram_write()
4642 			bnx2_enable_nvram_write(bp);  in bnx2_nvram_write()
4647 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4660 				((bp->flash_info->flags & BNX2_NV_BUFFERED) &&  in bnx2_nvram_write()
4665 			rc = bnx2_nvram_write_dword(bp, addr, buf,  in bnx2_nvram_write()
4677 		if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {  in bnx2_nvram_write()
4684 				rc = bnx2_nvram_write_dword(bp, addr,  in bnx2_nvram_write()
4695 		bnx2_disable_nvram_write(bp);  in bnx2_nvram_write()
4698 		bnx2_disable_nvram_access(bp);  in bnx2_nvram_write()
4699 		bnx2_release_nvram_lock(bp);  in bnx2_nvram_write()
4712 bnx2_init_fw_cap(struct bnx2 *bp)  in bnx2_init_fw_cap()  argument
4716 	bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4717 	bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4719 	if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))  in bnx2_init_fw_cap()
4720 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4722 	val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);  in bnx2_init_fw_cap()
4727 		bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;  in bnx2_init_fw_cap()
4731 	if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&  in bnx2_init_fw_cap()
4735 		bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;  in bnx2_init_fw_cap()
4737 		link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);  in bnx2_init_fw_cap()
4739 			bp->phy_port = PORT_FIBRE;  in bnx2_init_fw_cap()
4741 			bp->phy_port = PORT_TP;  in bnx2_init_fw_cap()
4747 	if (netif_running(bp->dev) && sig)  in bnx2_init_fw_cap()
4748 		bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);  in bnx2_init_fw_cap()
4752 bnx2_setup_msix_tbl(struct bnx2 *bp)  in bnx2_setup_msix_tbl()  argument
4754 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);  in bnx2_setup_msix_tbl()
4756 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);  in bnx2_setup_msix_tbl()
4757 	BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);  in bnx2_setup_msix_tbl()
4761 bnx2_wait_dma_complete(struct bnx2 *bp)  in bnx2_wait_dma_complete()  argument
4770 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_wait_dma_complete()
4771 	    (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {  in bnx2_wait_dma_complete()
4772 		BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,  in bnx2_wait_dma_complete()
4777 		val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);  in bnx2_wait_dma_complete()
4780 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_wait_dma_complete()
4782 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_wait_dma_complete()
4783 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_wait_dma_complete()
4787 			val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);  in bnx2_wait_dma_complete()
4798 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_chip()  argument
4806 	bnx2_wait_dma_complete(bp);  in bnx2_reset_chip()
4809 	bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);  in bnx2_reset_chip()
4813 	bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,  in bnx2_reset_chip()
4818 	val = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_reset_chip()
4820 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_reset_chip()
4821 		BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);  in bnx2_reset_chip()
4822 		BNX2_RD(bp, BNX2_MISC_COMMAND);  in bnx2_reset_chip()
4828 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4836 		BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);  in bnx2_reset_chip()
4842 		if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_reset_chip()
4843 		    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))  in bnx2_reset_chip()
4848 			val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);  in bnx2_reset_chip()
4863 	val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);  in bnx2_reset_chip()
4870 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);  in bnx2_reset_chip()
4874 	spin_lock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4875 	old_port = bp->phy_port;  in bnx2_reset_chip()
4876 	bnx2_init_fw_cap(bp);  in bnx2_reset_chip()
4877 	if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&  in bnx2_reset_chip()
4878 	    old_port != bp->phy_port)  in bnx2_reset_chip()
4879 		bnx2_set_default_remote_link(bp);  in bnx2_reset_chip()
4880 	spin_unlock_bh(&bp->phy_lock);  in bnx2_reset_chip()
4882 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_reset_chip()
4885 		BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);  in bnx2_reset_chip()
4888 		rc = bnx2_alloc_bad_rbuf(bp);  in bnx2_reset_chip()
4891 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_reset_chip()
4892 		bnx2_setup_msix_tbl(bp);  in bnx2_reset_chip()
4894 		BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,  in bnx2_reset_chip()
4902 bnx2_init_chip(struct bnx2 *bp)  in bnx2_init_chip()  argument
4908 	BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);  in bnx2_init_chip()
4921 	if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))  in bnx2_init_chip()
4924 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&  in bnx2_init_chip()
4925 	    (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&  in bnx2_init_chip()
4926 	    !(bp->flags & BNX2_FLAG_PCIX))  in bnx2_init_chip()
4929 	BNX2_WR(bp, BNX2_DMA_CONFIG, val);  in bnx2_init_chip()
4931 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_chip()
4932 		val = BNX2_RD(bp, BNX2_TDMA_CONFIG);  in bnx2_init_chip()
4934 		BNX2_WR(bp, BNX2_TDMA_CONFIG, val);  in bnx2_init_chip()
4937 	if (bp->flags & BNX2_FLAG_PCIX) {  in bnx2_init_chip()
4940 		pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4942 		pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,  in bnx2_init_chip()
4946 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,  in bnx2_init_chip()
4953 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4954 		rc = bnx2_init_5709_context(bp);  in bnx2_init_chip()
4958 		bnx2_init_context(bp);  in bnx2_init_chip()
4960 	if ((rc = bnx2_init_cpus(bp)) != 0)  in bnx2_init_chip()
4963 	bnx2_init_nvram(bp);  in bnx2_init_chip()
4965 	bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_init_chip()
4967 	val = BNX2_RD(bp, BNX2_MQ_CONFIG);  in bnx2_init_chip()
4970 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
4972 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_chip()
4976 	BNX2_WR(bp, BNX2_MQ_CONFIG, val);  in bnx2_init_chip()
4979 	BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);  in bnx2_init_chip()
4980 	BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);  in bnx2_init_chip()
4983 	BNX2_WR(bp, BNX2_RV2P_CONFIG, val);  in bnx2_init_chip()
4986 	val = BNX2_RD(bp, BNX2_TBDR_CONFIG);  in bnx2_init_chip()
4989 	BNX2_WR(bp, BNX2_TBDR_CONFIG, val);  in bnx2_init_chip()
4991 	val = bp->mac_addr[0] +  in bnx2_init_chip()
4992 	      (bp->mac_addr[1] << 8) +  in bnx2_init_chip()
4993 	      (bp->mac_addr[2] << 16) +  in bnx2_init_chip()
4994 	      bp->mac_addr[3] +  in bnx2_init_chip()
4995 	      (bp->mac_addr[4] << 8) +  in bnx2_init_chip()
4996 	      (bp->mac_addr[5] << 16);  in bnx2_init_chip()
4997 	BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);  in bnx2_init_chip()
5000 	mtu = bp->dev->mtu;  in bnx2_init_chip()
5004 	BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);  in bnx2_init_chip()
5009 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));  in bnx2_init_chip()
5010 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));  in bnx2_init_chip()
5011 	bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));  in bnx2_init_chip()
5013 	memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);  in bnx2_init_chip()
5015 		bp->bnx2_napi[i].last_status_idx = 0;  in bnx2_init_chip()
5017 	bp->idle_chk_status_idx = 0xffff;  in bnx2_init_chip()
5020 	BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);  in bnx2_init_chip()
5022 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,  in bnx2_init_chip()
5023 		(u64) bp->status_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5024 	BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);  in bnx2_init_chip()
5026 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,  in bnx2_init_chip()
5027 		(u64) bp->stats_blk_mapping & 0xffffffff);  in bnx2_init_chip()
5028 	BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,  in bnx2_init_chip()
5029 		(u64) bp->stats_blk_mapping >> 32);  in bnx2_init_chip()
5031 	BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5032 		(bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);  in bnx2_init_chip()
5034 	BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,  in bnx2_init_chip()
5035 		(bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);  in bnx2_init_chip()
5037 	BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,  in bnx2_init_chip()
5038 		(bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);  in bnx2_init_chip()
5040 	BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5042 	BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5044 	BNX2_WR(bp, BNX2_HC_COM_TICKS,  in bnx2_init_chip()
5045 		(bp->com_ticks_int << 16) | bp->com_ticks);  in bnx2_init_chip()
5047 	BNX2_WR(bp, BNX2_HC_CMD_TICKS,  in bnx2_init_chip()
5048 		(bp->cmd_ticks_int << 16) | bp->cmd_ticks);  in bnx2_init_chip()
5050 	if (bp->flags & BNX2_FLAG_BROKEN_STATS)  in bnx2_init_chip()
5051 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);  in bnx2_init_chip()
5053 		BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);  in bnx2_init_chip()
5054 	BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */  in bnx2_init_chip()
5056 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)  in bnx2_init_chip()
5063 	if (bp->flags & BNX2_FLAG_USING_MSIX) {  in bnx2_init_chip()
5064 		BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,  in bnx2_init_chip()
5070 	if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)  in bnx2_init_chip()
5073 	BNX2_WR(bp, BNX2_HC_CONFIG, val);  in bnx2_init_chip()
5075 	if (bp->rx_ticks < 25)  in bnx2_init_chip()
5076 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);  in bnx2_init_chip()
5078 		bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);  in bnx2_init_chip()
5080 	for (i = 1; i < bp->irq_nvecs; i++) {  in bnx2_init_chip()
5084 		BNX2_WR(bp, base,  in bnx2_init_chip()
5089 		BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5090 			(bp->tx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5091 			 bp->tx_quick_cons_trip);  in bnx2_init_chip()
5093 		BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,  in bnx2_init_chip()
5094 			(bp->tx_ticks_int << 16) | bp->tx_ticks);  in bnx2_init_chip()
5096 		BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,  in bnx2_init_chip()
5097 			(bp->rx_quick_cons_trip_int << 16) |  in bnx2_init_chip()
5098 			bp->rx_quick_cons_trip);  in bnx2_init_chip()
5100 		BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,  in bnx2_init_chip()
5101 			(bp->rx_ticks_int << 16) | bp->rx_ticks);  in bnx2_init_chip()
5105 	BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);  in bnx2_init_chip()
5107 	BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);  in bnx2_init_chip()
5110 	bnx2_set_rx_mode(bp->dev);  in bnx2_init_chip()
5112 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_chip()
5113 		val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);  in bnx2_init_chip()
5115 		BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);  in bnx2_init_chip()
5117 	rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,  in bnx2_init_chip()
5120 	BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);  in bnx2_init_chip()
5121 	BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);  in bnx2_init_chip()
5125 	bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_init_chip()
5131 bnx2_clear_ring_states(struct bnx2 *bp)  in bnx2_clear_ring_states()  argument
5139 		bnapi = &bp->bnx2_napi[i];  in bnx2_clear_ring_states()
5154 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)  in bnx2_init_tx_context()  argument
5159 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_tx_context()
5171 	bnx2_ctx_wr(bp, cid_addr, offset0, val);  in bnx2_init_tx_context()
5174 	bnx2_ctx_wr(bp, cid_addr, offset1, val);  in bnx2_init_tx_context()
5177 	bnx2_ctx_wr(bp, cid_addr, offset2, val);  in bnx2_init_tx_context()
5180 	bnx2_ctx_wr(bp, cid_addr, offset3, val);  in bnx2_init_tx_context()
5184 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_tx_ring()  argument
5191 	bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_tx_ring()
5199 	bp->tx_wake_thresh = bp->tx_ring_size / 2;  in bnx2_init_tx_ring()
5212 	bnx2_init_tx_context(bp, cid, txr);  in bnx2_init_tx_ring()
5240 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)  in bnx2_init_rx_ring()  argument
5245 	struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];  in bnx2_init_rx_ring()
5256 			     bp->rx_buf_use_size, bp->rx_max_ring);  in bnx2_init_rx_ring()
5258 	bnx2_init_rx_context(bp, cid);  in bnx2_init_rx_ring()
5260 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_rx_ring()
5261 		val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);  in bnx2_init_rx_ring()
5262 		BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);  in bnx2_init_rx_ring()
5265 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);  in bnx2_init_rx_ring()
5266 	if (bp->rx_pg_ring_size) {  in bnx2_init_rx_ring()
5269 				     PAGE_SIZE, bp->rx_max_pg_ring);  in bnx2_init_rx_ring()
5270 		val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;  in bnx2_init_rx_ring()
5271 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);  in bnx2_init_rx_ring()
5272 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,  in bnx2_init_rx_ring()
5276 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5279 		bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5281 		if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_rx_ring()
5282 			BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);  in bnx2_init_rx_ring()
5286 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);  in bnx2_init_rx_ring()
5289 	bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);  in bnx2_init_rx_ring()
5292 	for (i = 0; i < bp->rx_pg_ring_size; i++) {  in bnx2_init_rx_ring()
5293 		if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5294 			netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",  in bnx2_init_rx_ring()
5295 				    ring_num, i, bp->rx_pg_ring_size);  in bnx2_init_rx_ring()
5304 	for (i = 0; i < bp->rx_ring_size; i++) {  in bnx2_init_rx_ring()
5305 		if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {  in bnx2_init_rx_ring()
5306 			netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",  in bnx2_init_rx_ring()
5307 				    ring_num, i, bp->rx_ring_size);  in bnx2_init_rx_ring()
5319 	BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);  in bnx2_init_rx_ring()
5320 	BNX2_WR16(bp, rxr->rx_bidx_addr, prod);  in bnx2_init_rx_ring()
5322 	BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);  in bnx2_init_rx_ring()
5326 bnx2_init_all_rings(struct bnx2 *bp)  in bnx2_init_all_rings()  argument
5331 	bnx2_clear_ring_states(bp);  in bnx2_init_all_rings()
5333 	BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);  in bnx2_init_all_rings()
5334 	for (i = 0; i < bp->num_tx_rings; i++)  in bnx2_init_all_rings()
5335 		bnx2_init_tx_ring(bp, i);  in bnx2_init_all_rings()
5337 	if (bp->num_tx_rings > 1)  in bnx2_init_all_rings()
5338 		BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |  in bnx2_init_all_rings()
5341 	BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);  in bnx2_init_all_rings()
5342 	bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);  in bnx2_init_all_rings()
5344 	for (i = 0; i < bp->num_rx_rings; i++)  in bnx2_init_all_rings()
5345 		bnx2_init_rx_ring(bp, i);  in bnx2_init_all_rings()
5347 	if (bp->num_rx_rings > 1) {  in bnx2_init_all_rings()
5353 			tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;  in bnx2_init_all_rings()
5355 				BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);  in bnx2_init_all_rings()
5356 				BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |  in bnx2_init_all_rings()
5367 		BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);  in bnx2_init_all_rings()
5392 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)  in bnx2_set_rx_ring_size()  argument
5397 	rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;  in bnx2_set_rx_ring_size()
5402 	bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;  in bnx2_set_rx_ring_size()
5403 	bp->rx_pg_ring_size = 0;  in bnx2_set_rx_ring_size()
5404 	bp->rx_max_pg_ring = 0;  in bnx2_set_rx_ring_size()
5405 	bp->rx_max_pg_ring_idx = 0;  in bnx2_set_rx_ring_size()
5406 	if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {  in bnx2_set_rx_ring_size()
5407 		int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;  in bnx2_set_rx_ring_size()
5413 		bp->rx_pg_ring_size = jumbo_size;  in bnx2_set_rx_ring_size()
5414 		bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,  in bnx2_set_rx_ring_size()
5416 		bp->rx_max_pg_ring_idx =  in bnx2_set_rx_ring_size()
5417 			(bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5419 		bp->rx_copy_thresh = 0;  in bnx2_set_rx_ring_size()
5422 	bp->rx_buf_use_size = rx_size;  in bnx2_set_rx_ring_size()
5424 	bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +  in bnx2_set_rx_ring_size()
5426 	bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;  in bnx2_set_rx_ring_size()
5427 	bp->rx_ring_size = size;  in bnx2_set_rx_ring_size()
5428 	bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);  in bnx2_set_rx_ring_size()
5429 	bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;  in bnx2_set_rx_ring_size()
5433 bnx2_free_tx_skbs(struct bnx2 *bp)  in bnx2_free_tx_skbs()  argument
5437 	for (i = 0; i < bp->num_tx_rings; i++) {  in bnx2_free_tx_skbs()
5438 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_tx_skbs()
5455 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5466 				dma_unmap_page(&bp->pdev->dev,  in bnx2_free_tx_skbs()
5473 		netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));  in bnx2_free_tx_skbs()
5478 bnx2_free_rx_skbs(struct bnx2 *bp)  in bnx2_free_rx_skbs()  argument
5482 	for (i = 0; i < bp->num_rx_rings; i++) {  in bnx2_free_rx_skbs()
5483 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_free_rx_skbs()
5490 		for (j = 0; j < bp->rx_max_ring_idx; j++) {  in bnx2_free_rx_skbs()
5497 			dma_unmap_single(&bp->pdev->dev,  in bnx2_free_rx_skbs()
5499 					 bp->rx_buf_use_size,  in bnx2_free_rx_skbs()
5506 		for (j = 0; j < bp->rx_max_pg_ring_idx; j++)  in bnx2_free_rx_skbs()
5507 			bnx2_free_rx_page(bp, rxr, j);  in bnx2_free_rx_skbs()
5512 bnx2_free_skbs(struct bnx2 *bp)  in bnx2_free_skbs()  argument
5514 	bnx2_free_tx_skbs(bp);  in bnx2_free_skbs()
5515 	bnx2_free_rx_skbs(bp);  in bnx2_free_skbs()
5519 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)  in bnx2_reset_nic()  argument
5523 	rc = bnx2_reset_chip(bp, reset_code);  in bnx2_reset_nic()
5524 	bnx2_free_skbs(bp);  in bnx2_reset_nic()
5528 	if ((rc = bnx2_init_chip(bp)) != 0)  in bnx2_reset_nic()
5531 	bnx2_init_all_rings(bp);  in bnx2_reset_nic()
5536 bnx2_init_nic(struct bnx2 *bp, int reset_phy)  in bnx2_init_nic()  argument
5540 	if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)  in bnx2_init_nic()
5543 	spin_lock_bh(&bp->phy_lock);  in bnx2_init_nic()
5544 	bnx2_init_phy(bp, reset_phy);  in bnx2_init_nic()
5545 	bnx2_set_link(bp);  in bnx2_init_nic()
5546 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_init_nic()
5547 		bnx2_remote_phy_event(bp);  in bnx2_init_nic()
5548 	spin_unlock_bh(&bp->phy_lock);  in bnx2_init_nic()
5553 bnx2_shutdown_chip(struct bnx2 *bp)  in bnx2_shutdown_chip()  argument
5557 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_shutdown_chip()
5559 	else if (bp->wol)  in bnx2_shutdown_chip()
5564 	return bnx2_reset_chip(bp, reset_code);  in bnx2_shutdown_chip()
5568 bnx2_test_registers(struct bnx2 *bp)  in bnx2_test_registers()  argument
5689 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_registers()
5703 		save_val = readl(bp->regview + offset);  in bnx2_test_registers()
5705 		writel(0, bp->regview + offset);  in bnx2_test_registers()
5707 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5716 		writel(0xffffffff, bp->regview + offset);  in bnx2_test_registers()
5718 		val = readl(bp->regview + offset);  in bnx2_test_registers()
5727 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5731 		writel(save_val, bp->regview + offset);  in bnx2_test_registers()
5739 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)  in bnx2_do_mem_test()  argument
5750 			bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);  in bnx2_do_mem_test()
5752 			if (bnx2_reg_rd_ind(bp, start + offset) !=  in bnx2_do_mem_test()
5762 bnx2_test_memory(struct bnx2 *bp)  in bnx2_test_memory()  argument
5788 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_test_memory()
5794 		if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,  in bnx2_test_memory()
5807 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)  in bnx2_run_loopback()  argument
5819 	struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;  in bnx2_run_loopback()
5828 		bp->loopback = MAC_LOOPBACK;  in bnx2_run_loopback()
5829 		bnx2_set_mac_loopback(bp);  in bnx2_run_loopback()
5832 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_run_loopback()
5835 		bp->loopback = PHY_LOOPBACK;  in bnx2_run_loopback()
5836 		bnx2_set_phy_loopback(bp);  in bnx2_run_loopback()
5841 	pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);  in bnx2_run_loopback()
5842 	skb = netdev_alloc_skb(bp->dev, pkt_size);  in bnx2_run_loopback()
5846 	memcpy(packet, bp->dev->dev_addr, ETH_ALEN);  in bnx2_run_loopback()
5851 	map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,  in bnx2_run_loopback()
5853 	if (dma_mapping_error(&bp->pdev->dev, map)) {  in bnx2_run_loopback()
5858 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5859 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5861 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5879 	BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);  in bnx2_run_loopback()
5880 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_run_loopback()
5884 	BNX2_WR(bp, BNX2_HC_COMMAND,  in bnx2_run_loopback()
5885 		bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);  in bnx2_run_loopback()
5887 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_run_loopback()
5891 	dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);  in bnx2_run_loopback()
5908 	dma_sync_single_for_cpu(&bp->pdev->dev,  in bnx2_run_loopback()
5910 		bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);  in bnx2_run_loopback()
5935 	bp->loopback = 0;  in bnx2_run_loopback()
5945 bnx2_test_loopback(struct bnx2 *bp)  in bnx2_test_loopback()  argument
5949 	if (!netif_running(bp->dev))  in bnx2_test_loopback()
5952 	bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_test_loopback()
5953 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5954 	bnx2_init_phy(bp, 1);  in bnx2_test_loopback()
5955 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_loopback()
5956 	if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))  in bnx2_test_loopback()
5958 	if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))  in bnx2_test_loopback()
5967 bnx2_test_nvram(struct bnx2 *bp)  in bnx2_test_nvram()  argument
5974 	if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)  in bnx2_test_nvram()
5983 	if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)  in bnx2_test_nvram()
6002 bnx2_test_link(struct bnx2 *bp)  in bnx2_test_link()  argument
6006 	if (!netif_running(bp->dev))  in bnx2_test_link()
6009 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_test_link()
6010 		if (bp->link_up)  in bnx2_test_link()
6014 	spin_lock_bh(&bp->phy_lock);  in bnx2_test_link()
6015 	bnx2_enable_bmsr1(bp);  in bnx2_test_link()
6016 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
6017 	bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);  in bnx2_test_link()
6018 	bnx2_disable_bmsr1(bp);  in bnx2_test_link()
6019 	spin_unlock_bh(&bp->phy_lock);  in bnx2_test_link()
6028 bnx2_test_intr(struct bnx2 *bp)  in bnx2_test_intr()  argument
6033 	if (!netif_running(bp->dev))  in bnx2_test_intr()
6036 	status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;  in bnx2_test_intr()
6039 	BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);  in bnx2_test_intr()
6040 	BNX2_RD(bp, BNX2_HC_COMMAND);  in bnx2_test_intr()
6043 		if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=  in bnx2_test_intr()
6059 bnx2_5706_serdes_has_link(struct bnx2 *bp)  in bnx2_5706_serdes_has_link()  argument
6063 	if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)  in bnx2_5706_serdes_has_link()
6066 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);  in bnx2_5706_serdes_has_link()
6067 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);  in bnx2_5706_serdes_has_link()
6072 	bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_has_link()
6073 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6074 	bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);  in bnx2_5706_serdes_has_link()
6079 	bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);  in bnx2_5706_serdes_has_link()
6080 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6081 	bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);  in bnx2_5706_serdes_has_link()
6090 bnx2_5706_serdes_timer(struct bnx2 *bp)  in bnx2_5706_serdes_timer()  argument
6094 	spin_lock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6095 	if (bp->serdes_an_pending) {  in bnx2_5706_serdes_timer()
6096 		bp->serdes_an_pending--;  in bnx2_5706_serdes_timer()
6098 	} else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5706_serdes_timer()
6101 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6103 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6106 			if (bnx2_5706_serdes_has_link(bp)) {  in bnx2_5706_serdes_timer()
6109 				bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6110 				bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6114 	else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&  in bnx2_5706_serdes_timer()
6115 		 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {  in bnx2_5706_serdes_timer()
6118 		bnx2_write_phy(bp, 0x17, 0x0f01);  in bnx2_5706_serdes_timer()
6119 		bnx2_read_phy(bp, 0x15, &phy2);  in bnx2_5706_serdes_timer()
6123 			bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5706_serdes_timer()
6125 			bnx2_write_phy(bp, bp->mii_bmcr, bmcr);  in bnx2_5706_serdes_timer()
6127 			bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;  in bnx2_5706_serdes_timer()
6130 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5706_serdes_timer()
6135 		bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);  in bnx2_5706_serdes_timer()
6136 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6137 		bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);  in bnx2_5706_serdes_timer()
6139 		if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {  in bnx2_5706_serdes_timer()
6140 			if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {  in bnx2_5706_serdes_timer()
6141 				bnx2_5706s_force_link_dn(bp, 1);  in bnx2_5706_serdes_timer()
6142 				bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;  in bnx2_5706_serdes_timer()
6144 				bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6145 		} else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))  in bnx2_5706_serdes_timer()
6146 			bnx2_set_link(bp);  in bnx2_5706_serdes_timer()
6148 	spin_unlock(&bp->phy_lock);  in bnx2_5706_serdes_timer()
6152 bnx2_5708_serdes_timer(struct bnx2 *bp)  in bnx2_5708_serdes_timer()  argument
6154 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_5708_serdes_timer()
6157 	if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {  in bnx2_5708_serdes_timer()
6158 		bp->serdes_an_pending = 0;  in bnx2_5708_serdes_timer()
6162 	spin_lock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6163 	if (bp->serdes_an_pending)  in bnx2_5708_serdes_timer()
6164 		bp->serdes_an_pending--;  in bnx2_5708_serdes_timer()
6165 	else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {  in bnx2_5708_serdes_timer()
6168 		bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_5708_serdes_timer()
6170 			bnx2_enable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6171 			bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;  in bnx2_5708_serdes_timer()
6173 			bnx2_disable_forced_2g5(bp);  in bnx2_5708_serdes_timer()
6174 			bp->serdes_an_pending = 2;  in bnx2_5708_serdes_timer()
6175 			bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6179 		bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_5708_serdes_timer()
6181 	spin_unlock(&bp->phy_lock);  in bnx2_5708_serdes_timer()
6187 	struct bnx2 *bp = from_timer(bp, t, timer);  in bnx2_timer()  local
6189 	if (!netif_running(bp->dev))  in bnx2_timer()
6192 	if (atomic_read(&bp->intr_sem) != 0)  in bnx2_timer()
6195 	if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==  in bnx2_timer()
6197 		bnx2_chk_missed_msi(bp);  in bnx2_timer()
6199 	bnx2_send_heart_beat(bp);  in bnx2_timer()
6201 	bp->stats_blk->stat_FwRxDrop =  in bnx2_timer()
6202 		bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);  in bnx2_timer()
6205 	if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)  in bnx2_timer()
6206 		BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |  in bnx2_timer()
6209 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_timer()
6210 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706)  in bnx2_timer()
6211 			bnx2_5706_serdes_timer(bp);  in bnx2_timer()
6213 			bnx2_5708_serdes_timer(bp);  in bnx2_timer()
6217 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_timer()
6221 bnx2_request_irq(struct bnx2 *bp)  in bnx2_request_irq()  argument
6227 	if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)  in bnx2_request_irq()
6232 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_request_irq()
6233 		irq = &bp->irq_tbl[i];  in bnx2_request_irq()
6235 				 &bp->bnx2_napi[i]);  in bnx2_request_irq()
6244 __bnx2_free_irq(struct bnx2 *bp)  in __bnx2_free_irq()  argument
6249 	for (i = 0; i < bp->irq_nvecs; i++) {  in __bnx2_free_irq()
6250 		irq = &bp->irq_tbl[i];  in __bnx2_free_irq()
6252 			free_irq(irq->vector, &bp->bnx2_napi[i]);  in __bnx2_free_irq()
6258 bnx2_free_irq(struct bnx2 *bp)  in bnx2_free_irq()  argument
6261 	__bnx2_free_irq(bp);  in bnx2_free_irq()
6262 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_free_irq()
6263 		pci_disable_msi(bp->pdev);  in bnx2_free_irq()
6264 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_free_irq()
6265 		pci_disable_msix(bp->pdev);  in bnx2_free_irq()
6267 	bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);  in bnx2_free_irq()
6271 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)  in bnx2_enable_msix()  argument
6275 	struct net_device *dev = bp->dev;  in bnx2_enable_msix()
6276 	const int len = sizeof(bp->irq_tbl[0].name);  in bnx2_enable_msix()
6278 	bnx2_setup_msix_tbl(bp);  in bnx2_enable_msix()
6279 	BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);  in bnx2_enable_msix()
6280 	BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);  in bnx2_enable_msix()
6281 	BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);  in bnx2_enable_msix()
6285 	BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);  in bnx2_enable_msix()
6296 	total_vecs = pci_enable_msix_range(bp->pdev, msix_ent,  in bnx2_enable_msix()
6305 	bp->irq_nvecs = msix_vecs;  in bnx2_enable_msix()
6306 	bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_enable_msix()
6308 		bp->irq_tbl[i].vector = msix_ent[i].vector;  in bnx2_enable_msix()
6309 		snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);  in bnx2_enable_msix()
6310 		bp->irq_tbl[i].handler = bnx2_msi_1shot;  in bnx2_enable_msix()
6315 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)  in bnx2_setup_int_mode()  argument
6320 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6321 		msix_vecs = max(cpus + 1, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6322 	else if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6323 		msix_vecs = max(cpus, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6325 		msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6329 	bp->irq_tbl[0].handler = bnx2_interrupt;  in bnx2_setup_int_mode()
6330 	strcpy(bp->irq_tbl[0].name, bp->dev->name);  in bnx2_setup_int_mode()
6331 	bp->irq_nvecs = 1;  in bnx2_setup_int_mode()
6332 	bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6334 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)  in bnx2_setup_int_mode()
6335 		bnx2_enable_msix(bp, msix_vecs);  in bnx2_setup_int_mode()
6337 	if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&  in bnx2_setup_int_mode()
6338 	    !(bp->flags & BNX2_FLAG_USING_MSIX)) {  in bnx2_setup_int_mode()
6339 		if (pci_enable_msi(bp->pdev) == 0) {  in bnx2_setup_int_mode()
6340 			bp->flags |= BNX2_FLAG_USING_MSI;  in bnx2_setup_int_mode()
6341 			if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_setup_int_mode()
6342 				bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;  in bnx2_setup_int_mode()
6343 				bp->irq_tbl[0].handler = bnx2_msi_1shot;  in bnx2_setup_int_mode()
6345 				bp->irq_tbl[0].handler = bnx2_msi;  in bnx2_setup_int_mode()
6347 			bp->irq_tbl[0].vector = bp->pdev->irq;  in bnx2_setup_int_mode()
6351 	if (!bp->num_req_tx_rings)  in bnx2_setup_int_mode()
6352 		bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);  in bnx2_setup_int_mode()
6354 		bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);  in bnx2_setup_int_mode()
6356 	if (!bp->num_req_rx_rings)  in bnx2_setup_int_mode()
6357 		bp->num_rx_rings = bp->irq_nvecs;  in bnx2_setup_int_mode()
6359 		bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);  in bnx2_setup_int_mode()
6361 	netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);  in bnx2_setup_int_mode()
6363 	return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);  in bnx2_setup_int_mode()
6370 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_open()  local
6373 	rc = bnx2_request_firmware(bp);  in bnx2_open()
6379 	bnx2_disable_int(bp);  in bnx2_open()
6381 	rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_open()
6384 	bnx2_init_napi(bp);  in bnx2_open()
6385 	bnx2_napi_enable(bp);  in bnx2_open()
6386 	rc = bnx2_alloc_mem(bp);  in bnx2_open()
6390 	rc = bnx2_request_irq(bp);  in bnx2_open()
6394 	rc = bnx2_init_nic(bp, 1);  in bnx2_open()
6398 	mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_open()
6400 	atomic_set(&bp->intr_sem, 0);  in bnx2_open()
6402 	memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));  in bnx2_open()
6404 	bnx2_enable_int(bp);  in bnx2_open()
6406 	if (bp->flags & BNX2_FLAG_USING_MSI) {  in bnx2_open()
6410 		if (bnx2_test_intr(bp) != 0) {  in bnx2_open()
6411 …netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report …  in bnx2_open()
6413 			bnx2_disable_int(bp);  in bnx2_open()
6414 			bnx2_free_irq(bp);  in bnx2_open()
6416 			bnx2_setup_int_mode(bp, 1);  in bnx2_open()
6418 			rc = bnx2_init_nic(bp, 0);  in bnx2_open()
6421 				rc = bnx2_request_irq(bp);  in bnx2_open()
6424 				del_timer_sync(&bp->timer);  in bnx2_open()
6427 			bnx2_enable_int(bp);  in bnx2_open()
6430 	if (bp->flags & BNX2_FLAG_USING_MSI)  in bnx2_open()
6432 	else if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_open()
6440 	bnx2_napi_disable(bp);  in bnx2_open()
6441 	bnx2_free_skbs(bp);  in bnx2_open()
6442 	bnx2_free_irq(bp);  in bnx2_open()
6443 	bnx2_free_mem(bp);  in bnx2_open()
6444 	bnx2_del_napi(bp);  in bnx2_open()
6445 	bnx2_release_firmware(bp);  in bnx2_open()
6452 	struct bnx2 *bp = container_of(work, struct bnx2, reset_task);  in bnx2_reset_task()  local
6457 	if (!netif_running(bp->dev)) {  in bnx2_reset_task()
6462 	bnx2_netif_stop(bp, true);  in bnx2_reset_task()
6464 	pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);  in bnx2_reset_task()
6467 		pci_restore_state(bp->pdev);  in bnx2_reset_task()
6468 		pci_save_state(bp->pdev);  in bnx2_reset_task()
6470 	rc = bnx2_init_nic(bp, 1);  in bnx2_reset_task()
6472 		netdev_err(bp->dev, "failed to reset NIC, closing\n");  in bnx2_reset_task()
6473 		bnx2_napi_enable(bp);  in bnx2_reset_task()
6474 		dev_close(bp->dev);  in bnx2_reset_task()
6479 	atomic_set(&bp->intr_sem, 1);  in bnx2_reset_task()
6480 	bnx2_netif_start(bp, true);  in bnx2_reset_task()
6487 bnx2_dump_ftq(struct bnx2 *bp)  in bnx2_dump_ftq()  argument
6491 	struct net_device *dev = bp->dev;  in bnx2_dump_ftq()
6515 			   bnx2_reg_rd_ind(bp, ftq_arr[i].off));  in bnx2_dump_ftq()
6520 			   reg, bnx2_reg_rd_ind(bp, reg),  in bnx2_dump_ftq()
6521 			   bnx2_reg_rd_ind(bp, reg + 4),  in bnx2_dump_ftq()
6522 			   bnx2_reg_rd_ind(bp, reg + 8),  in bnx2_dump_ftq()
6523 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6524 			   bnx2_reg_rd_ind(bp, reg + 0x1c),  in bnx2_dump_ftq()
6525 			   bnx2_reg_rd_ind(bp, reg + 0x20));  in bnx2_dump_ftq()
6530 		   BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);  in bnx2_dump_ftq()
6535 		BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);  in bnx2_dump_ftq()
6536 		BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,  in bnx2_dump_ftq()
6538 		BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);  in bnx2_dump_ftq()
6539 		while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &  in bnx2_dump_ftq()
6543 		cid = BNX2_RD(bp, BNX2_TBDC_CID);  in bnx2_dump_ftq()
6544 		bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);  in bnx2_dump_ftq()
6545 		valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);  in bnx2_dump_ftq()
6554 bnx2_dump_state(struct bnx2 *bp)  in bnx2_dump_state()  argument
6556 	struct net_device *dev = bp->dev;  in bnx2_dump_state()
6559 	pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);  in bnx2_dump_state()
6561 		   atomic_read(&bp->intr_sem), val1);  in bnx2_dump_state()
6562 	pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);  in bnx2_dump_state()
6563 	pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);  in bnx2_dump_state()
6566 		   BNX2_RD(bp, BNX2_EMAC_TX_STATUS),  in bnx2_dump_state()
6567 		   BNX2_RD(bp, BNX2_EMAC_RX_STATUS));  in bnx2_dump_state()
6569 		   BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));  in bnx2_dump_state()
6571 		   BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));  in bnx2_dump_state()
6572 	if (bp->flags & BNX2_FLAG_USING_MSIX)  in bnx2_dump_state()
6574 			   BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));  in bnx2_dump_state()
6580 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_tx_timeout()  local
6582 	bnx2_dump_ftq(bp);  in bnx2_tx_timeout()
6583 	bnx2_dump_state(bp);  in bnx2_tx_timeout()
6584 	bnx2_dump_mcp_state(bp);  in bnx2_tx_timeout()
6587 	schedule_work(&bp->reset_task);  in bnx2_tx_timeout()
6597 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_start_xmit()  local
6610 	bnapi = &bp->bnx2_napi[i];  in bnx2_start_xmit()
6614 	if (unlikely(bnx2_tx_avail(bp, txr) <  in bnx2_start_xmit()
6669 	mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);  in bnx2_start_xmit()
6670 	if (dma_mapping_error(&bp->pdev->dev, mapping)) {  in bnx2_start_xmit()
6698 		mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,  in bnx2_start_xmit()
6700 		if (dma_mapping_error(&bp->pdev->dev, mapping))  in bnx2_start_xmit()
6721 	BNX2_WR16(bp, txr->tx_bidx_addr, prod);  in bnx2_start_xmit()
6722 	BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);  in bnx2_start_xmit()
6726 	if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {  in bnx2_start_xmit()
6735 		if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)  in bnx2_start_xmit()
6749 	dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6757 		dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),  in bnx2_start_xmit()
6770 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_close()  local
6772 	bnx2_disable_int_sync(bp);  in bnx2_close()
6773 	bnx2_napi_disable(bp);  in bnx2_close()
6775 	del_timer_sync(&bp->timer);  in bnx2_close()
6776 	bnx2_shutdown_chip(bp);  in bnx2_close()
6777 	bnx2_free_irq(bp);  in bnx2_close()
6778 	bnx2_free_skbs(bp);  in bnx2_close()
6779 	bnx2_free_mem(bp);  in bnx2_close()
6780 	bnx2_del_napi(bp);  in bnx2_close()
6781 	bp->link_up = 0;  in bnx2_close()
6782 	netif_carrier_off(bp->dev);  in bnx2_close()
6787 bnx2_save_stats(struct bnx2 *bp)  in bnx2_save_stats()  argument
6789 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_save_stats()
6790 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_save_stats()
6814 	GET_64BIT_NET_STATS64(bp->stats_blk->ctr) +		\
6815 	GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6818 	(unsigned long) (bp->stats_blk->ctr +			\
6819 			 bp->temp_stats_blk->ctr)
6824 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_stats64()  local
6826 	if (!bp->stats_blk)  in bnx2_get_stats64()
6873 	if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||  in bnx2_get_stats64()
6874 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_stats64()
6899 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link_ksettings()  local
6904 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_get_link_ksettings()
6907 	} else if (bp->phy_port == PORT_FIBRE)  in bnx2_get_link_ksettings()
6915 		if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)  in bnx2_get_link_ksettings()
6927 	spin_lock_bh(&bp->phy_lock);  in bnx2_get_link_ksettings()
6928 	cmd->base.port = bp->phy_port;  in bnx2_get_link_ksettings()
6929 	advertising = bp->advertising;  in bnx2_get_link_ksettings()
6931 	if (bp->autoneg & AUTONEG_SPEED) {  in bnx2_get_link_ksettings()
6938 		cmd->base.speed = bp->line_speed;  in bnx2_get_link_ksettings()
6939 		cmd->base.duplex = bp->duplex;  in bnx2_get_link_ksettings()
6940 		if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) {  in bnx2_get_link_ksettings()
6941 			if (bp->phy_flags & BNX2_PHY_FLAG_MDIX)  in bnx2_get_link_ksettings()
6951 	spin_unlock_bh(&bp->phy_lock);  in bnx2_get_link_ksettings()
6953 	cmd->base.phy_address = bp->phy_addr;  in bnx2_get_link_ksettings()
6967 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_link_ksettings()  local
6968 	u8 autoneg = bp->autoneg;  in bnx2_set_link_ksettings()
6969 	u8 req_duplex = bp->req_duplex;  in bnx2_set_link_ksettings()
6970 	u16 req_line_speed = bp->req_line_speed;  in bnx2_set_link_ksettings()
6971 	u32 advertising = bp->advertising;  in bnx2_set_link_ksettings()
6974 	spin_lock_bh(&bp->phy_lock);  in bnx2_set_link_ksettings()
6979 	if (cmd->base.port != bp->phy_port &&  in bnx2_set_link_ksettings()
6980 	    !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))  in bnx2_set_link_ksettings()
6986 	if (!netif_running(dev) && cmd->base.port != bp->phy_port)  in bnx2_set_link_ksettings()
7016 			    !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))  in bnx2_set_link_ksettings()
7027 	bp->autoneg = autoneg;  in bnx2_set_link_ksettings()
7028 	bp->advertising = advertising;  in bnx2_set_link_ksettings()
7029 	bp->req_line_speed = req_line_speed;  in bnx2_set_link_ksettings()
7030 	bp->req_duplex = req_duplex;  in bnx2_set_link_ksettings()
7037 		err = bnx2_setup_phy(bp, cmd->base.port);  in bnx2_set_link_ksettings()
7040 	spin_unlock_bh(&bp->phy_lock);  in bnx2_set_link_ksettings()
7048 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_drvinfo()  local
7052 	strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));  in bnx2_get_drvinfo()
7053 	strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));  in bnx2_get_drvinfo()
7069 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_regs()  local
7099 	if (!netif_running(bp->dev))  in bnx2_get_regs()
7106 		*p++ = BNX2_RD(bp, offset);  in bnx2_get_regs()
7119 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_wol()  local
7121 	if (bp->flags & BNX2_FLAG_NO_WOL) {  in bnx2_get_wol()
7127 		if (bp->wol)  in bnx2_get_wol()
7138 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_wol()  local
7144 		if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_set_wol()
7147 		bp->wol = 1;  in bnx2_set_wol()
7150 		bp->wol = 0;  in bnx2_set_wol()
7153 	device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_set_wol()
7161 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_nway_reset()  local
7167 	if (!(bp->autoneg & AUTONEG_SPEED)) {  in bnx2_nway_reset()
7171 	spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7173 	if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {  in bnx2_nway_reset()
7176 		rc = bnx2_setup_remote_phy(bp, bp->phy_port);  in bnx2_nway_reset()
7177 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7182 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_nway_reset()
7183 		bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);  in bnx2_nway_reset()
7184 		spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7188 		spin_lock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7190 		bp->current_interval = BNX2_SERDES_AN_TIMEOUT;  in bnx2_nway_reset()
7191 		bp->serdes_an_pending = 1;  in bnx2_nway_reset()
7192 		mod_timer(&bp->timer, jiffies + bp->current_interval);  in bnx2_nway_reset()
7195 	bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);  in bnx2_nway_reset()
7197 	bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);  in bnx2_nway_reset()
7199 	spin_unlock_bh(&bp->phy_lock);  in bnx2_nway_reset()
7207 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_link()  local
7209 	return bp->link_up;  in bnx2_get_link()
7215 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom_len()  local
7217 	if (!bp->flash_info)  in bnx2_get_eeprom_len()
7220 	return (int) bp->flash_size;  in bnx2_get_eeprom_len()
7227 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_eeprom()  local
7232 	rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_get_eeprom()
7241 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_eeprom()  local
7246 	rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);  in bnx2_set_eeprom()
7254 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_coalesce()  local
7258 	coal->rx_coalesce_usecs = bp->rx_ticks;  in bnx2_get_coalesce()
7259 	coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;  in bnx2_get_coalesce()
7260 	coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;  in bnx2_get_coalesce()
7261 	coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;  in bnx2_get_coalesce()
7263 	coal->tx_coalesce_usecs = bp->tx_ticks;  in bnx2_get_coalesce()
7264 	coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;  in bnx2_get_coalesce()
7265 	coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;  in bnx2_get_coalesce()
7266 	coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;  in bnx2_get_coalesce()
7268 	coal->stats_block_coalesce_usecs = bp->stats_ticks;  in bnx2_get_coalesce()
7276 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_coalesce()  local
7278 	bp->rx_ticks = (u16) coal->rx_coalesce_usecs;  in bnx2_set_coalesce()
7279 	if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;  in bnx2_set_coalesce()
7281 	bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;  in bnx2_set_coalesce()
7282 	if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7284 	bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7285 	if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7287 	bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7288 	if (bp->rx_quick_cons_trip_int > 0xff)  in bnx2_set_coalesce()
7289 		bp->rx_quick_cons_trip_int = 0xff;  in bnx2_set_coalesce()
7291 	bp->tx_ticks = (u16) coal->tx_coalesce_usecs;  in bnx2_set_coalesce()
7292 	if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;  in bnx2_set_coalesce()
7294 	bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;  in bnx2_set_coalesce()
7295 	if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;  in bnx2_set_coalesce()
7297 	bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;  in bnx2_set_coalesce()
7298 	if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;  in bnx2_set_coalesce()
7300 	bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;  in bnx2_set_coalesce()
7301 	if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =  in bnx2_set_coalesce()
7304 	bp->stats_ticks = coal->stats_block_coalesce_usecs;  in bnx2_set_coalesce()
7305 	if (bp->flags & BNX2_FLAG_BROKEN_STATS) {  in bnx2_set_coalesce()
7306 		if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)  in bnx2_set_coalesce()
7307 			bp->stats_ticks = USEC_PER_SEC;  in bnx2_set_coalesce()
7309 	if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)  in bnx2_set_coalesce()
7310 		bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7311 	bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_set_coalesce()
7313 	if (netif_running(bp->dev)) {  in bnx2_set_coalesce()
7314 		bnx2_netif_stop(bp, true);  in bnx2_set_coalesce()
7315 		bnx2_init_nic(bp, 0);  in bnx2_set_coalesce()
7316 		bnx2_netif_start(bp, true);  in bnx2_set_coalesce()
7325 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ringparam()  local
7330 	ering->rx_pending = bp->rx_ring_size;  in bnx2_get_ringparam()
7331 	ering->rx_jumbo_pending = bp->rx_pg_ring_size;  in bnx2_get_ringparam()
7334 	ering->tx_pending = bp->tx_ring_size;  in bnx2_get_ringparam()
7338 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)  in bnx2_change_ring_size()  argument
7340 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7342 		bnx2_save_stats(bp);  in bnx2_change_ring_size()
7344 		bnx2_netif_stop(bp, true);  in bnx2_change_ring_size()
7345 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_change_ring_size()
7347 			bnx2_free_irq(bp);  in bnx2_change_ring_size()
7348 			bnx2_del_napi(bp);  in bnx2_change_ring_size()
7350 			__bnx2_free_irq(bp);  in bnx2_change_ring_size()
7352 		bnx2_free_skbs(bp);  in bnx2_change_ring_size()
7353 		bnx2_free_mem(bp);  in bnx2_change_ring_size()
7356 	bnx2_set_rx_ring_size(bp, rx);  in bnx2_change_ring_size()
7357 	bp->tx_ring_size = tx;  in bnx2_change_ring_size()
7359 	if (netif_running(bp->dev)) {  in bnx2_change_ring_size()
7363 			rc = bnx2_setup_int_mode(bp, disable_msi);  in bnx2_change_ring_size()
7364 			bnx2_init_napi(bp);  in bnx2_change_ring_size()
7368 			rc = bnx2_alloc_mem(bp);  in bnx2_change_ring_size()
7371 			rc = bnx2_request_irq(bp);  in bnx2_change_ring_size()
7374 			rc = bnx2_init_nic(bp, 0);  in bnx2_change_ring_size()
7377 			bnx2_napi_enable(bp);  in bnx2_change_ring_size()
7378 			dev_close(bp->dev);  in bnx2_change_ring_size()
7382 		mutex_lock(&bp->cnic_lock);  in bnx2_change_ring_size()
7384 		if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)  in bnx2_change_ring_size()
7385 			bnx2_setup_cnic_irq_info(bp);  in bnx2_change_ring_size()
7386 		mutex_unlock(&bp->cnic_lock);  in bnx2_change_ring_size()
7388 		bnx2_netif_start(bp, true);  in bnx2_change_ring_size()
7396 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_ringparam()  local
7405 	rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,  in bnx2_set_ringparam()
7413 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_pauseparam()  local
7415 	epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);  in bnx2_get_pauseparam()
7416 	epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);  in bnx2_get_pauseparam()
7417 	epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);  in bnx2_get_pauseparam()
7423 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_pauseparam()  local
7425 	bp->req_flow_ctrl = 0;  in bnx2_set_pauseparam()
7427 		bp->req_flow_ctrl |= FLOW_CTRL_RX;  in bnx2_set_pauseparam()
7429 		bp->req_flow_ctrl |= FLOW_CTRL_TX;  in bnx2_set_pauseparam()
7432 		bp->autoneg |= AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7435 		bp->autoneg &= ~AUTONEG_FLOW_CTRL;  in bnx2_set_pauseparam()
7439 		spin_lock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7440 		bnx2_setup_phy(bp, bp->phy_port);  in bnx2_set_pauseparam()
7441 		spin_unlock_bh(&bp->phy_lock);  in bnx2_set_pauseparam()
7601 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_self_test()  local
7607 		bnx2_netif_stop(bp, true);  in bnx2_self_test()
7608 		bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);  in bnx2_self_test()
7609 		bnx2_free_skbs(bp);  in bnx2_self_test()
7611 		if (bnx2_test_registers(bp) != 0) {  in bnx2_self_test()
7615 		if (bnx2_test_memory(bp) != 0) {  in bnx2_self_test()
7619 		if ((buf[2] = bnx2_test_loopback(bp)) != 0)  in bnx2_self_test()
7622 		if (!netif_running(bp->dev))  in bnx2_self_test()
7623 			bnx2_shutdown_chip(bp);  in bnx2_self_test()
7625 			bnx2_init_nic(bp, 1);  in bnx2_self_test()
7626 			bnx2_netif_start(bp, true);  in bnx2_self_test()
7631 			if (bp->link_up)  in bnx2_self_test()
7637 	if (bnx2_test_nvram(bp) != 0) {  in bnx2_self_test()
7641 	if (bnx2_test_intr(bp) != 0) {  in bnx2_self_test()
7646 	if (bnx2_test_link(bp) != 0) {  in bnx2_self_test()
7672 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_ethtool_stats()  local
7674 	u32 *hw_stats = (u32 *) bp->stats_blk;  in bnx2_get_ethtool_stats()
7675 	u32 *temp_stats = (u32 *) bp->temp_stats_blk;  in bnx2_get_ethtool_stats()
7683 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||  in bnx2_get_ethtool_stats()
7684 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||  in bnx2_get_ethtool_stats()
7685 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||  in bnx2_get_ethtool_stats()
7686 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))  in bnx2_get_ethtool_stats()
7718 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_phys_id()  local
7722 		bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);  in bnx2_set_phys_id()
7723 		BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);  in bnx2_set_phys_id()
7727 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |  in bnx2_set_phys_id()
7736 		BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);  in bnx2_set_phys_id()
7740 		BNX2_WR(bp, BNX2_EMAC_LED, 0);  in bnx2_set_phys_id()
7741 		BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);  in bnx2_set_phys_id()
7751 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_features()  local
7760 	    !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&  in bnx2_set_features()
7762 		bnx2_netif_stop(bp, false);  in bnx2_set_features()
7765 		bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);  in bnx2_set_features()
7766 		bnx2_netif_start(bp, false);  in bnx2_set_features()
7776 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_get_channels()  local
7780 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_get_channels()
7789 	channels->rx_count = bp->num_rx_rings;  in bnx2_get_channels()
7790 	channels->tx_count = bp->num_tx_rings;  in bnx2_get_channels()
7798 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_set_channels()  local
7803 	if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {  in bnx2_set_channels()
7811 	bp->num_req_rx_rings = channels->rx_count;  in bnx2_set_channels()
7812 	bp->num_req_tx_rings = channels->tx_count;  in bnx2_set_channels()
7815 		rc = bnx2_change_ring_size(bp, bp->rx_ring_size,  in bnx2_set_channels()
7816 					   bp->tx_ring_size, true);  in bnx2_set_channels()
7854 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_ioctl()  local
7859 		data->phy_id = bp->phy_addr;  in bnx2_ioctl()
7865 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7871 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7872 		err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);  in bnx2_ioctl()
7873 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7881 		if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)  in bnx2_ioctl()
7887 		spin_lock_bh(&bp->phy_lock);  in bnx2_ioctl()
7888 		err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);  in bnx2_ioctl()
7889 		spin_unlock_bh(&bp->phy_lock);  in bnx2_ioctl()
7905 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mac_addr()  local
7912 		bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);  in bnx2_change_mac_addr()
7921 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_change_mtu()  local
7924 	return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,  in bnx2_change_mtu()
7932 	struct bnx2 *bp = netdev_priv(dev);  in poll_bnx2()  local
7935 	for (i = 0; i < bp->irq_nvecs; i++) {  in poll_bnx2()
7936 		struct bnx2_irq *irq = &bp->irq_tbl[i];  in poll_bnx2()
7939 		irq->handler(irq->vector, &bp->bnx2_napi[i]);  in poll_bnx2()
7946 bnx2_get_5709_media(struct bnx2 *bp)  in bnx2_get_5709_media()  argument
7948 	u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);  in bnx2_get_5709_media()
7955 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7964 	if (bp->func == 0) {  in bnx2_get_5709_media()
7969 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7977 			bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_get_5709_media()
7984 bnx2_get_pci_speed(struct bnx2 *bp)  in bnx2_get_pci_speed()  argument
7988 	reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);  in bnx2_get_pci_speed()
7992 		bp->flags |= BNX2_FLAG_PCIX;  in bnx2_get_pci_speed()
7994 		clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);  in bnx2_get_pci_speed()
7999 			bp->bus_speed_mhz = 133;  in bnx2_get_pci_speed()
8003 			bp->bus_speed_mhz = 100;  in bnx2_get_pci_speed()
8008 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8013 			bp->bus_speed_mhz = 50;  in bnx2_get_pci_speed()
8019 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8025 			bp->bus_speed_mhz = 66;  in bnx2_get_pci_speed()
8027 			bp->bus_speed_mhz = 33;  in bnx2_get_pci_speed()
8031 		bp->flags |= BNX2_FLAG_PCI_32BIT;  in bnx2_get_pci_speed()
8036 bnx2_read_vpd_fw_ver(struct bnx2 *bp)  in bnx2_read_vpd_fw_ver()  argument
8050 	rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,  in bnx2_read_vpd_fw_ver()
8096 	memcpy(bp->fw_version, &data[j], len);  in bnx2_read_vpd_fw_ver()
8097 	bp->fw_version[len] = ' ';  in bnx2_read_vpd_fw_ver()
8106 	struct bnx2 *bp;  in bnx2_init_board()  local
8113 	bp = netdev_priv(dev);  in bnx2_init_board()
8115 	bp->flags = 0;  in bnx2_init_board()
8116 	bp->phy_flags = 0;  in bnx2_init_board()
8118 	bp->temp_stats_blk =  in bnx2_init_board()
8121 	if (!bp->temp_stats_blk) {  in bnx2_init_board()
8148 	bp->pm_cap = pdev->pm_cap;  in bnx2_init_board()
8149 	if (bp->pm_cap == 0) {  in bnx2_init_board()
8156 	bp->dev = dev;  in bnx2_init_board()
8157 	bp->pdev = pdev;  in bnx2_init_board()
8159 	spin_lock_init(&bp->phy_lock);  in bnx2_init_board()
8160 	spin_lock_init(&bp->indirect_lock);  in bnx2_init_board()
8162 	mutex_init(&bp->cnic_lock);  in bnx2_init_board()
8164 	INIT_WORK(&bp->reset_task, bnx2_reset_task);  in bnx2_init_board()
8166 	bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +  in bnx2_init_board()
8168 	if (!bp->regview) {  in bnx2_init_board()
8178 	BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,  in bnx2_init_board()
8182 	bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);  in bnx2_init_board()
8184 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {  in bnx2_init_board()
8190 		bp->flags |= BNX2_FLAG_PCIE;  in bnx2_init_board()
8191 		if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)  in bnx2_init_board()
8192 			bp->flags |= BNX2_FLAG_JUMBO_BROKEN;  in bnx2_init_board()
8197 			bp->flags |= BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8200 		bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);  in bnx2_init_board()
8201 		if (bp->pcix_cap == 0) {  in bnx2_init_board()
8207 		bp->flags |= BNX2_FLAG_BROKEN_STATS;  in bnx2_init_board()
8210 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8211 	    BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {  in bnx2_init_board()
8213 			bp->flags |= BNX2_FLAG_MSIX_CAP;  in bnx2_init_board()
8216 	if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&  in bnx2_init_board()
8217 	    BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {  in bnx2_init_board()
8219 			bp->flags |= BNX2_FLAG_MSI_CAP;  in bnx2_init_board()
8223 	if (BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8242 	if (!(bp->flags & BNX2_FLAG_PCIE))  in bnx2_init_board()
8243 		bnx2_get_pci_speed(bp);  in bnx2_init_board()
8246 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8247 		reg = BNX2_RD(bp, PCI_COMMAND);  in bnx2_init_board()
8249 		BNX2_WR(bp, PCI_COMMAND, reg);  in bnx2_init_board()
8250 	} else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&  in bnx2_init_board()
8251 		!(bp->flags & BNX2_FLAG_PCIX)) {  in bnx2_init_board()
8258 	bnx2_init_nvram(bp);  in bnx2_init_board()
8260 	reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);  in bnx2_init_board()
8262 	if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)  in bnx2_init_board()
8263 		bp->func = 1;  in bnx2_init_board()
8267 		u32 off = bp->func << 2;  in bnx2_init_board()
8269 		bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);  in bnx2_init_board()
8271 		bp->shmem_base = HOST_VIEW_SHMEM_BASE;  in bnx2_init_board()
8276 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);  in bnx2_init_board()
8285 	bnx2_read_vpd_fw_ver(bp);  in bnx2_init_board()
8287 	j = strlen(bp->fw_version);  in bnx2_init_board()
8288 	reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);  in bnx2_init_board()
8293 			bp->fw_version[j++] = 'b';  in bnx2_init_board()
8294 			bp->fw_version[j++] = 'c';  in bnx2_init_board()
8295 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8300 				bp->fw_version[j++] = (num / k) + '0';  in bnx2_init_board()
8305 			bp->fw_version[j++] = '.';  in bnx2_init_board()
8307 	reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);  in bnx2_init_board()
8309 		bp->wol = 1;  in bnx2_init_board()
8312 		bp->flags |= BNX2_FLAG_ASF_ENABLE;  in bnx2_init_board()
8315 			reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8321 	reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);  in bnx2_init_board()
8325 		u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);  in bnx2_init_board()
8328 			bp->fw_version[j++] = ' ';  in bnx2_init_board()
8330 			reg = bnx2_reg_rd_ind(bp, addr + i * 4);  in bnx2_init_board()
8332 			memcpy(&bp->fw_version[j], &reg, 4);  in bnx2_init_board()
8337 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);  in bnx2_init_board()
8338 	bp->mac_addr[0] = (u8) (reg >> 8);  in bnx2_init_board()
8339 	bp->mac_addr[1] = (u8) reg;  in bnx2_init_board()
8341 	reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);  in bnx2_init_board()
8342 	bp->mac_addr[2] = (u8) (reg >> 24);  in bnx2_init_board()
8343 	bp->mac_addr[3] = (u8) (reg >> 16);  in bnx2_init_board()
8344 	bp->mac_addr[4] = (u8) (reg >> 8);  in bnx2_init_board()
8345 	bp->mac_addr[5] = (u8) reg;  in bnx2_init_board()
8347 	bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;  in bnx2_init_board()
8348 	bnx2_set_rx_ring_size(bp, 255);  in bnx2_init_board()
8350 	bp->tx_quick_cons_trip_int = 2;  in bnx2_init_board()
8351 	bp->tx_quick_cons_trip = 20;  in bnx2_init_board()
8352 	bp->tx_ticks_int = 18;  in bnx2_init_board()
8353 	bp->tx_ticks = 80;  in bnx2_init_board()
8355 	bp->rx_quick_cons_trip_int = 2;  in bnx2_init_board()
8356 	bp->rx_quick_cons_trip = 12;  in bnx2_init_board()
8357 	bp->rx_ticks_int = 18;  in bnx2_init_board()
8358 	bp->rx_ticks = 18;  in bnx2_init_board()
8360 	bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;  in bnx2_init_board()
8362 	bp->current_interval = BNX2_TIMER_INTERVAL;  in bnx2_init_board()
8364 	bp->phy_addr = 1;  in bnx2_init_board()
8372 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_board()
8373 		bnx2_get_5709_media(bp);  in bnx2_init_board()
8374 	else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)  in bnx2_init_board()
8375 		bp->phy_flags |= BNX2_PHY_FLAG_SERDES;  in bnx2_init_board()
8377 	bp->phy_port = PORT_TP;  in bnx2_init_board()
8378 	if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {  in bnx2_init_board()
8379 		bp->phy_port = PORT_FIBRE;  in bnx2_init_board()
8380 		reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);  in bnx2_init_board()
8382 			bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8383 			bp->wol = 0;  in bnx2_init_board()
8385 		if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {  in bnx2_init_board()
8392 				bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;  in bnx2_init_board()
8394 			bp->phy_addr = 2;  in bnx2_init_board()
8396 				bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;  in bnx2_init_board()
8398 	} else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||  in bnx2_init_board()
8399 		   BNX2_CHIP(bp) == BNX2_CHIP_5708)  in bnx2_init_board()
8400 		bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;  in bnx2_init_board()
8401 	else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&  in bnx2_init_board()
8402 		 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||  in bnx2_init_board()
8403 		  BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))  in bnx2_init_board()
8404 		bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;  in bnx2_init_board()
8406 	bnx2_init_fw_cap(bp);  in bnx2_init_board()
8408 	if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||  in bnx2_init_board()
8409 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||  in bnx2_init_board()
8410 	    (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||  in bnx2_init_board()
8411 	    !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {  in bnx2_init_board()
8412 		bp->flags |= BNX2_FLAG_NO_WOL;  in bnx2_init_board()
8413 		bp->wol = 0;  in bnx2_init_board()
8416 	if (bp->flags & BNX2_FLAG_NO_WOL)  in bnx2_init_board()
8417 		device_set_wakeup_capable(&bp->pdev->dev, false);  in bnx2_init_board()
8419 		device_set_wakeup_enable(&bp->pdev->dev, bp->wol);  in bnx2_init_board()
8421 	if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {  in bnx2_init_board()
8422 		bp->tx_quick_cons_trip_int =  in bnx2_init_board()
8423 			bp->tx_quick_cons_trip;  in bnx2_init_board()
8424 		bp->tx_ticks_int = bp->tx_ticks;  in bnx2_init_board()
8425 		bp->rx_quick_cons_trip_int =  in bnx2_init_board()
8426 			bp->rx_quick_cons_trip;  in bnx2_init_board()
8427 		bp->rx_ticks_int = bp->rx_ticks;  in bnx2_init_board()
8428 		bp->comp_prod_trip_int = bp->comp_prod_trip;  in bnx2_init_board()
8429 		bp->com_ticks_int = bp->com_ticks;  in bnx2_init_board()
8430 		bp->cmd_ticks_int = bp->cmd_ticks;  in bnx2_init_board()
8443 	if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {  in bnx2_init_board()
8459 	bnx2_set_default_link(bp);  in bnx2_init_board()
8460 	bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in bnx2_init_board()
8462 	timer_setup(&bp->timer, bnx2_timer, 0);  in bnx2_init_board()
8463 	bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);  in bnx2_init_board()
8466 	if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)  in bnx2_init_board()
8467 		bp->cnic_eth_dev.max_iscsi_conn =  in bnx2_init_board()
8468 			(bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &  in bnx2_init_board()
8470 	bp->cnic_probe = bnx2_cnic_probe;  in bnx2_init_board()
8477 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_init_board()
8479 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_init_board()
8482 	pci_iounmap(pdev, bp->regview);  in bnx2_init_board()
8483 	bp->regview = NULL;  in bnx2_init_board()
8492 	kfree(bp->temp_stats_blk);  in bnx2_init_board()
8498 bnx2_bus_string(struct bnx2 *bp, char *str)  in bnx2_bus_string()  argument
8502 	if (bp->flags & BNX2_FLAG_PCIE) {  in bnx2_bus_string()
8506 		if (bp->flags & BNX2_FLAG_PCIX)  in bnx2_bus_string()
8508 		if (bp->flags & BNX2_FLAG_PCI_32BIT)  in bnx2_bus_string()
8512 		s += sprintf(s, " %dMHz", bp->bus_speed_mhz);  in bnx2_bus_string()
8518 bnx2_del_napi(struct bnx2 *bp)  in bnx2_del_napi()  argument
8522 	for (i = 0; i < bp->irq_nvecs; i++)  in bnx2_del_napi()
8523 		netif_napi_del(&bp->bnx2_napi[i].napi);  in bnx2_del_napi()
8527 bnx2_init_napi(struct bnx2 *bp)  in bnx2_init_napi()  argument
8531 	for (i = 0; i < bp->irq_nvecs; i++) {  in bnx2_init_napi()
8532 		struct bnx2_napi *bnapi = &bp->bnx2_napi[i];  in bnx2_init_napi()
8540 		netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);  in bnx2_init_napi()
8541 		bnapi->bp = bp;  in bnx2_init_napi()
8567 	struct bnx2 *bp;  in bnx2_init_one()  local
8575 	dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);  in bnx2_init_one()
8587 	bp = netdev_priv(dev);  in bnx2_init_one()
8598 		bnx2_wait_dma_complete(bp);  in bnx2_init_one()
8600 	memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);  in bnx2_init_one()
8606 	if (BNX2_CHIP(bp) == BNX2_CHIP_5709)  in bnx2_init_one()
8616 	if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))  in bnx2_init_one()
8626 		    ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',  in bnx2_init_one()
8627 		    ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),  in bnx2_init_one()
8628 		    bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),  in bnx2_init_one()
8634 	pci_iounmap(pdev, bp->regview);  in bnx2_init_one()
8647 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_remove_one()  local
8651 	del_timer_sync(&bp->timer);  in bnx2_remove_one()
8652 	cancel_work_sync(&bp->reset_task);  in bnx2_remove_one()
8654 	pci_iounmap(bp->pdev, bp->regview);  in bnx2_remove_one()
8657 	kfree(bp->temp_stats_blk);  in bnx2_remove_one()
8659 	if (bp->flags & BNX2_FLAG_AER_ENABLED) {  in bnx2_remove_one()
8661 		bp->flags &= ~BNX2_FLAG_AER_ENABLED;  in bnx2_remove_one()
8664 	bnx2_release_firmware(bp);  in bnx2_remove_one()
8677 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_suspend()  local
8680 		cancel_work_sync(&bp->reset_task);  in bnx2_suspend()
8681 		bnx2_netif_stop(bp, true);  in bnx2_suspend()
8683 		del_timer_sync(&bp->timer);  in bnx2_suspend()
8684 		bnx2_shutdown_chip(bp);  in bnx2_suspend()
8685 		__bnx2_free_irq(bp);  in bnx2_suspend()
8686 		bnx2_free_skbs(bp);  in bnx2_suspend()
8688 	bnx2_setup_wol(bp);  in bnx2_suspend()
8696 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_resume()  local
8701 	bnx2_set_power_state(bp, PCI_D0);  in bnx2_resume()
8703 	bnx2_request_irq(bp);  in bnx2_resume()
8704 	bnx2_init_nic(bp, 1);  in bnx2_resume()
8705 	bnx2_netif_start(bp, true);  in bnx2_resume()
8729 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_error_detected()  local
8740 		bnx2_netif_stop(bp, true);  in bnx2_io_error_detected()
8741 		del_timer_sync(&bp->timer);  in bnx2_io_error_detected()
8742 		bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);  in bnx2_io_error_detected()
8761 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_slot_reset()  local
8775 			err = bnx2_init_nic(bp, 1);  in bnx2_io_slot_reset()
8782 		bnx2_napi_enable(bp);  in bnx2_io_slot_reset()
8787 	if (!(bp->flags & BNX2_FLAG_AER_ENABLED))  in bnx2_io_slot_reset()
8803 	struct bnx2 *bp = netdev_priv(dev);  in bnx2_io_resume()  local
8807 		bnx2_netif_start(bp, true);  in bnx2_io_resume()
8816 	struct bnx2 *bp;  in bnx2_shutdown()  local
8821 	bp = netdev_priv(dev);  in bnx2_shutdown()
8822 	if (!bp)  in bnx2_shutdown()
8827 		dev_close(bp->dev);  in bnx2_shutdown()
8830 		bnx2_set_power_state(bp, PCI_D3hot);  in bnx2_shutdown()