Lines Matching refs:CSR0
150 #define CSR0 0x00 macro
166 #define writedatareg(val) { writereg(val,CSR0); }
171 #define writedatareg(val) { writereg(val,CSR0); }
273 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ in ni65_set_performance()
288 outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */ in ni65_set_performance()
461 if( (j=readreg(CSR0)) != 0x4) { in ni65_probe1()
513 if(readreg(CSR0) & CSR0_IDON) in ni65_probe1()
535 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ in ni65_probe1()
574 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); in ni65_init_lance()
590 writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */ in ni65_init_lance()
805 if( (i=readreg(CSR0) ) != 0x4) in ni65_lance_reinit()