323 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)  in m_can_read()  argument
325 	return cdev->ops->read_reg(cdev, reg);  in m_can_read()
328 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,  in m_can_write()  argument
331 	cdev->ops->write_reg(cdev, reg, val);  in m_can_write()
334 static u32 m_can_fifo_read(struct m_can_classdev *cdev,  in m_can_fifo_read()  argument
337 	u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +  in m_can_fifo_read()
340 	return cdev->ops->read_fifo(cdev, addr_offset);  in m_can_fifo_read()
343 static void m_can_fifo_write(struct m_can_classdev *cdev,  in m_can_fifo_write()  argument
346 	u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +  in m_can_fifo_write()
349 	cdev->ops->write_fifo(cdev, addr_offset, val);  in m_can_fifo_write()
352 static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev,  in m_can_fifo_write_no_off()  argument
355 	cdev->ops->write_fifo(cdev, fpi, val);  in m_can_fifo_write_no_off()
358 static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)  in m_can_txe_fifo_read()  argument
360 	u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +  in m_can_txe_fifo_read()
363 	return cdev->ops->read_fifo(cdev, addr_offset);  in m_can_txe_fifo_read()
366 static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)  in m_can_tx_fifo_full()  argument
368 		return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);  in m_can_tx_fifo_full()
371 void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)  in m_can_config_endisable()  argument
373 	u32 cccr = m_can_read(cdev, M_CAN_CCCR);  in m_can_config_endisable()
387 		m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT);  in m_can_config_endisable()
390 		m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);  in m_can_config_endisable()
392 		m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));  in m_can_config_endisable()
399 	while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {  in m_can_config_endisable()
401 			netdev_warn(cdev->net, "Failed to init module\n");  in m_can_config_endisable()
409 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)  in m_can_enable_all_interrupts()  argument
412 	m_can_write(cdev, M_CAN_ILE, ILE_EINT0);  in m_can_enable_all_interrupts()
415 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)  in m_can_disable_all_interrupts()  argument
417 	m_can_write(cdev, M_CAN_ILE, 0x0);  in m_can_disable_all_interrupts()
422 	struct m_can_classdev *cdev = netdev_priv(net);  in m_can_clean()  local
424 	if (cdev->tx_skb) {  in m_can_clean()
428 		if (cdev->version > 30)  in m_can_clean()
429 			putidx = ((m_can_read(cdev, M_CAN_TXFQS) &  in m_can_clean()
432 		can_free_echo_skb(cdev->net, putidx);  in m_can_clean()
433 		cdev->tx_skb = NULL;  in m_can_clean()
440 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_read_fifo()  local
448 	dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);  in m_can_read_fifo()
463 	id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID);  in m_can_read_fifo()
482 				m_can_fifo_read(cdev, fgi,  in m_can_read_fifo()
487 	m_can_write(cdev, M_CAN_RXF0A, fgi);  in m_can_read_fifo()
497 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_do_rx_poll()  local
501 	rxfs = m_can_read(cdev, M_CAN_RXF0S);  in m_can_do_rx_poll()
515 		rxfs = m_can_read(cdev, M_CAN_RXF0S);  in m_can_do_rx_poll()
550 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_handle_lec_err()  local
555 	cdev->can.can_stats.bus_error++;  in m_can_handle_lec_err()
607 	struct m_can_classdev *cdev = netdev_priv(dev);  in __m_can_get_berr_counter()  local
610 	ecr = m_can_read(cdev, M_CAN_ECR);  in __m_can_get_berr_counter()
617 static int m_can_clk_start(struct m_can_classdev *cdev)  in m_can_clk_start()  argument
621 	if (cdev->pm_clock_support == 0)  in m_can_clk_start()
624 	err = pm_runtime_get_sync(cdev->dev);  in m_can_clk_start()
626 		pm_runtime_put_noidle(cdev->dev);  in m_can_clk_start()
633 static void m_can_clk_stop(struct m_can_classdev *cdev)  in m_can_clk_stop()  argument
635 	if (cdev->pm_clock_support)  in m_can_clk_stop()
636 		pm_runtime_put_sync(cdev->dev);  in m_can_clk_stop()
642 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_get_berr_counter()  local
645 	err = m_can_clk_start(cdev);  in m_can_get_berr_counter()
651 	m_can_clk_stop(cdev);  in m_can_get_berr_counter()
659 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_handle_state_change()  local
669 		cdev->can.can_stats.error_warning++;  in m_can_handle_state_change()
670 		cdev->can.state = CAN_STATE_ERROR_WARNING;  in m_can_handle_state_change()
674 		cdev->can.can_stats.error_passive++;  in m_can_handle_state_change()
675 		cdev->can.state = CAN_STATE_ERROR_PASSIVE;  in m_can_handle_state_change()
679 		cdev->can.state = CAN_STATE_BUS_OFF;  in m_can_handle_state_change()
680 		m_can_disable_all_interrupts(cdev);  in m_can_handle_state_change()
681 		cdev->can.can_stats.bus_off++;  in m_can_handle_state_change()
708 		ecr = m_can_read(cdev, M_CAN_ECR);  in m_can_handle_state_change()
733 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_handle_state_errors()  local
736 	if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {  in m_can_handle_state_errors()
742 	if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {  in m_can_handle_state_errors()
748 	if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {  in m_can_handle_state_errors()
783 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_handle_bus_errors()  local
790 	if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&  in m_can_handle_bus_errors()
802 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_rx_handler()  local
806 	irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);  in m_can_rx_handler()
820 	if (cdev->version <= 31 && irqstatus & IR_MRAF &&  in m_can_rx_handler()
821 	    m_can_read(cdev, M_CAN_ECR) & ECR_RP) {  in m_can_rx_handler()
826 			m_can_write(cdev, M_CAN_IR, IR_MRAF);  in m_can_rx_handler()
831 	psr = m_can_read(cdev, M_CAN_PSR);  in m_can_rx_handler()
847 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_rx_peripheral()  local
851 	m_can_enable_all_interrupts(cdev);  in m_can_rx_peripheral()
859 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_poll()  local
865 		m_can_enable_all_interrupts(cdev);  in m_can_poll()
879 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_echo_tx_event()  local
883 	m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);  in m_can_echo_tx_event()
892 		fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK)  in m_can_echo_tx_event()
896 		msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) &  in m_can_echo_tx_event()
900 		m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK &  in m_can_echo_tx_event()
912 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_isr()  local
916 	ir = m_can_read(cdev, M_CAN_IR);  in m_can_isr()
922 		m_can_write(cdev, M_CAN_IR, ir);  in m_can_isr()
924 	if (cdev->ops->clear_interrupts)  in m_can_isr()
925 		cdev->ops->clear_interrupts(cdev);  in m_can_isr()
933 		cdev->irqstatus = ir;  in m_can_isr()
934 		m_can_disable_all_interrupts(cdev);  in m_can_isr()
935 		if (!cdev->is_peripheral)  in m_can_isr()
936 			napi_schedule(&cdev->napi);  in m_can_isr()
941 	if (cdev->version == 30) {  in m_can_isr()
955 			    !m_can_tx_fifo_full(cdev))  in m_can_isr()
1013 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_set_bittiming()  local
1014 	const struct can_bittiming *bt = &cdev->can.bittiming;  in m_can_set_bittiming()
1015 	const struct can_bittiming *dbt = &cdev->can.data_bittiming;  in m_can_set_bittiming()
1025 	m_can_write(cdev, M_CAN_NBTP, reg_btp);  in m_can_set_bittiming()
1027 	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {  in m_can_set_bittiming()
1049 			tdco = (cdev->can.clock.freq / 1000) *  in m_can_set_bittiming()
1060 			m_can_write(cdev, M_CAN_TDCR,  in m_can_set_bittiming()
1069 		m_can_write(cdev, M_CAN_DBTP, reg_btp);  in m_can_set_bittiming()
1086 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_chip_config()  local
1089 	m_can_config_endisable(cdev, true);  in m_can_chip_config()
1092 	m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES);  in m_can_chip_config()
1095 	m_can_write(cdev, M_CAN_GFC, 0x0);  in m_can_chip_config()
1097 	if (cdev->version == 30) {  in m_can_chip_config()
1099 		m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |  in m_can_chip_config()
1100 				cdev->mcfg[MRAM_TXB].off);  in m_can_chip_config()
1103 		m_can_write(cdev, M_CAN_TXBC,  in m_can_chip_config()
1104 			    (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |  in m_can_chip_config()
1105 			    (cdev->mcfg[MRAM_TXB].off));  in m_can_chip_config()
1109 	m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES);  in m_can_chip_config()
1112 	if (cdev->version == 30) {  in m_can_chip_config()
1113 		m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |  in m_can_chip_config()
1114 				cdev->mcfg[MRAM_TXE].off);  in m_can_chip_config()
1117 		m_can_write(cdev, M_CAN_TXEFC,  in m_can_chip_config()
1118 			    ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)  in m_can_chip_config()
1120 			    cdev->mcfg[MRAM_TXE].off);  in m_can_chip_config()
1124 	m_can_write(cdev, M_CAN_RXF0C,  in m_can_chip_config()
1125 		    (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |  in m_can_chip_config()
1126 		     cdev->mcfg[MRAM_RXF0].off);  in m_can_chip_config()
1128 	m_can_write(cdev, M_CAN_RXF1C,  in m_can_chip_config()
1129 		    (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |  in m_can_chip_config()
1130 		     cdev->mcfg[MRAM_RXF1].off);  in m_can_chip_config()
1132 	cccr = m_can_read(cdev, M_CAN_CCCR);  in m_can_chip_config()
1133 	test = m_can_read(cdev, M_CAN_TEST);  in m_can_chip_config()
1135 	if (cdev->version == 30) {  in m_can_chip_config()
1142 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)  in m_can_chip_config()
1151 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)  in m_can_chip_config()
1154 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)  in m_can_chip_config()
1159 	if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {  in m_can_chip_config()
1165 	if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)  in m_can_chip_config()
1169 	m_can_write(cdev, M_CAN_CCCR, cccr);  in m_can_chip_config()
1170 	m_can_write(cdev, M_CAN_TEST, test);  in m_can_chip_config()
1173 	m_can_write(cdev, M_CAN_IR, IR_ALL_INT);  in m_can_chip_config()
1174 	if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))  in m_can_chip_config()
1175 		if (cdev->version == 30)  in m_can_chip_config()
1176 			m_can_write(cdev, M_CAN_IE, IR_ALL_INT &  in m_can_chip_config()
1179 			m_can_write(cdev, M_CAN_IE, IR_ALL_INT &  in m_can_chip_config()
1182 		m_can_write(cdev, M_CAN_IE, IR_ALL_INT);  in m_can_chip_config()
1185 	m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);  in m_can_chip_config()
1190 	m_can_config_endisable(cdev, false);  in m_can_chip_config()
1192 	if (cdev->ops->init)  in m_can_chip_config()
1193 		cdev->ops->init(cdev);  in m_can_chip_config()
1198 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_start()  local
1203 	cdev->can.state = CAN_STATE_ERROR_ACTIVE;  in m_can_start()
1205 	m_can_enable_all_interrupts(cdev);  in m_can_start()
1228 static int m_can_check_core_release(struct m_can_classdev *cdev)  in m_can_check_core_release()  argument
1238 	crel_reg = m_can_read(cdev, M_CAN_CREL);  in m_can_check_core_release()
1256 static bool m_can_niso_supported(struct m_can_classdev *cdev)  in m_can_niso_supported()  argument
1262 	m_can_config_endisable(cdev, true);  in m_can_niso_supported()
1263 	cccr_reg = m_can_read(cdev, M_CAN_CCCR);  in m_can_niso_supported()
1265 	m_can_write(cdev, M_CAN_CCCR, cccr_reg);  in m_can_niso_supported()
1268 		cccr_poll = m_can_read(cdev, M_CAN_CCCR);  in m_can_niso_supported()
1279 	m_can_write(cdev, M_CAN_CCCR, cccr_reg);  in m_can_niso_supported()
1281 	m_can_config_endisable(cdev, false);  in m_can_niso_supported()
1364 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_stop()  local
1367 	m_can_disable_all_interrupts(cdev);  in m_can_stop()
1370 	cdev->can.state = CAN_STATE_STOPPED;  in m_can_stop()
1375 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_close()  local
1379 	if (!cdev->is_peripheral)  in m_can_close()
1380 		napi_disable(&cdev->napi);  in m_can_close()
1383 	m_can_clk_stop(cdev);  in m_can_close()
1386 	if (cdev->is_peripheral) {  in m_can_close()
1387 		cdev->tx_skb = NULL;  in m_can_close()
1388 		destroy_workqueue(cdev->tx_wq);  in m_can_close()
1389 		cdev->tx_wq = NULL;  in m_can_close()
1400 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_next_echo_skb_occupied()  local
1402 	unsigned int wrap = cdev->can.echo_skb_max;  in m_can_next_echo_skb_occupied()
1409 	return !!cdev->can.echo_skb[next_idx];  in m_can_next_echo_skb_occupied()
1412 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)  in m_can_tx_handler()  argument
1414 	struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;  in m_can_tx_handler()
1415 	struct net_device *dev = cdev->net;  in m_can_tx_handler()
1416 	struct sk_buff *skb = cdev->tx_skb;  in m_can_tx_handler()
1433 	if (cdev->version == 30) {  in m_can_tx_handler()
1437 		m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id);  in m_can_tx_handler()
1438 		m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC,  in m_can_tx_handler()
1442 			m_can_fifo_write(cdev, 0,  in m_can_tx_handler()
1448 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {  in m_can_tx_handler()
1449 			cccr = m_can_read(cdev, M_CAN_CCCR);  in m_can_tx_handler()
1461 			m_can_write(cdev, M_CAN_CCCR, cccr);  in m_can_tx_handler()
1463 		m_can_write(cdev, M_CAN_TXBTIE, 0x1);  in m_can_tx_handler()
1464 		m_can_write(cdev, M_CAN_TXBAR, 0x1);  in m_can_tx_handler()
1470 		if (m_can_tx_fifo_full(cdev)) {  in m_can_tx_handler()
1476 			if (cdev->is_peripheral) {  in m_can_tx_handler()
1486 		putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)  in m_can_tx_handler()
1489 		m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);  in m_can_tx_handler()
1504 		m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC,  in m_can_tx_handler()
1511 			m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4),  in m_can_tx_handler()
1520 		m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));  in m_can_tx_handler()
1523 		if (m_can_tx_fifo_full(cdev) ||  in m_can_tx_handler()
1533 	struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,  in m_can_tx_work_queue()  local
1536 	m_can_tx_handler(cdev);  in m_can_tx_work_queue()
1537 	cdev->tx_skb = NULL;  in m_can_tx_work_queue()
1543 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_start_xmit()  local
1548 	if (cdev->is_peripheral) {  in m_can_start_xmit()
1549 		if (cdev->tx_skb) {  in m_can_start_xmit()
1554 		if (cdev->can.state == CAN_STATE_BUS_OFF) {  in m_can_start_xmit()
1562 			cdev->tx_skb = skb;  in m_can_start_xmit()
1563 			netif_stop_queue(cdev->net);  in m_can_start_xmit()
1564 			queue_work(cdev->tx_wq, &cdev->tx_work);  in m_can_start_xmit()
1567 		cdev->tx_skb = skb;  in m_can_start_xmit()
1568 		return m_can_tx_handler(cdev);  in m_can_start_xmit()
1576 	struct m_can_classdev *cdev = netdev_priv(dev);  in m_can_open()  local
1579 	err = m_can_clk_start(cdev);  in m_can_open()
1591 	if (cdev->is_peripheral) {  in m_can_open()
1592 		cdev->tx_skb = NULL;  in m_can_open()
1593 		cdev->tx_wq = alloc_workqueue("mcan_wq",  in m_can_open()
1595 		if (!cdev->tx_wq) {  in m_can_open()
1600 		INIT_WORK(&cdev->tx_work, m_can_tx_work_queue);  in m_can_open()
1620 	if (!cdev->is_peripheral)  in m_can_open()
1621 		napi_enable(&cdev->napi);  in m_can_open()
1628 	if (cdev->is_peripheral)  in m_can_open()
1629 		destroy_workqueue(cdev->tx_wq);  in m_can_open()
1633 	m_can_clk_stop(cdev);  in m_can_open()
1652 static void m_can_of_parse_mram(struct m_can_classdev *cdev,  in m_can_of_parse_mram()  argument
1655 	cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];  in m_can_of_parse_mram()
1656 	cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];  in m_can_of_parse_mram()
1657 	cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +  in m_can_of_parse_mram()
1658 			cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;  in m_can_of_parse_mram()
1659 	cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];  in m_can_of_parse_mram()
1660 	cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +  in m_can_of_parse_mram()
1661 			cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;  in m_can_of_parse_mram()
1662 	cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &  in m_can_of_parse_mram()
1664 	cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +  in m_can_of_parse_mram()
1665 			cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;  in m_can_of_parse_mram()
1666 	cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &  in m_can_of_parse_mram()
1668 	cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +  in m_can_of_parse_mram()
1669 			cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;  in m_can_of_parse_mram()
1670 	cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];  in m_can_of_parse_mram()
1671 	cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +  in m_can_of_parse_mram()
1672 			cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;  in m_can_of_parse_mram()
1673 	cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];  in m_can_of_parse_mram()
1674 	cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +  in m_can_of_parse_mram()
1675 			cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;  in m_can_of_parse_mram()
1676 	cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &  in m_can_of_parse_mram()
1679 	dev_dbg(cdev->dev,  in m_can_of_parse_mram()
1681 		cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,  in m_can_of_parse_mram()
1682 		cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,  in m_can_of_parse_mram()
1683 		cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,  in m_can_of_parse_mram()
1684 		cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,  in m_can_of_parse_mram()
1685 		cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,  in m_can_of_parse_mram()
1686 		cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,  in m_can_of_parse_mram()
1687 		cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);  in m_can_of_parse_mram()
1690 void m_can_init_ram(struct m_can_classdev *cdev)  in m_can_init_ram()  argument
1697 	start = cdev->mcfg[MRAM_SIDF].off;  in m_can_init_ram()
1698 	end = cdev->mcfg[MRAM_TXB].off +  in m_can_init_ram()
1699 		cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;  in m_can_init_ram()
1702 		m_can_fifo_write_no_off(cdev, i, 0x0);  in m_can_init_ram()
1815 	struct m_can_classdev *cdev = netdev_priv(ndev);  in m_can_class_suspend()  local
1821 		m_can_clk_stop(cdev);  in m_can_class_suspend()
1826 	cdev->can.state = CAN_STATE_SLEEPING;  in m_can_class_suspend()
1835 	struct m_can_classdev *cdev = netdev_priv(ndev);  in m_can_class_resume()  local
1839 	cdev->can.state = CAN_STATE_ERROR_ACTIVE;  in m_can_class_resume()
1844 		ret = m_can_clk_start(cdev);  in m_can_class_resume()
1848 		m_can_init_ram(cdev);  in m_can_class_resume()