456 	u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);  in flexcan_error_irq_enable()  local
458 	priv->write(reg_ctrl, &regs->ctrl);  in flexcan_error_irq_enable()
464 	u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);  in flexcan_error_irq_disable()  local
466 	priv->write(reg_ctrl, &regs->ctrl);  in flexcan_error_irq_disable()
793 	u32 reg_ctrl, reg_id, reg_iflag1;  in flexcan_mailbox_read()  local
802 			reg_ctrl = priv->read(&mb->can_ctrl);  in flexcan_mailbox_read()
803 		} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);  in flexcan_mailbox_read()
806 		code = reg_ctrl & FLEXCAN_MB_CODE_MASK;  in flexcan_mailbox_read()
821 		reg_ctrl = priv->read(&mb->can_ctrl);  in flexcan_mailbox_read()
825 	*timestamp = reg_ctrl << 16;  in flexcan_mailbox_read()
828 	if (reg_ctrl & FLEXCAN_MB_CNT_IDE)  in flexcan_mailbox_read()
833 	if (reg_ctrl & FLEXCAN_MB_CNT_RTR)  in flexcan_mailbox_read()
835 	cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);  in flexcan_mailbox_read()
920 		u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);  in flexcan_irq()  local
924 							       0, reg_ctrl << 16);  in flexcan_irq()
1042 	u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;  in flexcan_chip_start()  local
1116 	reg_ctrl = priv->read(&regs->ctrl);  in flexcan_chip_start()
1117 	reg_ctrl &= ~FLEXCAN_CTRL_TSYN;  in flexcan_chip_start()
1118 	reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |  in flexcan_chip_start()
1127 		reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;  in flexcan_chip_start()
1129 		reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;  in flexcan_chip_start()
1132 	priv->reg_ctrl_default = reg_ctrl;  in flexcan_chip_start()
1134 	reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;  in flexcan_chip_start()
1135 	netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);  in flexcan_chip_start()
1136 	priv->write(reg_ctrl, &regs->ctrl);  in flexcan_chip_start()