Lines Matching +full:nand +full:- +full:ecc +full:- +full:maximize
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
31 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
37 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
38 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
153 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
182 struct mtd_oob_region ecc; member
204 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
208 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
210 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
211 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_rs_ecc()
219 return -ERANGE; in tegra_nand_ooblayout_no_free()
223 .ecc = tegra_nand_ooblayout_rs_ecc,
231 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, in tegra_nand_ooblayout_bch_ecc()
235 return -ERANGE; in tegra_nand_ooblayout_bch_ecc()
237 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_bch_ecc()
238 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_bch_ecc()
244 .ecc = tegra_nand_ooblayout_bch_ecc,
253 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_irq()
254 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
255 dev_dbg(ctrl->dev, "isr %08x\n", isr); in tegra_nand_irq()
262 * HW ECC was successful. The data sheet states: in tegra_nand_irq()
263 * Correctable OR Un-correctable errors occurred in the DMA transfer... in tegra_nand_irq()
266 ctrl->last_read_error = true; in tegra_nand_irq()
269 complete(&ctrl->command_complete); in tegra_nand_irq()
272 dev_err(ctrl->dev, "FIFO underrun\n"); in tegra_nand_irq()
275 dev_err(ctrl->dev, "FIFO overrun\n"); in tegra_nand_irq()
279 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
280 complete(&ctrl->dma_complete); in tegra_nand_irq()
284 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_irq()
313 dev_err(ctrl->dev, "Tegra NAND controller register dump\n"); in tegra_nand_dump_reg()
320 reg = readl_relaxed(ctrl->regs + (i * 4)); in tegra_nand_dump_reg()
321 dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg); in tegra_nand_dump_reg()
329 disable_irq(ctrl->irq); in tegra_nand_controller_abort()
332 writel_relaxed(0, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
333 writel_relaxed(0, ctrl->regs + COMMAND); in tegra_nand_controller_abort()
336 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_controller_abort()
337 writel_relaxed(isr, ctrl->regs + ISR); in tegra_nand_controller_abort()
338 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
339 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_controller_abort()
341 reinit_completion(&ctrl->command_complete); in tegra_nand_controller_abort()
342 reinit_completion(&ctrl->dma_complete); in tegra_nand_controller_abort()
344 enable_irq(ctrl->irq); in tegra_nand_controller_abort()
352 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_cmd()
358 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in tegra_nand_cmd()
363 instr = &subop->instrs[op_id]; in tegra_nand_cmd()
365 switch (instr->type) { in tegra_nand_cmd()
369 writel_relaxed(instr->ctx.cmd.opcode, in tegra_nand_cmd()
370 ctrl->regs + CMD_REG1); in tegra_nand_cmd()
373 writel_relaxed(instr->ctx.cmd.opcode, in tegra_nand_cmd()
374 ctrl->regs + CMD_REG2); in tegra_nand_cmd()
382 addrs = &instr->ctx.addr.addrs[offset]; in tegra_nand_cmd()
387 naddrs -= i; in tegra_nand_cmd()
391 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_cmd()
392 writel_relaxed(addr2, ctrl->regs + ADDR_REG2); in tegra_nand_cmd()
411 memcpy(®, instr->ctx.data.buf.out + offset, size); in tegra_nand_cmd()
413 writel_relaxed(reg, ctrl->regs + RESP); in tegra_nand_cmd()
422 cmd |= COMMAND_GO | COMMAND_CE(ctrl->cur_cs); in tegra_nand_cmd()
423 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_cmd()
424 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_cmd()
427 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_cmd()
430 return -ETIMEDOUT; in tegra_nand_cmd()
434 reg = readl_relaxed(ctrl->regs + RESP); in tegra_nand_cmd()
435 memcpy(instr_data_in->ctx.data.buf.in + offset, ®, size); in tegra_nand_cmd()
460 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_select_target() local
461 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_select_target()
463 ctrl->cur_cs = nand->cs[die_nr]; in tegra_nand_select_target()
470 tegra_nand_select_target(chip, op->cs); in tegra_nand_exec_op()
478 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_hw_ecc() local
480 if (chip->ecc.algo == NAND_ECC_BCH && enable) in tegra_nand_hw_ecc()
481 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
483 writel_relaxed(0, ctrl->regs + BCH_CONFIG); in tegra_nand_hw_ecc()
486 writel_relaxed(nand->config_ecc, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
488 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_hw_ecc()
495 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_page_xfer()
501 tegra_nand_select_target(chip, chip->cur_cs); in tegra_nand_page_xfer()
504 writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
505 writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
507 writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_REG1); in tegra_nand_page_xfer()
508 writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_REG2); in tegra_nand_page_xfer()
512 /* Lower 16-bits are column, by default 0 */ in tegra_nand_page_xfer()
516 addr1 |= mtd->writesize; in tegra_nand_page_xfer()
517 writel_relaxed(addr1, ctrl->regs + ADDR_REG1); in tegra_nand_page_xfer()
519 if (chip->options & NAND_ROW_ADDR_3) { in tegra_nand_page_xfer()
520 writel_relaxed(page >> 16, ctrl->regs + ADDR_REG2); in tegra_nand_page_xfer()
527 dma_addr = dma_map_single(ctrl->dev, buf, mtd->writesize, dir); in tegra_nand_page_xfer()
528 ret = dma_mapping_error(ctrl->dev, dma_addr); in tegra_nand_page_xfer()
530 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
531 return -EINVAL; in tegra_nand_page_xfer()
534 writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A); in tegra_nand_page_xfer()
535 writel_relaxed(dma_addr, ctrl->regs + DATA_PTR); in tegra_nand_page_xfer()
539 dma_addr_oob = dma_map_single(ctrl->dev, oob_buf, mtd->oobsize, in tegra_nand_page_xfer()
541 ret = dma_mapping_error(ctrl->dev, dma_addr_oob); in tegra_nand_page_xfer()
543 dev_err(ctrl->dev, "dma mapping error\n"); in tegra_nand_page_xfer()
544 ret = -EINVAL; in tegra_nand_page_xfer()
548 writel_relaxed(oob_len - 1, ctrl->regs + DMA_CFG_B); in tegra_nand_page_xfer()
549 writel_relaxed(dma_addr_oob, ctrl->regs + TAG_PTR); in tegra_nand_page_xfer()
566 writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL); in tegra_nand_page_xfer()
569 COMMAND_CE(ctrl->cur_cs); in tegra_nand_page_xfer()
581 writel_relaxed(cmd, ctrl->regs + COMMAND); in tegra_nand_page_xfer()
583 ret = wait_for_completion_timeout(&ctrl->command_complete, in tegra_nand_page_xfer()
586 dev_err(ctrl->dev, "COMMAND timeout\n"); in tegra_nand_page_xfer()
589 ret = -ETIMEDOUT; in tegra_nand_page_xfer()
593 ret = wait_for_completion_timeout(&ctrl->dma_complete, in tegra_nand_page_xfer()
596 dev_err(ctrl->dev, "DMA timeout\n"); in tegra_nand_page_xfer()
599 ret = -ETIMEDOUT; in tegra_nand_page_xfer()
606 dma_unmap_single(ctrl->dev, dma_addr_oob, mtd->oobsize, dir); in tegra_nand_page_xfer()
609 dma_unmap_single(ctrl->dev, dma_addr, mtd->writesize, dir); in tegra_nand_page_xfer()
618 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_read_page_raw()
621 mtd->oobsize, page, true); in tegra_nand_read_page_raw()
628 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_write_page_raw()
631 mtd->oobsize, page, false); in tegra_nand_write_page_raw()
638 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi, in tegra_nand_read_oob()
639 mtd->oobsize, page, true); in tegra_nand_read_oob()
646 return tegra_nand_page_xfer(mtd, chip, NULL, chip->oob_poi, in tegra_nand_write_oob()
647 mtd->oobsize, page, false); in tegra_nand_write_oob()
654 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_read_page_hwecc()
655 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_read_page_hwecc() local
656 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_read_page_hwecc()
667 /* No correctable or un-correctable errors, page must have 0 bitflips */ in tegra_nand_read_page_hwecc()
668 if (!ctrl->last_read_error) in tegra_nand_read_page_hwecc()
672 * Correctable or un-correctable errors occurred. Use DEC_STAT_BUF in tegra_nand_read_page_hwecc()
673 * which contains information for all ECC selections. in tegra_nand_read_page_hwecc()
680 ctrl->last_read_error = false; in tegra_nand_read_page_hwecc()
681 dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF); in tegra_nand_read_page_hwecc()
705 if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) { in tegra_nand_read_page_hwecc()
706 mtd->ecc_stats.failed += hweight8(fail_sec_flag); in tegra_nand_read_page_hwecc()
711 * All sectors failed to correct, but the ECC isn't smart in tegra_nand_read_page_hwecc()
714 * erased or if error correction just failed for all sub- in tegra_nand_read_page_hwecc()
721 for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) { in tegra_nand_read_page_hwecc()
722 u8 *data = buf + (chip->ecc.size * bit); in tegra_nand_read_page_hwecc()
723 u8 *oob = chip->oob_poi + nand->ecc.offset + in tegra_nand_read_page_hwecc()
724 (chip->ecc.bytes * bit); in tegra_nand_read_page_hwecc()
726 ret = nand_check_erased_ecc_chunk(data, chip->ecc.size, in tegra_nand_read_page_hwecc()
727 oob, chip->ecc.bytes, in tegra_nand_read_page_hwecc()
729 chip->ecc.strength); in tegra_nand_read_page_hwecc()
731 mtd->ecc_stats.failed++; in tegra_nand_read_page_hwecc()
733 mtd->ecc_stats.corrected += ret; in tegra_nand_read_page_hwecc()
747 * bitflips encountered in any of the ECC regions. As there is in tegra_nand_read_page_hwecc()
754 mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag); in tegra_nand_read_page_hwecc()
764 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_write_page_hwecc()
765 void *oob_buf = oob_required ? chip->oob_poi : NULL; in tegra_nand_write_page_hwecc()
783 unsigned int rate = clk_get_rate(ctrl->clk) / 1000000; in tegra_nand_setup_timing()
787 val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min, in tegra_nand_setup_timing()
788 timings->tRC_min), period); in tegra_nand_setup_timing()
791 val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min), in tegra_nand_setup_timing()
792 max(timings->tALS_min, timings->tALH_min)), in tegra_nand_setup_timing()
796 val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000, in tegra_nand_setup_timing()
800 reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1)); in tegra_nand_setup_timing()
801 reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1)); in tegra_nand_setup_timing()
802 reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1)); in tegra_nand_setup_timing()
803 reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1)); in tegra_nand_setup_timing()
804 reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1)); in tegra_nand_setup_timing()
806 writel_relaxed(reg, ctrl->regs + TIMING_1); in tegra_nand_setup_timing()
808 val = DIV_ROUND_UP(timings->tADL_min, period); in tegra_nand_setup_timing()
811 writel_relaxed(reg, ctrl->regs + TIMING_2); in tegra_nand_setup_timing()
817 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_setup_data_interface()
841 bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE; in tegra_nand_get_strength() local
846 * maximize the BCH strength. in tegra_nand_get_strength()
851 if (maximize) { in tegra_nand_get_strength()
852 strength_sel = strength[strength_len - i - 1]; in tegra_nand_get_strength()
856 if (strength_sel < chip->base.eccreq.strength) in tegra_nand_get_strength()
862 bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_get_strength()
865 if (bytes_per_page < (oobsize - SKIP_SPARE_BYTES)) in tegra_nand_get_strength()
869 return -EINVAL; in tegra_nand_get_strength()
877 switch (chip->ecc.algo) { in tegra_nand_select_strength()
880 if (chip->options & NAND_IS_BOOT_MEDIUM) { in tegra_nand_select_strength()
890 if (chip->options & NAND_IS_BOOT_MEDIUM) { in tegra_nand_select_strength()
899 return -EINVAL; in tegra_nand_select_strength()
908 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); in tegra_nand_attach_chip()
909 struct tegra_nand_chip *nand = to_tegra_chip(chip); in tegra_nand_attach_chip() local
914 if (chip->bbt_options & NAND_BBT_USE_FLASH) in tegra_nand_attach_chip()
915 chip->bbt_options |= NAND_BBT_NO_OOB; in tegra_nand_attach_chip()
917 chip->ecc.mode = NAND_ECC_HW; in tegra_nand_attach_chip()
918 chip->ecc.size = 512; in tegra_nand_attach_chip()
919 chip->ecc.steps = mtd->writesize / chip->ecc.size; in tegra_nand_attach_chip()
920 if (chip->base.eccreq.step_size != 512) { in tegra_nand_attach_chip()
921 dev_err(ctrl->dev, "Unsupported step size %d\n", in tegra_nand_attach_chip()
922 chip->base.eccreq.step_size); in tegra_nand_attach_chip()
923 return -EINVAL; in tegra_nand_attach_chip()
926 chip->ecc.read_page = tegra_nand_read_page_hwecc; in tegra_nand_attach_chip()
927 chip->ecc.write_page = tegra_nand_write_page_hwecc; in tegra_nand_attach_chip()
928 chip->ecc.read_page_raw = tegra_nand_read_page_raw; in tegra_nand_attach_chip()
929 chip->ecc.write_page_raw = tegra_nand_write_page_raw; in tegra_nand_attach_chip()
930 chip->ecc.read_oob = tegra_nand_read_oob; in tegra_nand_attach_chip()
931 chip->ecc.write_oob = tegra_nand_write_oob; in tegra_nand_attach_chip()
933 if (chip->options & NAND_BUSWIDTH_16) in tegra_nand_attach_chip()
934 nand->config |= CONFIG_BUS_WIDTH_16; in tegra_nand_attach_chip()
936 if (chip->ecc.algo == NAND_ECC_UNKNOWN) { in tegra_nand_attach_chip()
937 if (mtd->writesize < 2048) in tegra_nand_attach_chip()
938 chip->ecc.algo = NAND_ECC_RS; in tegra_nand_attach_chip()
940 chip->ecc.algo = NAND_ECC_BCH; in tegra_nand_attach_chip()
943 if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) { in tegra_nand_attach_chip()
944 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n"); in tegra_nand_attach_chip()
945 return -EINVAL; in tegra_nand_attach_chip()
948 if (!chip->ecc.strength) { in tegra_nand_attach_chip()
949 ret = tegra_nand_select_strength(chip, mtd->oobsize); in tegra_nand_attach_chip()
951 dev_err(ctrl->dev, in tegra_nand_attach_chip()
953 chip->base.eccreq.strength); in tegra_nand_attach_chip()
957 chip->ecc.strength = ret; in tegra_nand_attach_chip()
960 nand->config_ecc = CONFIG_PIPE_EN | CONFIG_SKIP_SPARE | in tegra_nand_attach_chip()
963 switch (chip->ecc.algo) { in tegra_nand_attach_chip()
965 bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength; in tegra_nand_attach_chip()
967 nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL | in tegra_nand_attach_chip()
969 switch (chip->ecc.strength) { in tegra_nand_attach_chip()
971 nand->config_ecc |= CONFIG_TVAL_4; in tegra_nand_attach_chip()
974 nand->config_ecc |= CONFIG_TVAL_6; in tegra_nand_attach_chip()
977 nand->config_ecc |= CONFIG_TVAL_8; in tegra_nand_attach_chip()
980 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
981 chip->ecc.strength); in tegra_nand_attach_chip()
982 return -EINVAL; in tegra_nand_attach_chip()
986 bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength; in tegra_nand_attach_chip()
988 nand->bch_config = BCH_ENABLE; in tegra_nand_attach_chip()
989 switch (chip->ecc.strength) { in tegra_nand_attach_chip()
991 nand->bch_config |= BCH_TVAL_4; in tegra_nand_attach_chip()
994 nand->bch_config |= BCH_TVAL_8; in tegra_nand_attach_chip()
997 nand->bch_config |= BCH_TVAL_14; in tegra_nand_attach_chip()
1000 nand->bch_config |= BCH_TVAL_16; in tegra_nand_attach_chip()
1003 dev_err(ctrl->dev, "ECC strength %d not supported\n", in tegra_nand_attach_chip()
1004 chip->ecc.strength); in tegra_nand_attach_chip()
1005 return -EINVAL; in tegra_nand_attach_chip()
1009 dev_err(ctrl->dev, "ECC algorithm not supported\n"); in tegra_nand_attach_chip()
1010 return -EINVAL; in tegra_nand_attach_chip()
1013 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n", in tegra_nand_attach_chip()
1014 chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS", in tegra_nand_attach_chip()
1015 chip->ecc.strength); in tegra_nand_attach_chip()
1017 chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE); in tegra_nand_attach_chip()
1019 switch (mtd->writesize) { in tegra_nand_attach_chip()
1021 nand->config |= CONFIG_PS_256; in tegra_nand_attach_chip()
1024 nand->config |= CONFIG_PS_512; in tegra_nand_attach_chip()
1027 nand->config |= CONFIG_PS_1024; in tegra_nand_attach_chip()
1030 nand->config |= CONFIG_PS_2048; in tegra_nand_attach_chip()
1033 nand->config |= CONFIG_PS_4096; in tegra_nand_attach_chip()
1036 dev_err(ctrl->dev, "Unsupported writesize %d\n", in tegra_nand_attach_chip()
1037 mtd->writesize); in tegra_nand_attach_chip()
1038 return -ENODEV; in tegra_nand_attach_chip()
1041 /* Store complete configuration for HW ECC in config_ecc */ in tegra_nand_attach_chip()
1042 nand->config_ecc |= nand->config; in tegra_nand_attach_chip()
1044 /* Non-HW ECC read/writes complete OOB */ in tegra_nand_attach_chip()
1045 nand->config |= CONFIG_TAG_BYTE_SIZE(mtd->oobsize - 1); in tegra_nand_attach_chip()
1046 writel_relaxed(nand->config, ctrl->regs + CONFIG); in tegra_nand_attach_chip()
1060 struct device_node *np = dev->of_node; in tegra_nand_chips_init()
1063 struct tegra_nand_chip *nand; in tegra_nand_chips_init() local
1070 dev_err(dev, "Currently only one NAND chip supported\n"); in tegra_nand_chips_init()
1071 return -EINVAL; in tegra_nand_chips_init()
1079 return -EINVAL; in tegra_nand_chips_init()
1082 /* Retrieve CS id, currently only single die NAND supported */ in tegra_nand_chips_init()
1089 nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL); in tegra_nand_chips_init()
1090 if (!nand) in tegra_nand_chips_init()
1091 return -ENOMEM; in tegra_nand_chips_init()
1093 nand->cs[0] = cs; in tegra_nand_chips_init()
1095 nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW); in tegra_nand_chips_init()
1097 if (IS_ERR(nand->wp_gpio)) { in tegra_nand_chips_init()
1098 ret = PTR_ERR(nand->wp_gpio); in tegra_nand_chips_init()
1103 chip = &nand->chip; in tegra_nand_chips_init()
1104 chip->controller = &ctrl->controller; in tegra_nand_chips_init()
1108 mtd->dev.parent = dev; in tegra_nand_chips_init()
1109 mtd->owner = THIS_MODULE; in tegra_nand_chips_init()
1113 if (!mtd->name) in tegra_nand_chips_init()
1114 mtd->name = "tegra_nand"; in tegra_nand_chips_init()
1116 chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; in tegra_nand_chips_init()
1122 mtd_ooblayout_ecc(mtd, 0, &nand->ecc); in tegra_nand_chips_init()
1131 ctrl->chip = chip; in tegra_nand_chips_init()
1143 ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); in tegra_nand_probe()
1145 return -ENOMEM; in tegra_nand_probe()
1147 ctrl->dev = &pdev->dev; in tegra_nand_probe()
1148 nand_controller_init(&ctrl->controller); in tegra_nand_probe()
1149 ctrl->controller.ops = &tegra_nand_controller_ops; in tegra_nand_probe()
1152 ctrl->regs = devm_ioremap_resource(&pdev->dev, res); in tegra_nand_probe()
1153 if (IS_ERR(ctrl->regs)) in tegra_nand_probe()
1154 return PTR_ERR(ctrl->regs); in tegra_nand_probe()
1156 rst = devm_reset_control_get(&pdev->dev, "nand"); in tegra_nand_probe()
1160 ctrl->clk = devm_clk_get(&pdev->dev, "nand"); in tegra_nand_probe()
1161 if (IS_ERR(ctrl->clk)) in tegra_nand_probe()
1162 return PTR_ERR(ctrl->clk); in tegra_nand_probe()
1164 err = clk_prepare_enable(ctrl->clk); in tegra_nand_probe()
1170 dev_err(ctrl->dev, "Failed to reset HW: %d\n", err); in tegra_nand_probe()
1174 writel_relaxed(HWSTATUS_CMD_DEFAULT, ctrl->regs + HWSTATUS_CMD); in tegra_nand_probe()
1175 writel_relaxed(HWSTATUS_MASK_DEFAULT, ctrl->regs + HWSTATUS_MASK); in tegra_nand_probe()
1176 writel_relaxed(INT_MASK, ctrl->regs + IER); in tegra_nand_probe()
1178 init_completion(&ctrl->command_complete); in tegra_nand_probe()
1179 init_completion(&ctrl->dma_complete); in tegra_nand_probe()
1181 ctrl->irq = platform_get_irq(pdev, 0); in tegra_nand_probe()
1182 err = devm_request_irq(&pdev->dev, ctrl->irq, tegra_nand_irq, 0, in tegra_nand_probe()
1183 dev_name(&pdev->dev), ctrl); in tegra_nand_probe()
1185 dev_err(ctrl->dev, "Failed to get IRQ: %d\n", err); in tegra_nand_probe()
1189 writel_relaxed(DMA_MST_CTRL_IS_DONE, ctrl->regs + DMA_MST_CTRL); in tegra_nand_probe()
1191 err = tegra_nand_chips_init(ctrl->dev, ctrl); in tegra_nand_probe()
1200 clk_disable_unprepare(ctrl->clk); in tegra_nand_probe()
1207 struct nand_chip *chip = ctrl->chip; in tegra_nand_remove()
1217 clk_disable_unprepare(ctrl->clk); in tegra_nand_remove()
1223 { .compatible = "nvidia,tegra20-nand" },
1230 .name = "tegra-nand",
1238 MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");