Lines Matching refs:nandc
183 #define nandc_set_read_loc(nandc, reg, offset, size, is_last) \ argument
184 nandc_set_reg(nandc, NAND_READ_LOCATION_##reg, \
193 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
471 static void free_bam_transaction(struct qcom_nand_controller *nandc) in free_bam_transaction() argument
473 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
475 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
480 alloc_bam_transaction(struct qcom_nand_controller *nandc) in alloc_bam_transaction() argument
484 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
493 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
516 static void clear_bam_transaction(struct qcom_nand_controller *nandc) in clear_bam_transaction() argument
518 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
520 if (!nandc->props->is_bam) in clear_bam_transaction()
534 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
536 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
572 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
574 return ioread32(nandc->base + offset); in nandc_read()
577 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
580 iowrite32(val, nandc->base + offset); in nandc_write()
583 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, in nandc_read_buffer_sync() argument
586 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
590 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
592 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
595 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
597 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
647 static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset, in nandc_set_reg() argument
650 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
663 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in set_address() local
668 nandc_set_reg(nandc, NAND_ADDR0, page << 16 | column); in set_address()
669 nandc_set_reg(nandc, NAND_ADDR1, page >> 16 & 0xff); in set_address()
682 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in update_rw_regs() local
708 nandc_set_reg(nandc, NAND_FLASH_CMD, cmd); in update_rw_regs()
709 nandc_set_reg(nandc, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
710 nandc_set_reg(nandc, NAND_DEV0_CFG1, cfg1); in update_rw_regs()
711 nandc_set_reg(nandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg); in update_rw_regs()
712 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg); in update_rw_regs()
713 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in update_rw_regs()
714 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in update_rw_regs()
715 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in update_rw_regs()
718 nandc_set_read_loc(nandc, 0, 0, host->use_ecc ? in update_rw_regs()
727 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, in prepare_bam_async_desc() argument
735 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
743 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
749 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
764 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
766 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
778 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
779 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
787 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
792 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
806 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_cmd() argument
813 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
821 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
823 reg_buf_dma_addr(nandc, in prep_bam_dma_desc_cmd()
827 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
846 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
861 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_data() argument
866 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
882 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
892 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, in prep_adm_dma_desc() argument
919 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
930 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
931 slave_conf.slave_id = nandc->data_crci; in prep_adm_dma_desc()
934 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
935 slave_conf.slave_id = nandc->cmd_crci; in prep_adm_dma_desc()
938 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
940 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
944 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
946 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
953 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
970 static int read_reg_dma(struct qcom_nand_controller *nandc, int first, in read_reg_dma() argument
976 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
977 nandc->reg_read_pos += num_regs; in read_reg_dma()
980 first = dev_cmd_reg_addr(nandc, first); in read_reg_dma()
982 if (nandc->props->is_bam) in read_reg_dma()
983 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, in read_reg_dma()
989 return prep_adm_dma_desc(nandc, true, first, vaddr, in read_reg_dma()
1001 static int write_reg_dma(struct qcom_nand_controller *nandc, int first, in write_reg_dma() argument
1005 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1021 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); in write_reg_dma()
1024 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); in write_reg_dma()
1026 if (nandc->props->is_bam) in write_reg_dma()
1027 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, in write_reg_dma()
1033 return prep_adm_dma_desc(nandc, false, first, vaddr, in write_reg_dma()
1046 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1049 if (nandc->props->is_bam) in read_data_dma()
1050 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); in read_data_dma()
1052 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1064 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1067 if (nandc->props->is_bam) in write_data_dma()
1068 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); in write_data_dma()
1070 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1077 static void config_nand_page_read(struct qcom_nand_controller *nandc) in config_nand_page_read() argument
1079 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_read()
1080 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
1081 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
1082 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); in config_nand_page_read()
1083 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, in config_nand_page_read()
1092 config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc) in config_nand_cw_read() argument
1094 if (nandc->props->is_bam) in config_nand_cw_read()
1095 write_reg_dma(nandc, NAND_READ_LOCATION_0, 4, in config_nand_cw_read()
1098 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1099 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1102 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); in config_nand_cw_read()
1103 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, in config_nand_cw_read()
1106 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1115 config_nand_single_cw_page_read(struct qcom_nand_controller *nandc, in config_nand_single_cw_page_read() argument
1118 config_nand_page_read(nandc); in config_nand_single_cw_page_read()
1119 config_nand_cw_read(nandc, use_ecc); in config_nand_single_cw_page_read()
1126 static void config_nand_page_write(struct qcom_nand_controller *nandc) in config_nand_page_write() argument
1128 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_write()
1129 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
1130 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
1138 static void config_nand_cw_write(struct qcom_nand_controller *nandc) in config_nand_cw_write() argument
1140 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1141 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1143 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1145 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
1146 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1158 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_param() local
1165 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE); in nandc_param()
1166 nandc_set_reg(nandc, NAND_ADDR0, 0); in nandc_param()
1167 nandc_set_reg(nandc, NAND_ADDR1, 0); in nandc_param()
1168 nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE in nandc_param()
1172 nandc_set_reg(nandc, NAND_DEV0_CFG1, 7 << NAND_RECOVERY_CYCLES in nandc_param()
1179 nandc_set_reg(nandc, NAND_EBI2_ECC_BUF_CFG, 1 << ECC_CFG_ECC_DISABLE); in nandc_param()
1182 nandc_set_reg(nandc, NAND_DEV_CMD_VLD, in nandc_param()
1183 (nandc->vld & ~READ_START_VLD)); in nandc_param()
1184 nandc_set_reg(nandc, NAND_DEV_CMD1, in nandc_param()
1185 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in nandc_param()
1188 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in nandc_param()
1190 nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in nandc_param()
1191 nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in nandc_param()
1192 nandc_set_read_loc(nandc, 0, 0, 512, 1); in nandc_param()
1194 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); in nandc_param()
1195 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1197 nandc->buf_count = 512; in nandc_param()
1198 memset(nandc->data_buffer, 0xff, nandc->buf_count); in nandc_param()
1200 config_nand_single_cw_page_read(nandc, false); in nandc_param()
1202 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in nandc_param()
1203 nandc->buf_count, 0); in nandc_param()
1206 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); in nandc_param()
1207 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); in nandc_param()
1216 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in erase_block() local
1218 nandc_set_reg(nandc, NAND_FLASH_CMD, in erase_block()
1220 nandc_set_reg(nandc, NAND_ADDR0, page_addr); in erase_block()
1221 nandc_set_reg(nandc, NAND_ADDR1, 0); in erase_block()
1222 nandc_set_reg(nandc, NAND_DEV0_CFG0, in erase_block()
1224 nandc_set_reg(nandc, NAND_DEV0_CFG1, host->cfg1_raw); in erase_block()
1225 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in erase_block()
1226 nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus); in erase_block()
1227 nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus); in erase_block()
1229 write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); in erase_block()
1230 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in erase_block()
1231 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in erase_block()
1233 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1235 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in erase_block()
1236 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in erase_block()
1245 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_id() local
1250 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID); in read_id()
1251 nandc_set_reg(nandc, NAND_ADDR0, column); in read_id()
1252 nandc_set_reg(nandc, NAND_ADDR1, 0); in read_id()
1253 nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT, in read_id()
1254 nandc->props->is_bam ? 0 : DM_EN); in read_id()
1255 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in read_id()
1257 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in read_id()
1258 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in read_id()
1260 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); in read_id()
1269 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in reset() local
1271 nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE); in reset()
1272 nandc_set_reg(nandc, NAND_EXEC_CMD, 1); in reset()
1274 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1275 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in reset()
1277 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in reset()
1283 static int submit_descs(struct qcom_nand_controller *nandc) in submit_descs() argument
1287 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1290 if (nandc->props->is_bam) { in submit_descs()
1292 r = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1298 r = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1305 r = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1312 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1315 if (nandc->props->is_bam) { in submit_descs()
1324 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1325 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1326 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1332 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1339 static void free_descs(struct qcom_nand_controller *nandc) in free_descs() argument
1343 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in free_descs()
1346 if (nandc->props->is_bam) in free_descs()
1347 dma_unmap_sg(nandc->dev, desc->bam_sgl, in free_descs()
1350 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in free_descs()
1358 static void clear_read_regs(struct qcom_nand_controller *nandc) in clear_read_regs() argument
1360 nandc->reg_read_pos = 0; in clear_read_regs()
1361 nandc_read_buffer_sync(nandc, false); in clear_read_regs()
1367 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in pre_command() local
1369 nandc->buf_count = 0; in pre_command()
1370 nandc->buf_start = 0; in pre_command()
1374 clear_read_regs(nandc); in pre_command()
1378 clear_bam_transaction(nandc); in pre_command()
1389 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_erase_write_errors() local
1395 nandc_read_buffer_sync(nandc, true); in parse_erase_write_errors()
1398 u32 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in parse_erase_write_errors()
1413 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in post_command() local
1417 nandc_read_buffer_sync(nandc, true); in post_command()
1418 memcpy(nandc->data_buffer, nandc->reg_read_buf, in post_command()
1419 nandc->buf_count); in post_command()
1441 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_command() local
1454 nandc->buf_count = 4; in qcom_nandc_command()
1491 dev_err(nandc->dev, "failure executing command %d\n", in qcom_nandc_command()
1493 free_descs(nandc); in qcom_nandc_command()
1498 ret = submit_descs(nandc); in qcom_nandc_command()
1500 dev_err(nandc->dev, in qcom_nandc_command()
1505 free_descs(nandc); in qcom_nandc_command()
1568 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in check_flash_errors() local
1572 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1587 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_cw_raw() local
1595 clear_bam_transaction(nandc); in qcom_nandc_read_cw_raw()
1598 config_nand_page_read(nandc); in qcom_nandc_read_cw_raw()
1613 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1614 nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0); in qcom_nandc_read_cw_raw()
1617 nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0); in qcom_nandc_read_cw_raw()
1620 nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0); in qcom_nandc_read_cw_raw()
1623 nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1); in qcom_nandc_read_cw_raw()
1626 config_nand_cw_read(nandc, false); in qcom_nandc_read_cw_raw()
1628 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_cw_raw()
1631 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); in qcom_nandc_read_cw_raw()
1634 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); in qcom_nandc_read_cw_raw()
1637 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); in qcom_nandc_read_cw_raw()
1639 ret = submit_descs(nandc); in qcom_nandc_read_cw_raw()
1640 free_descs(nandc); in qcom_nandc_read_cw_raw()
1642 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1728 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_read_errors() local
1737 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1738 nandc_read_buffer_sync(nandc, true); in parse_read_errors()
1832 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_page_ecc() local
1837 config_nand_page_read(nandc); in read_page_ecc()
1852 if (nandc->props->is_bam) { in read_page_ecc()
1854 nandc_set_read_loc(nandc, 0, 0, data_size, 0); in read_page_ecc()
1855 nandc_set_read_loc(nandc, 1, data_size, in read_page_ecc()
1858 nandc_set_read_loc(nandc, 0, 0, data_size, 1); in read_page_ecc()
1860 nandc_set_read_loc(nandc, 0, data_size, in read_page_ecc()
1865 config_nand_cw_read(nandc, true); in read_page_ecc()
1868 read_data_dma(nandc, FLASH_BUF_ACC, data_buf, in read_page_ecc()
1884 read_data_dma(nandc, FLASH_BUF_ACC + data_size, in read_page_ecc()
1894 ret = submit_descs(nandc); in read_page_ecc()
1895 free_descs(nandc); in read_page_ecc()
1898 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
1912 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in copy_last_cw() local
1917 clear_read_regs(nandc); in copy_last_cw()
1922 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
1927 config_nand_single_cw_page_read(nandc, host->use_ecc); in copy_last_cw()
1929 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
1931 ret = submit_descs(nandc); in copy_last_cw()
1933 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
1935 free_descs(nandc); in copy_last_cw()
1945 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_page() local
1952 clear_bam_transaction(nandc); in qcom_nandc_read_page()
1984 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_oob() local
1987 clear_read_regs(nandc); in qcom_nandc_read_oob()
1988 clear_bam_transaction(nandc); in qcom_nandc_read_oob()
2002 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page() local
2009 clear_read_regs(nandc); in qcom_nandc_write_page()
2010 clear_bam_transaction(nandc); in qcom_nandc_write_page()
2017 config_nand_page_write(nandc); in qcom_nandc_write_page()
2032 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, in qcom_nandc_write_page()
2045 write_data_dma(nandc, FLASH_BUF_ACC + data_size, in qcom_nandc_write_page()
2049 config_nand_cw_write(nandc); in qcom_nandc_write_page()
2055 ret = submit_descs(nandc); in qcom_nandc_write_page()
2057 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2059 free_descs(nandc); in qcom_nandc_write_page()
2074 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page_raw() local
2080 clear_read_regs(nandc); in qcom_nandc_write_page_raw()
2081 clear_bam_transaction(nandc); in qcom_nandc_write_page_raw()
2088 config_nand_page_write(nandc); in qcom_nandc_write_page_raw()
2107 write_data_dma(nandc, reg_off, data_buf, data_size1, in qcom_nandc_write_page_raw()
2112 write_data_dma(nandc, reg_off, oob_buf, oob_size1, in qcom_nandc_write_page_raw()
2117 write_data_dma(nandc, reg_off, data_buf, data_size2, in qcom_nandc_write_page_raw()
2122 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); in qcom_nandc_write_page_raw()
2125 config_nand_cw_write(nandc); in qcom_nandc_write_page_raw()
2128 ret = submit_descs(nandc); in qcom_nandc_write_page_raw()
2130 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2132 free_descs(nandc); in qcom_nandc_write_page_raw()
2151 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_oob() local
2158 clear_bam_transaction(nandc); in qcom_nandc_write_oob()
2164 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2166 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2172 config_nand_page_write(nandc); in qcom_nandc_write_oob()
2173 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_write_oob()
2174 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2175 config_nand_cw_write(nandc); in qcom_nandc_write_oob()
2177 ret = submit_descs(nandc); in qcom_nandc_write_oob()
2179 free_descs(nandc); in qcom_nandc_write_oob()
2182 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2193 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_bad() local
2207 clear_bam_transaction(nandc); in qcom_nandc_block_bad()
2213 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2219 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2222 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2230 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_markbad() local
2234 clear_read_regs(nandc); in qcom_nandc_block_markbad()
2235 clear_bam_transaction(nandc); in qcom_nandc_block_markbad()
2242 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2251 config_nand_page_write(nandc); in qcom_nandc_block_markbad()
2252 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_block_markbad()
2253 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2254 config_nand_cw_write(nandc); in qcom_nandc_block_markbad()
2256 ret = submit_descs(nandc); in qcom_nandc_block_markbad()
2258 free_descs(nandc); in qcom_nandc_block_markbad()
2261 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2277 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_byte() local
2278 u8 *buf = nandc->data_buffer; in qcom_nandc_read_byte()
2289 if (nandc->buf_start < nandc->buf_count) in qcom_nandc_read_byte()
2290 ret = buf[nandc->buf_start++]; in qcom_nandc_read_byte()
2297 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_buf() local
2298 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_read_buf()
2300 memcpy(buf, nandc->data_buffer + nandc->buf_start, real_len); in qcom_nandc_read_buf()
2301 nandc->buf_start += real_len; in qcom_nandc_read_buf()
2307 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_buf() local
2308 int real_len = min_t(size_t, len, nandc->buf_count - nandc->buf_start); in qcom_nandc_write_buf()
2310 memcpy(nandc->data_buffer + nandc->buf_start, buf, real_len); in qcom_nandc_write_buf()
2312 nandc->buf_start += real_len; in qcom_nandc_write_buf()
2318 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_select_chip() local
2323 dev_warn(nandc->dev, "invalid chip select\n"); in qcom_nandc_select_chip()
2467 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nand_attach_chip() local
2484 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2508 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2555 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2613 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2615 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2618 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2631 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) in qcom_nandc_alloc() argument
2635 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
2637 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
2647 nandc->buf_size = 532; in qcom_nandc_alloc()
2649 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, in qcom_nandc_alloc()
2651 if (!nandc->data_buffer) in qcom_nandc_alloc()
2654 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), in qcom_nandc_alloc()
2656 if (!nandc->regs) in qcom_nandc_alloc()
2659 nandc->reg_read_buf = devm_kcalloc(nandc->dev, in qcom_nandc_alloc()
2660 MAX_REG_RD, sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2662 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
2665 if (nandc->props->is_bam) { in qcom_nandc_alloc()
2666 nandc->reg_read_dma = in qcom_nandc_alloc()
2667 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
2669 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
2671 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
2672 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
2676 nandc->tx_chan = dma_request_slave_channel(nandc->dev, "tx"); in qcom_nandc_alloc()
2677 if (!nandc->tx_chan) { in qcom_nandc_alloc()
2678 dev_err(nandc->dev, "failed to request tx channel\n"); in qcom_nandc_alloc()
2682 nandc->rx_chan = dma_request_slave_channel(nandc->dev, "rx"); in qcom_nandc_alloc()
2683 if (!nandc->rx_chan) { in qcom_nandc_alloc()
2684 dev_err(nandc->dev, "failed to request rx channel\n"); in qcom_nandc_alloc()
2688 nandc->cmd_chan = dma_request_slave_channel(nandc->dev, "cmd"); in qcom_nandc_alloc()
2689 if (!nandc->cmd_chan) { in qcom_nandc_alloc()
2690 dev_err(nandc->dev, "failed to request cmd channel\n"); in qcom_nandc_alloc()
2700 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
2701 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
2702 if (!nandc->bam_txn) { in qcom_nandc_alloc()
2703 dev_err(nandc->dev, in qcom_nandc_alloc()
2708 nandc->chan = dma_request_slave_channel(nandc->dev, "rxtx"); in qcom_nandc_alloc()
2709 if (!nandc->chan) { in qcom_nandc_alloc()
2710 dev_err(nandc->dev, in qcom_nandc_alloc()
2716 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
2717 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
2719 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
2720 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
2725 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) in qcom_nandc_unalloc() argument
2727 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
2728 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
2729 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
2731 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
2734 if (nandc->tx_chan) in qcom_nandc_unalloc()
2735 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
2737 if (nandc->rx_chan) in qcom_nandc_unalloc()
2738 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
2740 if (nandc->cmd_chan) in qcom_nandc_unalloc()
2741 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
2743 if (nandc->chan) in qcom_nandc_unalloc()
2744 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
2749 static int qcom_nandc_setup(struct qcom_nand_controller *nandc) in qcom_nandc_setup() argument
2754 nandc_write(nandc, SFLASHC_BURST_CFG, 0); in qcom_nandc_setup()
2755 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), in qcom_nandc_setup()
2759 if (nandc->props->is_bam) { in qcom_nandc_setup()
2760 nand_ctrl = nandc_read(nandc, NAND_CTRL); in qcom_nandc_setup()
2761 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); in qcom_nandc_setup()
2763 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); in qcom_nandc_setup()
2767 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
2768 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
2773 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, in qcom_nand_host_init_and_register() argument
2779 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
2815 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
2826 if (nandc->props->is_bam) { in qcom_nand_host_init_and_register()
2827 free_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2828 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_host_init_and_register()
2829 if (!nandc->bam_txn) { in qcom_nand_host_init_and_register()
2830 dev_err(nandc->dev, in qcom_nand_host_init_and_register()
2843 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) in qcom_probe_nand_devices() argument
2845 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
2857 ret = qcom_nand_host_init_and_register(nandc, host, child); in qcom_probe_nand_devices()
2863 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
2866 if (list_empty(&nandc->host_list)) in qcom_probe_nand_devices()
2875 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_parse_dt() local
2876 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
2879 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
2881 &nandc->cmd_crci); in qcom_nandc_parse_dt()
2883 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
2888 &nandc->data_crci); in qcom_nandc_parse_dt()
2890 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
2900 struct qcom_nand_controller *nandc; in qcom_nandc_probe() local
2906 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
2907 if (!nandc) in qcom_nandc_probe()
2910 platform_set_drvdata(pdev, nandc); in qcom_nandc_probe()
2911 nandc->dev = dev; in qcom_nandc_probe()
2919 nandc->props = dev_data; in qcom_nandc_probe()
2921 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
2922 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
2923 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
2925 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
2926 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
2927 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
2934 nandc->base = devm_ioremap_resource(dev, res); in qcom_nandc_probe()
2935 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
2936 return PTR_ERR(nandc->base); in qcom_nandc_probe()
2938 nandc->base_phys = res->start; in qcom_nandc_probe()
2939 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
2942 if (!nandc->base_dma) in qcom_nandc_probe()
2945 ret = qcom_nandc_alloc(nandc); in qcom_nandc_probe()
2949 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
2953 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
2957 ret = qcom_nandc_setup(nandc); in qcom_nandc_probe()
2961 ret = qcom_probe_nand_devices(nandc); in qcom_nandc_probe()
2968 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
2970 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
2972 qcom_nandc_unalloc(nandc); in qcom_nandc_probe()
2982 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_remove() local
2986 list_for_each_entry(host, &nandc->host_list, node) in qcom_nandc_remove()
2990 qcom_nandc_unalloc(nandc); in qcom_nandc_remove()
2992 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
2993 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
2995 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()