163  * the NAND controller performs reads/writes with ECC in 516 byte chunks.
177 /* ECC modes supported by the controller */
416  *				of a page, consisting of all data, ecc, spare
419  *				by ECC
420  * @use_ecc:			request the controller to use ECC for the
422  * @bch_enabled:		flag to tell whether BCH ECC mode is used
423  * @ecc_bytes_hw:		ECC bytes used by controller hardware for this
431  *				ecc/non-ecc mode for the current nand flash
460  * @ecc_modes - ecc mode for NAND
1390 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in parse_erase_write_errors()  local
1394 	num_cw = command == NAND_CMD_PAGEPROG ? ecc->steps : 1;  in parse_erase_write_errors()
1440 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_command()  local
1475 		update_rw_regs(host, ecc->steps, true);  in qcom_nandc_command()
1511  * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
1514  * when using RS ECC, the HW reports the same erros when reading an erased CW,
1518  * verify if the page is erased or not, and fix up the page for RS ECC by
1588 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_cw_raw()  local
1600 	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_read_cw_raw()
1603 	if (cw == (ecc->steps - 1)) {  in qcom_nandc_read_cw_raw()
1604 		data_size2 = ecc->size - data_size1 -  in qcom_nandc_read_cw_raw()
1605 			     ((ecc->steps - 1) * 4);  in qcom_nandc_read_cw_raw()
1606 		oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +  in qcom_nandc_read_cw_raw()
1651  * number of 0 in each CW for which ECC engine returns the uncorrectable
1653  * equal to the ecc->strength for each CW.
1661  *    The BBM and spare bytes bit flip won’t affect the ECC so don’t check
1671 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in check_for_erased_page()  local
1683 	for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {  in check_for_erased_page()
1684 		if (cw == (ecc->steps - 1)) {  in check_for_erased_page()
1685 			data_size = ecc->size - ((ecc->steps - 1) * 4);  in check_for_erased_page()
1686 			oob_size = (ecc->steps * 4) + host->ecc_bytes_hw;  in check_for_erased_page()
1694 		cw_oob_buf = oob_buf + (cw * ecc->bytes);  in check_for_erased_page()
1708 						  0, ecc->strength);  in check_for_erased_page()
1722  * errors. this is equivalent to what 'ecc->correct()' would do.
1730 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in parse_read_errors()  local
1740 	for (i = 0; i < ecc->steps; i++, buf++) {  in parse_read_errors()
1744 		if (i == (ecc->steps - 1)) {  in parse_read_errors()
1745 			data_len = ecc->size - ((ecc->steps - 1) << 2);  in parse_read_errors()
1746 			oob_len = ecc->steps << 2;  in parse_read_errors()
1757 		 * Check ECC failure for each codeword. ECC failure can  in parse_read_errors()
1759 		 * 1. If number of bitflips are greater than ECC engine  in parse_read_errors()
1766 			 * For BCH ECC, ignore erased codeword errors, if  in parse_read_errors()
1773 			 * For RS ECC, HW reports the erased CW by placing  in parse_read_errors()
1796 		 * No ECC or operational errors happened. Check the number of  in parse_read_errors()
1810 			oob_buf += oob_len + ecc->bytes;  in parse_read_errors()
1825  * helper to perform the actual page read operation, used by ecc->read_page(),
1826  * ecc->read_oob()
1833 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in read_page_ecc()  local
1840 	for (i = 0; i < ecc->steps; i++) {  in read_page_ecc()
1843 		if (i == (ecc->steps - 1)) {  in read_page_ecc()
1844 			data_size = ecc->size - ((ecc->steps - 1) << 2);  in read_page_ecc()
1845 			oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +  in read_page_ecc()
1872 		 * when ecc is enabled, the controller doesn't read the real  in read_page_ecc()
1874 		 * consistent layout across RAW and ECC reads, we just  in read_page_ecc()
1913 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in copy_last_cw()  local
1924 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in copy_last_cw()
1940 /* implements ecc->read_page() */
1957 /* implements ecc->read_page_raw() */
1963 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_page_raw()  local
1967 	for (cw = 0; cw < ecc->steps; cw++) {  in qcom_nandc_read_page_raw()
1974 		oob_buf += ecc->bytes;  in qcom_nandc_read_page_raw()
1980 /* implements ecc->read_oob() */
1985 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_read_oob()  local
1992 	update_rw_regs(host, ecc->steps, true);  in qcom_nandc_read_oob()
1997 /* implements ecc->write_page() */
2003 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_page()  local
2016 	update_rw_regs(host, ecc->steps, false);  in qcom_nandc_write_page()
2019 	for (i = 0; i < ecc->steps; i++) {  in qcom_nandc_write_page()
2022 		if (i == (ecc->steps - 1)) {  in qcom_nandc_write_page()
2023 			data_size = ecc->size - ((ecc->steps - 1) << 2);  in qcom_nandc_write_page()
2024 			oob_size = (ecc->steps << 2) + host->ecc_bytes_hw +  in qcom_nandc_write_page()
2028 			oob_size = ecc->bytes;  in qcom_nandc_write_page()
2033 			       i == (ecc->steps - 1) ? NAND_BAM_NO_EOT : 0);  in qcom_nandc_write_page()
2036 		 * when ECC is enabled, we don't really need to write anything  in qcom_nandc_write_page()
2038 		 * just contain ECC bytes that's written by the controller  in qcom_nandc_write_page()
2042 		if (i == (ecc->steps - 1)) {  in qcom_nandc_write_page()
2067 /* implements ecc->write_page_raw() */
2075 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_page_raw()  local
2087 	update_rw_regs(host, ecc->steps, false);  in qcom_nandc_write_page_raw()
2090 	for (i = 0; i < ecc->steps; i++) {  in qcom_nandc_write_page_raw()
2094 		data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_write_page_raw()
2097 		if (i == (ecc->steps - 1)) {  in qcom_nandc_write_page_raw()
2098 			data_size2 = ecc->size - data_size1 -  in qcom_nandc_write_page_raw()
2099 				     ((ecc->steps - 1) << 2);  in qcom_nandc_write_page_raw()
2100 			oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +  in qcom_nandc_write_page_raw()
2141  * implements ecc->write_oob()
2144  * since ECC is calculated for the combined codeword. So update the OOB from
2152 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_write_oob()  local
2161 	data_size = ecc->size - ((ecc->steps - 1) << 2);  in qcom_nandc_write_oob()
2169 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in qcom_nandc_write_oob()
2194 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_block_bad()  local
2201 	 * the beginning of the last codeword, we don't care about reading ecc  in qcom_nandc_block_bad()
2217 	bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);  in qcom_nandc_block_bad()
2231 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nandc_block_markbad()  local
2248 	set_address(host, host->cw_size * (ecc->steps - 1), page);  in qcom_nandc_block_markbad()
2329  * Layout with ECC enabled:
2333  * |    DATA   xx..ECC..yy|  |    DATA     **SPARE**xx..ECC..yy|
2341  * . = ECC bytes
2351  * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively.
2352  * the number of ECC bytes vary based on the ECC strength and the bus width.
2355  * 12/16 bytes consist of ECC and reserved data. The nth codeword contains
2358  * When we access a page with ECC enabled, the reserved bytes(s) are not
2363  * Layout with ECC disabled:
2367  * |  DATA1  yy  DATA2   xx..ECC..|  |  DATA1  bb  DATA2   **SPARE**xx..ECC..|
2375  * . = ECC bytes
2382  * when the ECC block is disabled, one reserved byte (or two for 16 bit bus
2386  * In order to have a consistent layout between RAW and ECC modes, we assume
2391  * |yyxx..ECC..|  |bb*FREEOOB*xx..ECC..|
2399  * . = ECC bytes
2401  * y = Dummy bad block byte(s) (inaccessible when ECC enabled)
2403  * b = Real bad block byte(s) (inaccessible when ECC enabled)
2405  * This layout is read as is when ECC is disabled. When ECC is enabled, the
2407  * and assumed as 0xffs when we read a page/oob. The ECC, unused and
2408  * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is
2416 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_ooblayout_ecc()  local
2422 		oobregion->length = (ecc->bytes * (ecc->steps - 1)) +  in qcom_nand_ooblayout_ecc()
2438 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_ooblayout_free()  local
2443 	oobregion->length = ecc->steps * 4;  in qcom_nand_ooblayout_free()
2444 	oobregion->offset = ((ecc->steps - 1) * ecc->bytes) + host->bbm_size;  in qcom_nand_ooblayout_free()
2450 	.ecc = qcom_nand_ooblayout_ecc,
2466 	struct nand_ecc_ctrl *ecc = &chip->ecc;  in qcom_nand_attach_chip()  local
2473 	ecc->size = NANDC_STEP_SIZE;  in qcom_nand_attach_chip()
2478 	 * Each CW has 4 available OOB bytes which will be protected with ECC  in qcom_nand_attach_chip()
2479 	 * so remaining bytes can be used for ECC.  in qcom_nand_attach_chip()
2484 		dev_err(nandc->dev, "No valid ECC settings possible\n");  in qcom_nand_attach_chip()
2488 	if (ecc->strength >= 8) {  in qcom_nand_attach_chip()
2489 		/* 8 bit ECC defaults to BCH ECC on all platforms */  in qcom_nand_attach_chip()
2504 		 * if the controller supports BCH for 4 bit ECC, the controller  in qcom_nand_attach_chip()
2505 		 * uses lesser bytes for ECC. If RS is used, the ECC bytes is  in qcom_nand_attach_chip()
2537 	 * we consider ecc->bytes as the sum of all the non-data content in a  in qcom_nand_attach_chip()
2539 	 * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit  in qcom_nand_attach_chip()
2540 	 * ECC and 12 bytes for 4 bit ECC  in qcom_nand_attach_chip()
2542 	ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size;  in qcom_nand_attach_chip()
2544 	ecc->read_page		= qcom_nandc_read_page;  in qcom_nand_attach_chip()
2545 	ecc->read_page_raw	= qcom_nandc_read_page_raw;  in qcom_nand_attach_chip()
2546 	ecc->read_oob		= qcom_nandc_read_oob;  in qcom_nand_attach_chip()
2547 	ecc->write_page		= qcom_nandc_write_page;  in qcom_nand_attach_chip()
2548 	ecc->write_page_raw	= qcom_nandc_write_page_raw;  in qcom_nand_attach_chip()
2549 	ecc->write_oob		= qcom_nandc_write_oob;  in qcom_nand_attach_chip()
2551 	ecc->mode = NAND_ECC_HW;  in qcom_nand_attach_chip()
2560 	 * spare data with ECC too. We protect spare data by default, so we set  in qcom_nand_attach_chip()
2566 	 * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes  in qcom_nand_attach_chip()
2567 	 * for 8 bit ECC  in qcom_nand_attach_chip()
2569 	host->cw_size = host->cw_data + ecc->bytes;  in qcom_nand_attach_chip()
2621 		host->cw_size, host->cw_data, ecc->strength, ecc->bytes,  in qcom_nand_attach_chip()
2806 	 * of a page with ECC disabled. currently, the nand_base and nand_bbt  in qcom_nand_host_init_and_register()
2807 	 * helpers don't allow us to read BB from a nand chip with ECC  in qcom_nand_host_init_and_register()